[Mesa-dev] [PATCH 2/4] i965: Add more precise cache tracking helpers

[Kenneth Graunke]

On Monday, November 6, 2017 1:38:55 PM PST Jason Ekstrand wrote:
> In theory, this will let us track the depth and render caches
> separately.  Right now, they're just wrappers around
> brw_render_cache_set_*
> ---
>  src/mesa/drivers/dri/i965/brw_draw.c          | 12 +++++------
>  src/mesa/drivers/dri/i965/brw_misc_state.c    |  4 ++--
>  src/mesa/drivers/dri/i965/genX_blorp_exec.c   | 10 ++++-----
>  src/mesa/drivers/dri/i965/intel_fbo.c         | 29 +++++++++++++++++++++++++++
>  src/mesa/drivers/dri/i965/intel_fbo.h         |  6 ++++++
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c |  2 +-
>  6 files changed, 49 insertions(+), 14 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
> index 10b6298..8920b00 100644
> --- a/src/mesa/drivers/dri/i965/brw_draw.c
> +++ b/src/mesa/drivers/dri/i965/brw_draw.c
> @@ -426,7 +426,7 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering)
>                                      min_layer, num_layers,
>                                      disable_aux);
>  
> -      brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
> +      brw_cache_flush_for_read(brw, tex_obj->mt->bo);
>  
>        if (tex_obj->base.StencilSampling ||
>            tex_obj->mt->format == MESA_FORMAT_S_UINT8) {
> @@ -450,7 +450,7 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering)
>  
>                 intel_miptree_prepare_image(brw, tex_obj->mt);
>  
> -               brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
> +               brw_cache_flush_for_read(brw, tex_obj->mt->bo);
>              }
>           }
>        }
> @@ -561,11 +561,11 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
>                                      depth_written);
>        }
>        if (depth_written)
> -         brw_render_cache_set_add_bo(brw, depth_irb->mt->bo);
> +         brw_depth_cache_add_bo(brw, depth_irb->mt->bo);
>     }
>  
>     if (stencil_irb && brw->stencil_write_enabled)
> -      brw_render_cache_set_add_bo(brw, stencil_irb->mt->bo);
> +      brw_depth_cache_add_bo(brw, stencil_irb->mt->bo);
>  
>     for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
>        struct intel_renderbuffer *irb =
> @@ -578,7 +578,7 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
>           _mesa_get_render_format(ctx, intel_rb_format(irb));
>        enum isl_format isl_format = brw_isl_format_for_mesa_format(mesa_format);
>  
> -      brw_render_cache_set_add_bo(brw, irb->mt->bo);
> +      brw_render_cache_add_bo(brw, irb->mt->bo);
>        intel_miptree_finish_render(brw, irb->mt, irb->mt_level,
>                                    irb->mt_layer, irb->layer_count,
>                                    isl_format,
> @@ -593,7 +593,7 @@ intel_renderbuffer_move_temp_back(struct brw_context *brw,
>     if (irb->align_wa_mt == NULL)
>        return;
>  
> -   brw_render_cache_set_check_flush(brw, irb->align_wa_mt->bo);
> +   brw_cache_flush_for_read(brw, irb->align_wa_mt->bo);
>  
>     intel_miptree_copy_slice(brw, irb->align_wa_mt, 0, 0,
>                              irb->mt,
> diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
> index 53137cc..fd96485 100644
> --- a/src/mesa/drivers/dri/i965/brw_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
> @@ -333,9 +333,9 @@ brw_emit_depthbuffer(struct brw_context *brw)
>     }
>  
>     if (depth_mt)
> -      brw_render_cache_set_check_flush(brw, depth_mt->bo);
> +      brw_cache_flush_for_depth(brw, depth_mt->bo);
>     if (stencil_mt)
> -      brw_render_cache_set_check_flush(brw, stencil_mt->bo);
> +      brw_cache_flush_for_depth(brw, stencil_mt->bo);
>  
>     brw->vtbl.emit_depth_stencil_hiz(brw, depth_mt, depth_offset,
>                                      depthbuffer_format, depth_surface_type,
> diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> index 3c7a7b4..296a83b 100644
> --- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> +++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> @@ -215,8 +215,8 @@ genX(blorp_exec)(struct blorp_batch *batch,
>      * data.
>      */
>     if (params->src.enabled)
> -      brw_render_cache_set_check_flush(brw, params->src.addr.buffer);
> -   brw_render_cache_set_check_flush(brw, params->dst.addr.buffer);
> +      brw_cache_flush_for_read(brw, params->src.addr.buffer);
> +   brw_cache_flush_for_render(brw, params->dst.addr.buffer);

This drops the cache flush, because brw_cache_flush_for_render
is an empty function.  I don't think you intended to do that.

You probably want brw_cache_flush_for_render to do
brw_render_cache_set_check_flush until patch 4.

Otherwise, the series is:
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
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