[Mesa-dev] [PATCH] radeonsi: remove has_cp_dma, has_streamout flags (v2)
Nicolai Hähnle
nhaehnle at gmail.com
Tue Nov 14 16:17:21 UTC 2017
On 09.11.2017 17:34, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> v2: remove r600_can_dma_copy_buffer
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
> ---
> src/gallium/drivers/radeon/r600_buffer_common.c | 17 ++---------------
> src/gallium/drivers/radeon/r600_pipe_common.h | 2 --
> src/gallium/drivers/radeonsi/si_pipe.c | 3 ---
> 3 files changed, 2 insertions(+), 20 deletions(-)
>
> diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
> index f0cfd09..770f4e9 100644
> --- a/src/gallium/drivers/radeon/r600_buffer_common.c
> +++ b/src/gallium/drivers/radeon/r600_buffer_common.c
> @@ -342,31 +342,20 @@ static void *r600_buffer_get_transfer(struct pipe_context *ctx,
> transfer->b.b.box = *box;
> transfer->b.b.stride = 0;
> transfer->b.b.layer_stride = 0;
> transfer->b.staging = NULL;
> transfer->offset = offset;
> transfer->staging = staging;
> *ptransfer = &transfer->b.b;
> return data;
> }
>
> -static bool r600_can_dma_copy_buffer(struct r600_common_context *rctx,
> - unsigned dstx, unsigned srcx, unsigned size)
> -{
> - bool dword_aligned = !(dstx % 4) && !(srcx % 4) && !(size % 4);
> -
> - return rctx->screen->has_cp_dma ||
> - (dword_aligned && (rctx->dma.cs ||
> - rctx->screen->has_streamout));
> -
> -}
> -
> static void *r600_buffer_transfer_map(struct pipe_context *ctx,
> struct pipe_resource *resource,
> unsigned level,
> unsigned usage,
> const struct pipe_box *box,
> struct pipe_transfer **ptransfer)
> {
> struct r600_common_context *rctx = (struct r600_common_context*)ctx;
> struct r600_resource *rbuffer = r600_resource(resource);
> uint8_t *data;
> @@ -429,22 +418,21 @@ static void *r600_buffer_transfer_map(struct pipe_context *ctx,
> /* At this point, the buffer is always idle. */
> usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
> } else {
> /* Fall back to a temporary buffer. */
> usage |= PIPE_TRANSFER_DISCARD_RANGE;
> }
> }
>
> if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
> ((!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
> - PIPE_TRANSFER_PERSISTENT)) &&
> - r600_can_dma_copy_buffer(rctx, box->x, 0, box->width)) ||
> + PIPE_TRANSFER_PERSISTENT))) ||
> (rbuffer->flags & RADEON_FLAG_SPARSE))) {
> assert(usage & PIPE_TRANSFER_WRITE);
>
> /* Check if mapping this buffer would cause waiting for the GPU.
> */
> if (rbuffer->flags & RADEON_FLAG_SPARSE ||
> force_discard_range ||
> si_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
> !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
> /* Do a wait-free write-only transfer using a temporary buffer. */
> @@ -466,22 +454,21 @@ static void *r600_buffer_transfer_map(struct pipe_context *ctx,
> }
> } else {
> /* At this point, the buffer is always idle (we checked it above). */
> usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
> }
> }
> /* Use a staging buffer in cached GTT for reads. */
> else if (((usage & PIPE_TRANSFER_READ) &&
> !(usage & PIPE_TRANSFER_PERSISTENT) &&
> (rbuffer->domains & RADEON_DOMAIN_VRAM ||
> - rbuffer->flags & RADEON_FLAG_GTT_WC) &&
> - r600_can_dma_copy_buffer(rctx, 0, box->x, box->width)) ||
> + rbuffer->flags & RADEON_FLAG_GTT_WC)) ||
> (rbuffer->flags & RADEON_FLAG_SPARSE)) {
> struct r600_resource *staging;
>
> assert(!(usage & TC_TRANSFER_MAP_THREADED_UNSYNC));
> staging = (struct r600_resource*) pipe_buffer_create(
> ctx->screen, 0, PIPE_USAGE_STAGING,
> box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT));
> if (staging) {
> /* Copy the VRAM buffer to the staging buffer. */
> rctx->dma_copy(ctx, &staging->b.b, 0,
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
> index 1219a86..adfcc7c 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.h
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.h
> @@ -384,22 +384,20 @@ struct r600_memory_object {
> uint32_t offset;
> };
>
> struct r600_common_screen {
> struct pipe_screen b;
> struct radeon_winsys *ws;
> enum radeon_family family;
> enum chip_class chip_class;
> struct radeon_info info;
> uint64_t debug_flags;
> - bool has_cp_dma;
> - bool has_streamout;
> bool has_rbplus; /* if RB+ registers exist */
> bool rbplus_allowed; /* if RB+ is allowed */
>
> struct disk_cache *disk_shader_cache;
>
> struct slab_parent_pool pool_transfers;
>
> /* Texture filter settings. */
> int force_aniso; /* -1 = disabled */
>
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
> index 3f22e39..89a1782 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -1114,23 +1114,20 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
> sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
> !(sscreen->b.debug_flags & DBG(NO_DFSM));
> }
>
> /* While it would be nice not to have this flag, we are constrained
> * by the reality that LLVM 5.0 doesn't have working VGPR indexing
> * on GFX9.
> */
> sscreen->llvm_has_working_vgpr_indexing = sscreen->b.chip_class <= VI;
>
> - sscreen->b.has_cp_dma = true;
> - sscreen->b.has_streamout = true;
> -
> /* Some chips have RB+ registers, but don't support RB+. Those must
> * always disable it.
> */
> if (sscreen->b.family == CHIP_STONEY ||
> sscreen->b.chip_class >= GFX9) {
> sscreen->b.has_rbplus = true;
>
> sscreen->b.rbplus_allowed =
> !(sscreen->b.debug_flags & DBG(NO_RB_PLUS)) &&
> (sscreen->b.family == CHIP_STONEY ||
>
--
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.
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