[Mesa-dev] [PATCH] i965: Implement another VF cache invalidate workaround on Gen8+.

[Rafael Antognolli]

Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>

On Tue, Nov 14, 2017 at 03:24:36PM -0800, Kenneth Graunke wrote:
> ...and provide a better citation for the existing one.
> 
> v2:
> - Apply the workaround to Gen8 too, as intended (caught by Topi).
> - Restructure to add bits instead of an extra flush (based on a similar
>   patch by Rafael Antognolli).
> ---
>  src/mesa/drivers/dri/i965/brw_pipe_control.c | 41 ++++++++++++++++++++++------
>  1 file changed, 33 insertions(+), 8 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
> index 39e8bff7309..c6e7dd15f4c 100644
> --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
> +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
> @@ -119,14 +119,39 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t flags,
>        if (devinfo->gen == 8)
>           gen8_add_cs_stall_workaround_bits(&flags);
>  
> -      if (devinfo->gen == 9 &&
> -          (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) {
> -         /* Hardware workaround: SKL
> -          *
> -          * Emit Pipe Control with all bits set to zero before emitting
> -          * a Pipe Control with VF Cache Invalidate set.
> -          */
> -         brw_emit_pipe_control_flush(brw, 0);
> +      if (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE) {
> +         if (devinfo->gen == 9) {
> +            /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
> +             * lists several workarounds:
> +             *
> +             *    "Project: SKL, KBL, BXT
> +             *
> +             *     If the VF Cache Invalidation Enable is set to a 1 in a
> +             *     PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
> +             *     sets to 0, with the VF Cache Invalidation Enable set to 0
> +             *     needs to be sent prior to the PIPE_CONTROL with VF Cache
> +             *     Invalidation Enable set to a 1."
> +             */
> +            brw_emit_pipe_control_flush(brw, 0);
> +         }
> +
> +         if (devinfo->gen >= 8) {
> +            /* THE PIPE_CONTROL "VF Cache Invalidation Enable" docs continue:
> +             *
> +             *    "Project: BDW+
> +             *
> +             *     When VF Cache Invalidate is set “Post Sync Operation” must
> +             *     be enabled to “Write Immediate Data” or “Write PS Depth
> +             *     Count” or “Write Timestamp”."
> +             *
> +             * If there's a BO, we're already doing some kind of write.
> +             * If not, add a write to the workaround BO.
> +             */
> +            if (!bo) {
> +               flags |= PIPE_CONTROL_WRITE_IMMEDIATE;
> +               bo = brw->workaround_bo;
> +            }
> +         }
>        }
>  
>        if (devinfo->gen == 10)
> -- 
> 2.15.0
> 
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