[Mesa-dev] V3 More linking optimisations

[Timothy Arceri]

V3: Some small fixes to allow these passes to work with the radeonsi
nir backend.

V2: This is a resend/rebddase of the series I sent a couple of weeks ago,
its rebased on some of Jason's changes to i965 NIR linking that
landed in master.

This series adds a varying array splitting pass as well a previous
component packing series I sent out previously. This allows avoiding the
workaround of calling gather shader info twice since we can more easily
keep the input/output bitmasks in sync now that we don't need to worry
about partial marking of arrays.

Remaining improvements include adding a pass to compact varyings into
consecutive
slots rather than leaving empty slots when removing dead varyings.

Radv results:

SaschaWillems Vulkan demo tessellation:

~4000fps -> ~4600fps

Shader-db results for serires on i965 (BDW):

total instructions in shared programs: 13298718 -> 13191284 (-0.81%)
instructions in affected programs: 2315180 -> 2207746 (-4.64%)
helped: 14956
HURT: 390

total cycles in shared programs: 540151400 -> 539397048 (-0.14%)
cycles in affected programs: 297905258 -> 297150906 (-0.25%)
helped: 25231
HURT: 13033

total loops in shared programs: 3807 -> 3804 (-0.08%)
loops in affected programs: 3 -> 0
helped: 3
HURT: 0

total spills in shared programs: 86577 -> 86640 (0.07%)
spills in affected programs: 1380 -> 1443 (4.57%)
helped: 7
HURT: 15

total fills in shared programs: 90871 -> 90946 (0.08%)
fills in affected programs: 1728 -> 1803 (4.34%)
helped: 16
HURT: 9

LOST:   4
GAINED: 15

The spill hurt is all in dolphin uber shaders (as is most of the spill
improvements).

Two of the lost programs are SIMD16 programs are from CS: GO because 80% of the
shaders get optimised away when we remove dead varying components, these are
also the shaders where the 3 loops go away.

Please review.