[Mesa-dev] [PATCH 1/8] amd/common: sid.h cleanups
Nicolai Hähnle
nhaehnle at gmail.com
Tue Nov 21 15:03:21 UTC 2017
From: Nicolai Hähnle <nicolai.haehnle at amd.com>
Fix a bunch of labels indicating when registers were added/removed
and normalize the SI-class GRBM_GFX_INDEX.
---
src/amd/common/sid.h | 42 +++++++++++++++++++++++----------
src/amd/vulkan/si_cmd_buffer.c | 14 ++++++-----
src/gallium/drivers/radeonsi/si_state.c | 2 +-
3 files changed, 38 insertions(+), 20 deletions(-)
diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h
index 15ebd9b267f..59a7e2a06e6 100644
--- a/src/amd/common/sid.h
+++ b/src/amd/common/sid.h
@@ -691,27 +691,28 @@
#define C_008010_CP_COHERENCY_BUSY 0xEFFFFFFF
#define S_008010_CP_BUSY(x) (((unsigned)(x) & 0x1) << 29)
#define G_008010_CP_BUSY(x) (((x) >> 29) & 0x1)
#define C_008010_CP_BUSY 0xDFFFFFFF
#define S_008010_CB_BUSY(x) (((unsigned)(x) & 0x1) << 30)
#define G_008010_CB_BUSY(x) (((x) >> 30) & 0x1)
#define C_008010_CB_BUSY 0xBFFFFFFF
#define S_008010_GUI_ACTIVE(x) (((unsigned)(x) & 0x1) << 31)
#define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 0x1)
#define C_008010_GUI_ACTIVE 0x7FFFFFFF
-#define GRBM_GFX_INDEX 0x802C
-#define INSTANCE_INDEX(x) ((x) << 0)
-#define SH_INDEX(x) ((x) << 8)
-#define SE_INDEX(x) ((x) << 16)
-#define SH_BROADCAST_WRITES (1 << 29)
-#define INSTANCE_BROADCAST_WRITES (1 << 30)
-#define SE_BROADCAST_WRITES (1 << 31)
+/* not on CIK -- moved to uconfig space */
+#define R_00802C_GRBM_GFX_INDEX 0x802C
+#define S_00802C_INSTANCE_INDEX(x) (((unsigned)(x) & 0xFF) << 0)
+#define S_00802C_SH_INDEX(x) (((unsigned)(x) & 0xFF) << 8)
+#define S_00802C_SE_INDEX(x) (((unsigned)(x) & 0xFF) << 16)
+#define S_00802C_SH_BROADCAST_WRITES(x) (((unsigned)(x) & 0x1) << 29)
+#define S_00802C_INSTANCE_BROADCAST_WRITES(x) (((unsigned)(x) & 0x1) << 30)
+#define S_00802C_SE_BROADCAST_WRITES(x) (((unsigned)(x) & 0x1) << 31)
#define R_0084FC_CP_STRMOUT_CNTL 0x0084FC
#define S_0084FC_OFFSET_UPDATE_DONE(x) (((unsigned)(x) & 0x1) << 0)
#define R_0085F0_CP_COHER_CNTL 0x0085F0
#define S_0085F0_DEST_BASE_0_ENA(x) (((unsigned)(x) & 0x1) << 0)
#define G_0085F0_DEST_BASE_0_ENA(x) (((x) >> 0) & 0x1)
#define C_0085F0_DEST_BASE_0_ENA 0xFFFFFFFE
#define S_0085F0_DEST_BASE_1_ENA(x) (((unsigned)(x) & 0x1) << 1)
#define G_0085F0_DEST_BASE_1_ENA(x) (((x) >> 1) & 0x1)
#define C_0085F0_DEST_BASE_1_ENA 0xFFFFFFFD
#define S_0085F0_CB0_DEST_BASE_ENA(x) (((unsigned)(x) & 0x1) << 6)
@@ -760,20 +761,21 @@
#define G_0085F0_DB_ACTION_ENA(x) (((x) >> 26) & 0x1)
#define C_0085F0_DB_ACTION_ENA 0xFBFFFFFF
#define S_0085F0_SH_KCACHE_ACTION_ENA(x) (((unsigned)(x) & 0x1) << 27)
#define G_0085F0_SH_KCACHE_ACTION_ENA(x) (((x) >> 27) & 0x1)
#define C_0085F0_SH_KCACHE_ACTION_ENA 0xF7FFFFFF
#define S_0085F0_SH_ICACHE_ACTION_ENA(x) (((unsigned)(x) & 0x1) << 29)
#define G_0085F0_SH_ICACHE_ACTION_ENA(x) (((x) >> 29) & 0x1)
#define C_0085F0_SH_ICACHE_ACTION_ENA 0xDFFFFFFF
#define R_0085F4_CP_COHER_SIZE 0x0085F4
#define R_0085F8_CP_COHER_BASE 0x0085F8
+/* */
#define R_008014_GRBM_STATUS_SE0 0x008014
#define S_008014_DB_CLEAN(x) (((unsigned)(x) & 0x1) << 1)
#define G_008014_DB_CLEAN(x) (((x) >> 1) & 0x1)
#define C_008014_DB_CLEAN 0xFFFFFFFD
#define S_008014_CB_CLEAN(x) (((unsigned)(x) & 0x1) << 2)
#define G_008014_CB_CLEAN(x) (((x) >> 2) & 0x1)
#define C_008014_CB_CLEAN 0xFFFFFFFB
#define S_008014_BCI_BUSY(x) (((unsigned)(x) & 0x1) << 22)
#define G_008014_BCI_BUSY(x) (((x) >> 22) & 0x1)
#define C_008014_BCI_BUSY 0xFFBFFFFF
@@ -994,36 +996,37 @@
#define S_0301F0_SH_ICACHE_ACTION_ENA(x) (((unsigned)(x) & 0x1) << 29)
#define G_0301F0_SH_ICACHE_ACTION_ENA(x) (((x) >> 29) & 0x1)
#define C_0301F0_SH_ICACHE_ACTION_ENA 0xDFFFFFFF
/* VI */
#define S_0301F0_SH_KCACHE_WB_ACTION_ENA(x) (((unsigned)(x) & 0x1) << 30)
#define G_0301F0_SH_KCACHE_WB_ACTION_ENA(x) (((x) >> 30) & 0x1)
#define C_0301F0_SH_KCACHE_WB_ACTION_ENA 0xBFFFFFFF
#define S_0301F0_SH_SD_ACTION_ENA(x) (((unsigned)(x) & 0x1) << 31)
#define G_0301F0_SH_SD_ACTION_ENA(x) (((x) >> 31) & 0x1)
#define C_0301F0_SH_SD_ACTION_ENA 0x7FFFFFFF
-/* */
+/* CIK */
#define R_0301F4_CP_COHER_SIZE 0x0301F4
#define R_0301F8_CP_COHER_BASE 0x0301F8
#define R_0301FC_CP_COHER_STATUS 0x0301FC
#define S_0301FC_MATCHING_GFX_CNTX(x) (((unsigned)(x) & 0xFF) << 0)
#define G_0301FC_MATCHING_GFX_CNTX(x) (((x) >> 0) & 0xFF)
#define C_0301FC_MATCHING_GFX_CNTX 0xFFFFFF00
#define S_0301FC_MEID(x) (((unsigned)(x) & 0x03) << 24)
#define G_0301FC_MEID(x) (((x) >> 24) & 0x03)
#define C_0301FC_MEID 0xFCFFFFFF
#define S_0301FC_PHASE1_STATUS(x) (((unsigned)(x) & 0x1) << 30)
#define G_0301FC_PHASE1_STATUS(x) (((x) >> 30) & 0x1)
#define C_0301FC_PHASE1_STATUS 0xBFFFFFFF
#define S_0301FC_STATUS(x) (((unsigned)(x) & 0x1) << 31)
#define G_0301FC_STATUS(x) (((x) >> 31) & 0x1)
#define C_0301FC_STATUS 0x7FFFFFFF
+/* */
#define R_008210_CP_CPC_STATUS 0x008210
#define S_008210_MEC1_BUSY(x) (((unsigned)(x) & 0x1) << 0)
#define G_008210_MEC1_BUSY(x) (((x) >> 0) & 0x1)
#define C_008210_MEC1_BUSY 0xFFFFFFFE
#define S_008210_MEC2_BUSY(x) (((unsigned)(x) & 0x1) << 1)
#define G_008210_MEC2_BUSY(x) (((x) >> 1) & 0x1)
#define C_008210_MEC2_BUSY 0xFFFFFFFD
#define S_008210_DC0_BUSY(x) (((unsigned)(x) & 0x1) << 2)
#define G_008210_DC0_BUSY(x) (((x) >> 2) & 0x1)
#define C_008210_DC0_BUSY 0xFFFFFFFB
@@ -1389,26 +1392,29 @@
#define R_0088C4_VGT_CACHE_INVALIDATION 0x0088C4
#define S_0088C4_VS_NO_EXTRA_BUFFER(x) (((unsigned)(x) & 0x1) << 5)
#define G_0088C4_VS_NO_EXTRA_BUFFER(x) (((x) >> 5) & 0x1)
#define C_0088C4_VS_NO_EXTRA_BUFFER 0xFFFFFFDF
#define S_0088C4_STREAMOUT_FULL_FLUSH(x) (((unsigned)(x) & 0x1) << 13)
#define G_0088C4_STREAMOUT_FULL_FLUSH(x) (((x) >> 13) & 0x1)
#define C_0088C4_STREAMOUT_FULL_FLUSH 0xFFFFDFFF
#define S_0088C4_ES_LIMIT(x) (((unsigned)(x) & 0x1F) << 16)
#define G_0088C4_ES_LIMIT(x) (((x) >> 16) & 0x1F)
#define C_0088C4_ES_LIMIT 0xFFE0FFFF
+/* not on CIK -- moved to uconfig space */
#define R_0088C8_VGT_ESGS_RING_SIZE 0x0088C8
#define R_0088CC_VGT_GSVS_RING_SIZE 0x0088CC
+/* */
#define R_0088D4_VGT_GS_VERTEX_REUSE 0x0088D4
#define S_0088D4_VERT_REUSE(x) (((unsigned)(x) & 0x1F) << 0)
#define G_0088D4_VERT_REUSE(x) (((x) >> 0) & 0x1F)
#define C_0088D4_VERT_REUSE 0xFFFFFFE0
+/* not on CIK -- moved to uconfig space */
#define R_008958_VGT_PRIMITIVE_TYPE 0x008958
#define S_008958_PRIM_TYPE(x) (((unsigned)(x) & 0x3F) << 0)
#define G_008958_PRIM_TYPE(x) (((x) >> 0) & 0x3F)
#define C_008958_PRIM_TYPE 0xFFFFFFC0
#define V_008958_DI_PT_NONE 0x00
#define V_008958_DI_PT_POINTLIST 0x01
#define V_008958_DI_PT_LINELIST 0x02
#define V_008958_DI_PT_LINESTRIP 0x03
#define V_008958_DI_PT_TRILIST 0x04
#define V_008958_DI_PT_TRIFAN 0x05
@@ -1449,44 +1455,47 @@
#define R_008974_VGT_NUM_INSTANCES 0x008974
#define R_008988_VGT_TF_RING_SIZE 0x008988
#define S_008988_SIZE(x) (((unsigned)(x) & 0xFFFF) << 0)
#define G_008988_SIZE(x) (((x) >> 0) & 0xFFFF)
#define C_008988_SIZE 0xFFFF0000
#define R_0089B0_VGT_HS_OFFCHIP_PARAM 0x0089B0
#define S_0089B0_OFFCHIP_BUFFERING(x) (((unsigned)(x) & 0x7F) << 0)
#define G_0089B0_OFFCHIP_BUFFERING(x) (((x) >> 0) & 0x7F)
#define C_0089B0_OFFCHIP_BUFFERING 0xFFFFFF80
#define R_0089B8_VGT_TF_MEMORY_BASE 0x0089B8
+/* */
#define R_008A14_PA_CL_ENHANCE 0x008A14
#define S_008A14_CLIP_VTX_REORDER_ENA(x) (((unsigned)(x) & 0x1) << 0)
#define G_008A14_CLIP_VTX_REORDER_ENA(x) (((x) >> 0) & 0x1)
#define C_008A14_CLIP_VTX_REORDER_ENA 0xFFFFFFFE
#define S_008A14_NUM_CLIP_SEQ(x) (((unsigned)(x) & 0x03) << 1)
#define G_008A14_NUM_CLIP_SEQ(x) (((x) >> 1) & 0x03)
#define C_008A14_NUM_CLIP_SEQ 0xFFFFFFF9
#define S_008A14_CLIPPED_PRIM_SEQ_STALL(x) (((unsigned)(x) & 0x1) << 3)
#define G_008A14_CLIPPED_PRIM_SEQ_STALL(x) (((x) >> 3) & 0x1)
#define C_008A14_CLIPPED_PRIM_SEQ_STALL 0xFFFFFFF7
#define S_008A14_VE_NAN_PROC_DISABLE(x) (((unsigned)(x) & 0x1) << 4)
#define G_008A14_VE_NAN_PROC_DISABLE(x) (((x) >> 4) & 0x1)
#define C_008A14_VE_NAN_PROC_DISABLE 0xFFFFFFEF
+/* not on CIK -- moved to uconfig space */
#define R_008A60_PA_SU_LINE_STIPPLE_VALUE 0x008A60
#define S_008A60_LINE_STIPPLE_VALUE(x) (((unsigned)(x) & 0xFFFFFF) << 0)
#define G_008A60_LINE_STIPPLE_VALUE(x) (((x) >> 0) & 0xFFFFFF)
#define C_008A60_LINE_STIPPLE_VALUE 0xFF000000
#define R_008B10_PA_SC_LINE_STIPPLE_STATE 0x008B10
#define S_008B10_CURRENT_PTR(x) (((unsigned)(x) & 0x0F) << 0)
#define G_008B10_CURRENT_PTR(x) (((x) >> 0) & 0x0F)
#define C_008B10_CURRENT_PTR 0xFFFFFFF0
#define S_008B10_CURRENT_COUNT(x) (((unsigned)(x) & 0xFF) << 8)
#define G_008B10_CURRENT_COUNT(x) (((x) >> 8) & 0xFF)
#define C_008B10_CURRENT_COUNT 0xFFFF00FF
+/* */
#define R_008670_CP_STALLED_STAT3 0x008670
#define S_008670_CE_TO_CSF_NOT_RDY_TO_RCV(x) (((unsigned)(x) & 0x1) << 0)
#define G_008670_CE_TO_CSF_NOT_RDY_TO_RCV(x) (((x) >> 0) & 0x1)
#define C_008670_CE_TO_CSF_NOT_RDY_TO_RCV 0xFFFFFFFE
#define S_008670_CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV(x) (((unsigned)(x) & 0x1) << 1)
#define G_008670_CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV(x) (((x) >> 1) & 0x1)
#define C_008670_CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV 0xFFFFFFFD
#define S_008670_CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER(x) (((unsigned)(x) & 0x1) << 2)
#define G_008670_CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER(x) (((x) >> 2) & 0x1)
#define C_008670_CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER 0xFFFFFFFB
@@ -1885,20 +1894,21 @@
#define C_008BF0_DISABLE_SCISSOR_FIX 0xFFFFFFDF
#define S_008BF0_DISABLE_PW_BUBBLE_COLLAPSE(x) (((unsigned)(x) & 0x03) << 6)
#define G_008BF0_DISABLE_PW_BUBBLE_COLLAPSE(x) (((x) >> 6) & 0x03)
#define C_008BF0_DISABLE_PW_BUBBLE_COLLAPSE 0xFFFFFF3F
#define S_008BF0_SEND_UNLIT_STILES_TO_PACKER(x) (((unsigned)(x) & 0x1) << 8)
#define G_008BF0_SEND_UNLIT_STILES_TO_PACKER(x) (((x) >> 8) & 0x1)
#define C_008BF0_SEND_UNLIT_STILES_TO_PACKER 0xFFFFFEFF
#define S_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION(x) (((unsigned)(x) & 0x1) << 9)
#define G_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION(x) (((x) >> 9) & 0x1)
#define C_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION 0xFFFFFDFF
+/* not on CIK */
#define R_008C08_SQC_CACHES 0x008C08
#define S_008C08_INST_INVALIDATE(x) (((unsigned)(x) & 0x1) << 0)
#define G_008C08_INST_INVALIDATE(x) (((x) >> 0) & 0x1)
#define C_008C08_INST_INVALIDATE 0xFFFFFFFE
#define S_008C08_DATA_INVALIDATE(x) (((unsigned)(x) & 0x1) << 1)
#define G_008C08_DATA_INVALIDATE(x) (((x) >> 1) & 0x1)
#define C_008C08_DATA_INVALIDATE 0xFFFFFFFD
/* CIK */
#define R_030D20_SQC_CACHES 0x030D20
#define S_030D20_INST_INVALIDATE(x) (((unsigned)(x) & 0x1) << 0)
@@ -1939,31 +1949,33 @@
#define S_008DFC_DONE(x) (((unsigned)(x) & 0x1) << 11)
#define G_008DFC_DONE(x) (((x) >> 11) & 0x1)
#define C_008DFC_DONE 0xFFFFF7FF
#define S_008DFC_VM(x) (((unsigned)(x) & 0x1) << 12)
#define G_008DFC_VM(x) (((x) >> 12) & 0x1)
#define C_008DFC_VM 0xFFFFEFFF
#define S_008DFC_ENCODING(x) (((unsigned)(x) & 0x3F) << 26)
#define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
#define C_008DFC_ENCODING 0x03FFFFFF
#define V_008DFC_SQ_ENC_EXP_FIELD 0x3E
+/* CIK */
#define R_030E00_TA_CS_BC_BASE_ADDR 0x030E00
#define R_030E04_TA_CS_BC_BASE_ADDR_HI 0x030E04
#define S_030E04_ADDRESS(x) (((unsigned)(x) & 0xFF) << 0)
#define G_030E04_ADDRESS(x) (((x) >> 0) & 0xFF)
#define C_030E04_ADDRESS 0xFFFFFF00
#define R_030F00_DB_OCCLUSION_COUNT0_LOW 0x030F00
-#define R_008F00_SQ_BUF_RSRC_WORD0 0x008F00
#define R_030F04_DB_OCCLUSION_COUNT0_HI 0x030F04
#define S_030F04_COUNT_HI(x) (((unsigned)(x) & 0x7FFFFFFF) << 0)
#define G_030F04_COUNT_HI(x) (((x) >> 0) & 0x7FFFFFFF)
#define C_030F04_COUNT_HI 0x80000000
+/* */
+#define R_008F00_SQ_BUF_RSRC_WORD0 0x008F00
#define R_008F04_SQ_BUF_RSRC_WORD1 0x008F04
#define S_008F04_BASE_ADDRESS_HI(x) (((unsigned)(x) & 0xFFFF) << 0)
#define G_008F04_BASE_ADDRESS_HI(x) (((x) >> 0) & 0xFFFF)
#define C_008F04_BASE_ADDRESS_HI 0xFFFF0000
#define S_008F04_STRIDE(x) (((unsigned)(x) & 0x3FFF) << 16)
#define G_008F04_STRIDE(x) (((x) >> 16) & 0x3FFF)
#define C_008F04_STRIDE 0xC000FFFF
#define S_008F04_CACHE_SWIZZLE(x) (((unsigned)(x) & 0x1) << 30)
#define G_008F04_CACHE_SWIZZLE(x) (((x) >> 30) & 0x1)
#define C_008F04_CACHE_SWIZZLE 0xBFFFFFFF
@@ -2506,30 +2518,31 @@
#define S_0090E4_GS_CU_EN(x) (((unsigned)(x) & 0xFFFF) << 0)
#define G_0090E4_GS_CU_EN(x) (((x) >> 0) & 0xFFFF)
#define C_0090E4_GS_CU_EN 0xFFFF0000
#define S_0090E4_ES_CU_EN(x) (((unsigned)(x) & 0xFFFF) << 16)
#define G_0090E4_ES_CU_EN(x) (((x) >> 16) & 0xFFFF)
#define C_0090E4_ES_CU_EN 0x0000FFFF
#define R_0090E8_SPI_STATIC_THREAD_MGMT_3 0x0090E8 /* not on CIK */
#define S_0090E8_LSHS_CU_EN(x) (((unsigned)(x) & 0xFFFF) << 0)
#define G_0090E8_LSHS_CU_EN(x) (((x) >> 0) & 0xFFFF)
#define C_0090E8_LSHS_CU_EN 0xFFFF0000
+/* not on CIK */
#define R_0090EC_SPI_PS_MAX_WAVE_ID 0x0090EC
#define S_0090EC_MAX_WAVE_ID(x) (((unsigned)(x) & 0xFFF) << 0)
#define G_0090EC_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF)
#define C_0090EC_MAX_WAVE_ID 0xFFFFF000
/* CIK */
#define R_0090E8_SPI_PS_MAX_WAVE_ID 0x0090E8
#define S_0090E8_MAX_WAVE_ID(x) (((unsigned)(x) & 0xFFF) << 0)
#define G_0090E8_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF)
#define C_0090E8_MAX_WAVE_ID 0xFFFFF000
-/* */
+/* not on CIK */
#define R_0090F0_SPI_ARB_PRIORITY 0x0090F0
#define S_0090F0_RING_ORDER_TS0(x) (((unsigned)(x) & 0x07) << 0)
#define G_0090F0_RING_ORDER_TS0(x) (((x) >> 0) & 0x07)
#define C_0090F0_RING_ORDER_TS0 0xFFFFFFF8
#define V_0090F0_X_R0 0x00
#define S_0090F0_RING_ORDER_TS1(x) (((unsigned)(x) & 0x07) << 3)
#define G_0090F0_RING_ORDER_TS1(x) (((x) >> 3) & 0x07)
#define C_0090F0_RING_ORDER_TS1 0xFFFFFFC7
#define S_0090F0_RING_ORDER_TS2(x) (((unsigned)(x) & 0x07) << 6)
#define G_0090F0_RING_ORDER_TS2(x) (((x) >> 6) & 0x07)
@@ -2553,22 +2566,22 @@
#define C_00C700_TS0_DUR_MULT 0xFFFFCFFF
#define S_00C700_TS1_DUR_MULT(x) (((unsigned)(x) & 0x03) << 14)
#define G_00C700_TS1_DUR_MULT(x) (((x) >> 14) & 0x03)
#define C_00C700_TS1_DUR_MULT 0xFFFF3FFF
#define S_00C700_TS2_DUR_MULT(x) (((unsigned)(x) & 0x03) << 16)
#define G_00C700_TS2_DUR_MULT(x) (((x) >> 16) & 0x03)
#define C_00C700_TS2_DUR_MULT 0xFFFCFFFF
#define S_00C700_TS3_DUR_MULT(x) (((unsigned)(x) & 0x03) << 18)
#define G_00C700_TS3_DUR_MULT(x) (((x) >> 18) & 0x03)
#define C_00C700_TS3_DUR_MULT 0xFFF3FFFF
-/* */
-#define R_0090F4_SPI_ARB_CYCLES_0 0x0090F4 /* moved to 0xC704 on CIK */
+/* not on CIK */
+#define R_0090F4_SPI_ARB_CYCLES_0 0x0090F4 /* moved to 0xC704 on CIK*/
#define S_0090F4_TS0_DURATION(x) (((unsigned)(x) & 0xFFFF) << 0)
#define G_0090F4_TS0_DURATION(x) (((x) >> 0) & 0xFFFF)
#define C_0090F4_TS0_DURATION 0xFFFF0000
#define S_0090F4_TS1_DURATION(x) (((unsigned)(x) & 0xFFFF) << 16)
#define G_0090F4_TS1_DURATION(x) (((x) >> 16) & 0xFFFF)
#define C_0090F4_TS1_DURATION 0x0000FFFF
#define R_0090F8_SPI_ARB_CYCLES_1 0x0090F8 /* moved to 0xC708 on CIK */
#define S_0090F8_TS2_DURATION(x) (((unsigned)(x) & 0xFFFF) << 0)
#define G_0090F8_TS2_DURATION(x) (((x) >> 0) & 0xFFFF)
#define C_0090F8_TS2_DURATION 0xFFFF0000
@@ -2665,21 +2678,23 @@
#define C_00936C_SGPR_B 0xFC7FFFFF
#define S_00936C_LDS_B(x) (((unsigned)(x) & 0x07) << 26)
#define G_00936C_LDS_B(x) (((x) >> 26) & 0x07)
#define C_00936C_LDS_B 0xE3FFFFFF
#define S_00936C_WAVES_B(x) (((unsigned)(x) & 0x03) << 29)
#define G_00936C_WAVES_B(x) (((x) >> 29) & 0x03)
#define C_00936C_WAVES_B 0x9FFFFFFF
#define S_00936C_EN_B(x) (((unsigned)(x) & 0x1) << 31)
#define G_00936C_EN_B(x) (((x) >> 31) & 0x1)
#define C_00936C_EN_B 0x7FFFFFFF
+/* not on CIK -- moved to uconfig space */
#define R_00950C_TA_CS_BC_BASE_ADDR 0x00950C
+/* */
#define R_009858_DB_SUBTILE_CONTROL 0x009858
#define S_009858_MSAA1_X(x) (((unsigned)(x) & 0x03) << 0)
#define G_009858_MSAA1_X(x) (((x) >> 0) & 0x03)
#define C_009858_MSAA1_X 0xFFFFFFFC
#define S_009858_MSAA1_Y(x) (((unsigned)(x) & 0x03) << 2)
#define G_009858_MSAA1_Y(x) (((x) >> 2) & 0x03)
#define C_009858_MSAA1_Y 0xFFFFFFF3
#define S_009858_MSAA2_X(x) (((unsigned)(x) & 0x03) << 4)
#define G_009858_MSAA2_X(x) (((x) >> 4) & 0x03)
#define C_009858_MSAA2_X 0xFFFFFFCF
@@ -3581,21 +3596,21 @@
#define S_00B820_NUM_THREAD_PARTIAL(x) (((unsigned)(x) & 0xFFFF) << 16)
#define G_00B820_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF)
#define C_00B820_NUM_THREAD_PARTIAL 0x0000FFFF
#define R_00B824_COMPUTE_NUM_THREAD_Z 0x00B824
#define S_00B824_NUM_THREAD_FULL(x) (((unsigned)(x) & 0xFFFF) << 0)
#define G_00B824_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF)
#define C_00B824_NUM_THREAD_FULL 0xFFFF0000
#define S_00B824_NUM_THREAD_PARTIAL(x) (((unsigned)(x) & 0xFFFF) << 16)
#define G_00B824_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF)
#define C_00B824_NUM_THREAD_PARTIAL 0x0000FFFF
-#define R_00B82C_COMPUTE_MAX_WAVE_ID 0x00B82C /* moved to 0xCD20 on CIK */
+#define R_00B82C_COMPUTE_MAX_WAVE_ID 0x00B82C /* not on CIK -- moved to 0xCD20 */
#define S_00B82C_MAX_WAVE_ID(x) (((unsigned)(x) & 0xFFF) << 0)
#define G_00B82C_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF)
#define C_00B82C_MAX_WAVE_ID 0xFFFFF000
/* CIK */
#define R_00B828_COMPUTE_PIPELINESTAT_ENABLE 0x00B828
#define S_00B828_PIPELINESTAT_ENABLE(x) (((unsigned)(x) & 0x1) << 0)
#define G_00B828_PIPELINESTAT_ENABLE(x) (((x) >> 0) & 0x1)
#define C_00B828_PIPELINESTAT_ENABLE 0xFFFFFFFE
#define R_00B82C_COMPUTE_PERFCOUNT_ENABLE 0x00B82C
#define S_00B82C_PERFCOUNT_ENABLE(x) (((unsigned)(x) & 0x1) << 0)
@@ -7784,20 +7799,21 @@
#define S_028A7C_REQ_PATH(x) (((unsigned)(x) & 0x1) << 10)
#define G_028A7C_REQ_PATH(x) (((x) >> 10) & 0x1)
#define C_028A7C_REQ_PATH 0xFFFFFBFF
/* */
/* VI */
#define S_028A7C_MTYPE(x) (((unsigned)(x) & 0x03) << 11)
#define G_028A7C_MTYPE(x) (((x) >> 11) & 0x03)
#define C_028A7C_MTYPE 0xFFFFE7FF
/* */
#define R_028A80_WD_ENHANCE 0x028A80
+/* not on CIK */
#define R_028A84_VGT_PRIMITIVEID_EN 0x028A84
#define S_028A84_PRIMITIVEID_EN(x) (((unsigned)(x) & 0x1) << 0)
#define G_028A84_PRIMITIVEID_EN(x) (((x) >> 0) & 0x1)
#define C_028A84_PRIMITIVEID_EN 0xFFFFFFFE
#define S_028A84_DISABLE_RESET_ON_EOI(x) (((unsigned)(x) & 0x1) << 1) /* not on CIK */
#define G_028A84_DISABLE_RESET_ON_EOI(x) (((x) >> 1) & 0x1) /* not on CIK */
#define C_028A84_DISABLE_RESET_ON_EOI 0xFFFFFFFD /* not on CIK */
#define R_028A88_VGT_DMA_NUM_INSTANCES 0x028A88
#define R_028A8C_VGT_PRIMITIVEID_RESET 0x028A8C
#define R_028A90_VGT_EVENT_INITIATOR 0x028A90
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index e61f5b8fa47..972d37948aa 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -140,37 +140,39 @@ si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
} else {
raster_config_se |=
S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
}
}
}
}
/* GRBM_GFX_INDEX has a different offset on SI and CI+ */
if (physical_device->rad_info.chip_class < CIK)
- radeon_set_config_reg(cs, GRBM_GFX_INDEX,
- SE_INDEX(se) | SH_BROADCAST_WRITES |
- INSTANCE_BROADCAST_WRITES);
+ radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
+ S_00802C_SE_INDEX(se) |
+ S_00802C_SH_BROADCAST_WRITES(1) |
+ S_00802C_INSTANCE_BROADCAST_WRITES(1));
else
radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
S_030800_INSTANCE_BROADCAST_WRITES(1));
radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
if (physical_device->rad_info.chip_class >= CIK)
radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
}
/* GRBM_GFX_INDEX has a different offset on SI and CI+ */
if (physical_device->rad_info.chip_class < CIK)
- radeon_set_config_reg(cs, GRBM_GFX_INDEX,
- SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
- INSTANCE_BROADCAST_WRITES);
+ radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
+ S_00802C_SE_BROADCAST_WRITES(1) |
+ S_00802C_SH_BROADCAST_WRITES(1) |
+ S_00802C_INSTANCE_BROADCAST_WRITES(1));
else
radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
S_030800_INSTANCE_BROADCAST_WRITES(1));
}
static void
si_emit_compute(struct radv_physical_device *physical_device,
struct radeon_winsys_cs *cs)
{
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index fcf4928e65e..2f9241f02f8 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -4639,21 +4639,21 @@ void si_init_screen_state_functions(struct si_screen *sscreen)
{
sscreen->b.b.is_format_supported = si_is_format_supported;
sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
}
static void si_set_grbm_gfx_index(struct si_context *sctx,
struct si_pm4_state *pm4, unsigned value)
{
unsigned reg = sctx->b.chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
- GRBM_GFX_INDEX;
+ R_00802C_GRBM_GFX_INDEX;
si_pm4_set_reg(pm4, reg, value);
}
static void si_set_grbm_gfx_index_se(struct si_context *sctx,
struct si_pm4_state *pm4, unsigned se)
{
assert(se == ~0 || se < sctx->screen->b.info.max_se);
si_set_grbm_gfx_index(sctx, pm4,
(se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
S_030800_SE_INDEX(se)) |
--
2.11.0
More information about the mesa-dev
mailing list