[Mesa-dev] [PATCH 1/9] ac: pack ac_surface better
Nicolai Hähnle
nhaehnle at gmail.com
Wed Nov 22 18:48:15 UTC 2017
On 21.11.2017 18:30, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> r600_texture: 1736 -> 1488 bytes
> ---
> src/amd/common/ac_surface.h | 9 +++++----
> src/gallium/drivers/r600/r600_texture.c | 2 +-
> src/gallium/drivers/radeon/r600_texture.c | 12 ++++++------
> 3 files changed, 12 insertions(+), 11 deletions(-)
>
> diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
> index 7ac4737..1dc95cd 100644
> --- a/src/amd/common/ac_surface.h
> +++ b/src/amd/common/ac_surface.h
> @@ -65,22 +65,22 @@ enum radeon_micro_mode {
> #define RADEON_SURF_FMASK (1 << 21)
> #define RADEON_SURF_DISABLE_DCC (1 << 22)
> #define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
> #define RADEON_SURF_IMPORTED (1 << 24)
> #define RADEON_SURF_OPTIMIZE_FOR_SPACE (1 << 25)
> #define RADEON_SURF_SHAREABLE (1 << 26)
>
> struct legacy_surf_level {
> uint64_t offset;
> uint64_t slice_size;
> - uint64_t dcc_offset;
> - uint64_t dcc_fast_clear_size;
> + uint32_t dcc_offset; /* relative offset within DCC mip tree */
What about array textures? Those can get rather large.
Apart from that, this patch is:
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
> + uint32_t dcc_fast_clear_size;
> uint16_t nblk_x;
> uint16_t nblk_y;
> enum radeon_surf_mode mode;
> };
>
> struct legacy_surf_layout {
> unsigned bankw:4; /* max 8 */
> unsigned bankh:4; /* max 8 */
> unsigned mtilea:4; /* max 8 */
> unsigned tile_split:13; /* max 4K */
> @@ -180,22 +180,23 @@ struct radeon_surf {
> * Only these surfaces are allowed to set it:
> * - color (if it doesn't have to be displayable)
> * - DCC (same tile swizzle as color)
> * - FMASK
> * - CMASK if it's TC-compatible or if the gen is GFX9
> * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
> */
> uint8_t tile_swizzle;
>
> uint64_t surf_size;
> - uint64_t dcc_size;
> - uint64_t htile_size;
> + /* DCC and HTILE are very small. */
> + uint32_t dcc_size;
> + uint32_t htile_size;
>
> uint32_t htile_slice_size;
>
> uint32_t surf_alignment;
> uint32_t dcc_alignment;
> uint32_t htile_alignment;
>
> union {
> /* R600-VI return values.
> *
> diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
> index ee6ed64..f7c9b63 100644
> --- a/src/gallium/drivers/r600/r600_texture.c
> +++ b/src/gallium/drivers/r600/r600_texture.c
> @@ -830,21 +830,21 @@ void r600_print_texture_info(struct r600_common_screen *rscreen,
> rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
> rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
>
> if (rtex->cmask.size)
> u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, "
> "slice_tile_max=%u\n",
> rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
> rtex->cmask.slice_tile_max);
>
> if (rtex->htile_offset)
> - u_log_printf(log, " HTile: offset=%"PRIu64", size=%"PRIu64", "
> + u_log_printf(log, " HTile: offset=%"PRIu64", size=%u "
> "alignment=%u\n",
> rtex->htile_offset, rtex->surface.htile_size,
> rtex->surface.htile_alignment);
>
> for (i = 0; i <= rtex->resource.b.b.last_level; i++)
> u_log_printf(log, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
> "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
> "mode=%u, tiling_index = %u\n",
> i, rtex->surface.u.legacy.level[i].offset,
> rtex->surface.u.legacy.level[i].slice_size,
> diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
> index 5f6e913..38d2470 100644
> --- a/src/gallium/drivers/radeon/r600_texture.c
> +++ b/src/gallium/drivers/radeon/r600_texture.c
> @@ -998,31 +998,31 @@ void si_print_texture_info(struct r600_common_screen *rscreen,
> u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", "
> "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
> rtex->cmask.offset,
> rtex->surface.u.gfx9.cmask_size,
> rtex->surface.u.gfx9.cmask_alignment,
> rtex->surface.u.gfx9.cmask.rb_aligned,
> rtex->surface.u.gfx9.cmask.pipe_aligned);
> }
>
> if (rtex->htile_offset) {
> - u_log_printf(log, " HTile: offset=%"PRIu64", size=%"PRIu64", alignment=%u, "
> + u_log_printf(log, " HTile: offset=%"PRIu64", size=%u, alignment=%u, "
> "rb_aligned=%u, pipe_aligned=%u\n",
> rtex->htile_offset,
> rtex->surface.htile_size,
> rtex->surface.htile_alignment,
> rtex->surface.u.gfx9.htile.rb_aligned,
> rtex->surface.u.gfx9.htile.pipe_aligned);
> }
>
> if (rtex->dcc_offset) {
> - u_log_printf(log, " DCC: offset=%"PRIu64", size=%"PRIu64", "
> + u_log_printf(log, " DCC: offset=%"PRIu64", size=%u, "
> "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
> rtex->dcc_offset, rtex->surface.dcc_size,
> rtex->surface.dcc_alignment,
> rtex->surface.u.gfx9.dcc_pitch_max,
> rtex->surface.num_dcc_levels);
> }
>
> if (rtex->surface.u.gfx9.stencil_offset) {
> u_log_printf(log, " Stencil: offset=%"PRIu64", swmode=%u, epitch=%u\n",
> rtex->surface.u.gfx9.stencil_offset,
> @@ -1046,33 +1046,33 @@ void si_print_texture_info(struct r600_common_screen *rscreen,
> rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
> rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
>
> if (rtex->cmask.size)
> u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, "
> "slice_tile_max=%u\n",
> rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
> rtex->cmask.slice_tile_max);
>
> if (rtex->htile_offset)
> - u_log_printf(log, " HTile: offset=%"PRIu64", size=%"PRIu64", "
> + u_log_printf(log, " HTile: offset=%"PRIu64", size=%u, "
> "alignment=%u, TC_compatible = %u\n",
> rtex->htile_offset, rtex->surface.htile_size,
> rtex->surface.htile_alignment,
> rtex->tc_compatible_htile);
>
> if (rtex->dcc_offset) {
> - u_log_printf(log, " DCC: offset=%"PRIu64", size=%"PRIu64", alignment=%u\n",
> + u_log_printf(log, " DCC: offset=%"PRIu64", size=%u, alignment=%u\n",
> rtex->dcc_offset, rtex->surface.dcc_size,
> rtex->surface.dcc_alignment);
> for (i = 0; i <= rtex->resource.b.b.last_level; i++)
> - u_log_printf(log, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64", "
> - "fast_clear_size=%"PRIu64"\n",
> + u_log_printf(log, " DCCLevel[%i]: enabled=%u, offset=%u, "
> + "fast_clear_size=%u\n",
> i, i < rtex->surface.num_dcc_levels,
> rtex->surface.u.legacy.level[i].dcc_offset,
> rtex->surface.u.legacy.level[i].dcc_fast_clear_size);
> }
>
> for (i = 0; i <= rtex->resource.b.b.last_level; i++)
> u_log_printf(log, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
> "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
> "mode=%u, tiling_index = %u\n",
> i, rtex->surface.u.legacy.level[i].offset,
>
--
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.
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