[Mesa-dev] [PATCH 30/51] intel/compiler/fs: Pad 16-bit texture return payloads

[Topi Pohjolainen]

This is to tell offset and read/write calculators enough to
work correctly with 16-bit texture payloads.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/intel/compiler/brw_fs_nir.cpp | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 35e78b134a..6d9b272a57 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -4949,7 +4949,22 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
       }
    }
 
-   fs_reg dst = bld.vgrf(brw_type_for_nir_type(devinfo, instr->dest_type), 4);
+   const enum brw_reg_type dst_type =
+      brw_type_for_nir_type(devinfo, instr->dest_type);
+
+   /* In case of 16-bit return format one needs to prepare for 4 registers
+    * regardless of the dispatch width:
+    *
+    * From SKL PRM Vol. 7 Page 131, Return Format = 16-bit:
+    *
+    * A SIMD8* writeback message with Return Format of 16-bit consists of 
+    * up to 4 destination registers).
+    *
+    * Therefore tell builder to give full register per component even in
+    * case of 16-bit size and SIMD8.
+    */
+   const bool pad_components_to_full_registers = true;
+   fs_reg dst = bld.vgrf(dst_type, 4, pad_components_to_full_registers);
    fs_inst *inst = bld.emit(opcode, dst, srcs, ARRAY_SIZE(srcs));
    inst->offset = header_bits;
 
@@ -4987,7 +5002,9 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
       bld.emit_minmax(nir_dest[2], depth, brw_imm_d(1), BRW_CONDITIONAL_GE);
    }
 
-   bld.LOAD_PAYLOAD(get_nir_dest(instr->dest), nir_dest, dest_size, 0);
+   bld.LOAD_PAYLOAD(get_nir_dest(instr->dest,
+                                 pad_components_to_full_registers),
+                    nir_dest, dest_size, 0);
 }
 
 void
-- 
2.11.0