[Mesa-dev] [PATCH 51/51] i965/fs: Lower gles mediump floats into 16-bits

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_link.cpp | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp
index d18521e792..89ccbb06b5 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -134,6 +134,9 @@ process_glsl_ir(struct brw_context *brw,
    lower_noise(shader->ir);
    lower_quadop_vector(shader->ir, false);
 
+   if (shader_prog->IsES && shader->Stage == MESA_SHADER_FRAGMENT)
+      lower_mediump(shader);
+
    validate_ir_tree(shader->ir);
 
    /* Now that we've finished altering the linked IR, reparent any live IR back
-- 
2.11.0