[Mesa-dev] [PATCH 22/23] radeonsi: remove r600_common_screen

Marek Olšák maraeo at gmail.com
Tue Nov 28 21:38:50 UTC 2017


From: Marek Olšák <marek.olsak at amd.com>

Most files in gallium/radeon now include si_pipe.h.

chip_class and family are now here:
    sscreen->info.family
    sscreen->info.chip_class
---
 src/gallium/drivers/radeon/r600_buffer_common.c    |  48 ++--
 src/gallium/drivers/radeon/r600_cs.h               |   4 +-
 src/gallium/drivers/radeon/r600_gpu_load.c         | 112 ++++-----
 src/gallium/drivers/radeon/r600_perfcounter.c      |  32 +--
 src/gallium/drivers/radeon/r600_pipe_common.c      |  40 ++--
 src/gallium/drivers/radeon/r600_pipe_common.h      | 102 ++-------
 src/gallium/drivers/radeon/r600_query.c            | 100 ++++----
 src/gallium/drivers/radeon/r600_query.h            |  20 +-
 src/gallium/drivers/radeon/r600_texture.c          | 251 ++++++++++-----------
 src/gallium/drivers/radeon/radeon_uvd.c            |  14 +-
 src/gallium/drivers/radeon/radeon_vce.c            |  42 ++--
 src/gallium/drivers/radeon/radeon_vce.h            |   4 +-
 src/gallium/drivers/radeon/radeon_vce_52.c         |  10 +-
 src/gallium/drivers/radeon/radeon_vcn_dec.c        |   4 +-
 src/gallium/drivers/radeon/radeon_vcn_enc.c        |   6 +-
 src/gallium/drivers/radeon/radeon_video.c          |   6 +-
 src/gallium/drivers/radeonsi/cik_sdma.c            |   4 +-
 src/gallium/drivers/radeonsi/si_blit.c             |   4 +-
 src/gallium/drivers/radeonsi/si_clear.c            |  26 +--
 src/gallium/drivers/radeonsi/si_compute.c          |  18 +-
 src/gallium/drivers/radeonsi/si_cp_dma.c           |   2 +-
 src/gallium/drivers/radeonsi/si_debug.c            |  12 +-
 src/gallium/drivers/radeonsi/si_descriptors.c      |  12 +-
 src/gallium/drivers/radeonsi/si_dma.c              |   2 +-
 src/gallium/drivers/radeonsi/si_fence.c            |  22 +-
 src/gallium/drivers/radeonsi/si_get.c              | 170 +++++++-------
 src/gallium/drivers/radeonsi/si_hw_context.c       |   4 +-
 src/gallium/drivers/radeonsi/si_perfcounter.c      |  20 +-
 src/gallium/drivers/radeonsi/si_pipe.c             | 222 +++++++++---------
 src/gallium/drivers/radeonsi/si_pipe.h             |  74 +++++-
 src/gallium/drivers/radeonsi/si_pm4.c              |   2 +-
 src/gallium/drivers/radeonsi/si_shader.c           | 102 ++++-----
 src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c  |  22 +-
 .../drivers/radeonsi/si_shader_tgsi_setup.c        |   8 +-
 src/gallium/drivers/radeonsi/si_state.c            |  92 ++++----
 src/gallium/drivers/radeonsi/si_state_binning.c    |   6 +-
 src/gallium/drivers/radeonsi/si_state_draw.c       |  52 ++---
 src/gallium/drivers/radeonsi/si_state_shaders.c    |  60 ++---
 src/gallium/drivers/radeonsi/si_test_dma.c         |   4 +-
 src/gallium/drivers/radeonsi/si_uvd.c              |   2 +-
 40 files changed, 864 insertions(+), 873 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
index 52b4726..5efde0c 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -92,21 +92,21 @@ void *si_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 			ctx->ws->cs_sync_flush(ctx->gfx.cs);
 			if (ctx->dma.cs)
 				ctx->ws->cs_sync_flush(ctx->dma.cs);
 		}
 	}
 
 	/* Setting the CS to NULL will prevent doing checks we have done already. */
 	return ctx->ws->buffer_map(resource->buf, NULL, usage);
 }
 
-void si_init_resource_fields(struct r600_common_screen *rscreen,
+void si_init_resource_fields(struct si_screen *sscreen,
 			     struct r600_resource *res,
 			     uint64_t size, unsigned alignment)
 {
 	struct r600_texture *rtex = (struct r600_texture*)res;
 
 	res->bo_size = size;
 	res->bo_alignment = alignment;
 	res->flags = 0;
 	res->texture_handle_allocated = false;
 	res->image_handle_allocated = false;
@@ -117,22 +117,22 @@ void si_init_resource_fields(struct r600_common_screen *rscreen,
 		/* fall through */
 	case PIPE_USAGE_STAGING:
 		/* Transfers are likely to occur more often with these
 		 * resources. */
 		res->domains = RADEON_DOMAIN_GTT;
 		break;
 	case PIPE_USAGE_DYNAMIC:
 		/* Older kernels didn't always flush the HDP cache before
 		 * CS execution
 		 */
-		if (rscreen->info.drm_major == 2 &&
-		    rscreen->info.drm_minor < 40) {
+		if (sscreen->info.drm_major == 2 &&
+		    sscreen->info.drm_minor < 40) {
 			res->domains = RADEON_DOMAIN_GTT;
 			res->flags |= RADEON_FLAG_GTT_WC;
 			break;
 		}
 		/* fall through */
 	case PIPE_USAGE_DEFAULT:
 	case PIPE_USAGE_IMMUTABLE:
 	default:
 		/* Not listing GTT here improves performance in some
 		 * apps. */
@@ -145,22 +145,22 @@ void si_init_resource_fields(struct r600_common_screen *rscreen,
 	    res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
 			      PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
 		/* Use GTT for all persistent mappings with older
 		 * kernels, because they didn't always flush the HDP
 		 * cache before CS execution.
 		 *
 		 * Write-combined CPU mappings are fine, the kernel
 		 * ensures all CPU writes finish before the GPU
 		 * executes a command stream.
 		 */
-		if (rscreen->info.drm_major == 2 &&
-		    rscreen->info.drm_minor < 40)
+		if (sscreen->info.drm_major == 2 &&
+		    sscreen->info.drm_minor < 40)
 			res->domains = RADEON_DOMAIN_GTT;
 	}
 
 	/* Tiled textures are unmappable. Always put them in VRAM. */
 	if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
 	    res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
 		res->domains = RADEON_DOMAIN_VRAM;
 		res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
 			 RADEON_FLAG_GTT_WC;
 	}
@@ -171,80 +171,80 @@ void si_init_resource_fields(struct r600_common_screen *rscreen,
 	else
 		res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
 
 	/* If VRAM is just stolen system memory, allow both VRAM and
 	 * GTT, whichever has free space. If a buffer is evicted from
 	 * VRAM to GTT, it will stay there.
 	 *
 	 * DRM 3.6.0 has good BO move throttling, so we can allow VRAM-only
 	 * placements even with a low amount of stolen VRAM.
 	 */
-	if (!rscreen->info.has_dedicated_vram &&
-	    (rscreen->info.drm_major < 3 || rscreen->info.drm_minor < 6) &&
+	if (!sscreen->info.has_dedicated_vram &&
+	    (sscreen->info.drm_major < 3 || sscreen->info.drm_minor < 6) &&
 	    res->domains == RADEON_DOMAIN_VRAM) {
 		res->domains = RADEON_DOMAIN_VRAM_GTT;
 		res->flags &= ~RADEON_FLAG_NO_CPU_ACCESS; /* disallowed with VRAM_GTT */
 	}
 
-	if (rscreen->debug_flags & DBG(NO_WC))
+	if (sscreen->debug_flags & DBG(NO_WC))
 		res->flags &= ~RADEON_FLAG_GTT_WC;
 
 	/* Set expected VRAM and GART usage for the buffer. */
 	res->vram_usage = 0;
 	res->gart_usage = 0;
 	res->max_forced_staging_uploads = 0;
 	res->b.max_forced_staging_uploads = 0;
 
 	if (res->domains & RADEON_DOMAIN_VRAM) {
 		res->vram_usage = size;
 
 		res->max_forced_staging_uploads =
 		res->b.max_forced_staging_uploads =
-			rscreen->info.has_dedicated_vram &&
-			size >= rscreen->info.vram_vis_size / 4 ? 1 : 0;
+			sscreen->info.has_dedicated_vram &&
+			size >= sscreen->info.vram_vis_size / 4 ? 1 : 0;
 	} else if (res->domains & RADEON_DOMAIN_GTT) {
 		res->gart_usage = size;
 	}
 }
 
-bool si_alloc_resource(struct r600_common_screen *rscreen,
+bool si_alloc_resource(struct si_screen *sscreen,
 		       struct r600_resource *res)
 {
 	struct pb_buffer *old_buf, *new_buf;
 
 	/* Allocate a new resource. */
-	new_buf = rscreen->ws->buffer_create(rscreen->ws, res->bo_size,
+	new_buf = sscreen->ws->buffer_create(sscreen->ws, res->bo_size,
 					     res->bo_alignment,
 					     res->domains, res->flags);
 	if (!new_buf) {
 		return false;
 	}
 
 	/* Replace the pointer such that if res->buf wasn't NULL, it won't be
 	 * NULL. This should prevent crashes with multiple contexts using
 	 * the same buffer where one of the contexts invalidates it while
 	 * the others are using it. */
 	old_buf = res->buf;
 	res->buf = new_buf; /* should be atomic */
 
-	if (rscreen->info.has_virtual_memory)
-		res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->buf);
+	if (sscreen->info.has_virtual_memory)
+		res->gpu_address = sscreen->ws->buffer_get_virtual_address(res->buf);
 	else
 		res->gpu_address = 0;
 
 	pb_reference(&old_buf, NULL);
 
 	util_range_set_empty(&res->valid_buffer_range);
 	res->TC_L2_dirty = false;
 
 	/* Print debug information. */
-	if (rscreen->debug_flags & DBG(VM) && res->b.b.target == PIPE_BUFFER) {
+	if (sscreen->debug_flags & DBG(VM) && res->b.b.target == PIPE_BUFFER) {
 		fprintf(stderr, "VM start=0x%"PRIX64"  end=0x%"PRIX64" | Buffer %"PRIu64" bytes\n",
 			res->gpu_address, res->gpu_address + res->buf->size,
 			res->buf->size);
 	}
 	return true;
 }
 
 static void r600_buffer_destroy(struct pipe_screen *screen,
 				struct pipe_resource *buf)
 {
@@ -614,29 +614,29 @@ r600_alloc_buffer_struct(struct pipe_screen *screen,
 	rbuffer->bind_history = 0;
 	rbuffer->TC_L2_dirty = false;
 	util_range_init(&rbuffer->valid_buffer_range);
 	return rbuffer;
 }
 
 static struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
 					      const struct pipe_resource *templ,
 					      unsigned alignment)
 {
-	struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
+	struct si_screen *sscreen = (struct si_screen*)screen;
 	struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 
-	si_init_resource_fields(rscreen, rbuffer, templ->width0, alignment);
+	si_init_resource_fields(sscreen, rbuffer, templ->width0, alignment);
 
 	if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
 		rbuffer->flags |= RADEON_FLAG_SPARSE;
 
-	if (!si_alloc_resource(rscreen, rbuffer)) {
+	if (!si_alloc_resource(sscreen, rbuffer)) {
 		FREE(rbuffer);
 		return NULL;
 	}
 	return &rbuffer->b.b;
 }
 
 struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
 					       unsigned flags,
 					       unsigned usage,
 					       unsigned size,
@@ -655,38 +655,38 @@ struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
 	buffer.depth0 = 1;
 	buffer.array_size = 1;
 	return si_buffer_create(screen, &buffer, alignment);
 }
 
 static struct pipe_resource *
 si_buffer_from_user_memory(struct pipe_screen *screen,
 			   const struct pipe_resource *templ,
 			   void *user_memory)
 {
-	struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
-	struct radeon_winsys *ws = rscreen->ws;
+	struct si_screen *sscreen = (struct si_screen*)screen;
+	struct radeon_winsys *ws = sscreen->ws;
 	struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 
 	rbuffer->domains = RADEON_DOMAIN_GTT;
 	rbuffer->flags = 0;
 	rbuffer->b.is_user_ptr = true;
 	util_range_add(&rbuffer->valid_buffer_range, 0, templ->width0);
 	util_range_add(&rbuffer->b.valid_buffer_range, 0, templ->width0);
 
 	/* Convert a user pointer to a buffer. */
 	rbuffer->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0);
 	if (!rbuffer->buf) {
 		FREE(rbuffer);
 		return NULL;
 	}
 
-	if (rscreen->info.has_virtual_memory)
+	if (sscreen->info.has_virtual_memory)
 		rbuffer->gpu_address =
 			ws->buffer_get_virtual_address(rbuffer->buf);
 	else
 		rbuffer->gpu_address = 0;
 
 	rbuffer->vram_usage = 0;
 	rbuffer->gart_usage = templ->width0;
 
 	return &rbuffer->b.b;
 }
@@ -696,23 +696,23 @@ static struct pipe_resource *si_resource_create(struct pipe_screen *screen,
 {
 	if (templ->target == PIPE_BUFFER) {
 		return si_buffer_create(screen, templ, 256);
 	} else {
 		return si_texture_create(screen, templ);
 	}
 }
 
 void si_init_screen_buffer_functions(struct si_screen *sscreen)
 {
-	sscreen->b.b.resource_create = si_resource_create;
-	sscreen->b.b.resource_destroy = u_resource_destroy_vtbl;
-	sscreen->b.b.resource_from_user_memory = si_buffer_from_user_memory;
+	sscreen->b.resource_create = si_resource_create;
+	sscreen->b.resource_destroy = u_resource_destroy_vtbl;
+	sscreen->b.resource_from_user_memory = si_buffer_from_user_memory;
 }
 
 void si_init_buffer_functions(struct si_context *sctx)
 {
 	sctx->b.b.invalidate_resource = si_invalidate_resource;
 	sctx->b.b.transfer_map = u_transfer_map_vtbl;
 	sctx->b.b.transfer_flush_region = u_transfer_flush_region_vtbl;
 	sctx->b.b.transfer_unmap = u_transfer_unmap_vtbl;
 	sctx->b.b.texture_subdata = u_default_texture_subdata;
 	sctx->b.b.buffer_subdata = si_buffer_subdata;
diff --git a/src/gallium/drivers/radeon/r600_cs.h b/src/gallium/drivers/radeon/r600_cs.h
index 79737d2..2f555dc 100644
--- a/src/gallium/drivers/radeon/r600_cs.h
+++ b/src/gallium/drivers/radeon/r600_cs.h
@@ -21,32 +21,32 @@
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /**
  * This file contains helpers for writing commands to commands streams.
  */
 
 #ifndef R600_CS_H
 #define R600_CS_H
 
-#include "r600_pipe_common.h"
+#include "radeonsi/si_pipe.h"
 #include "amd/common/sid.h"
 
 /**
  * Return true if there is enough memory in VRAM and GTT for the buffers
  * added so far.
  *
  * \param vram      VRAM memory size not added to the buffer list yet
  * \param gtt       GTT memory size not added to the buffer list yet
  */
 static inline bool
-radeon_cs_memory_below_limit(struct r600_common_screen *screen,
+radeon_cs_memory_below_limit(struct si_screen *screen,
 			     struct radeon_winsys_cs *cs,
 			     uint64_t vram, uint64_t gtt)
 {
 	vram += cs->used_vram;
 	gtt += cs->used_gart;
 
 	/* Anything that goes above the VRAM size should go to GTT. */
 	if (vram > screen->info.vram_size)
 		gtt += vram - screen->info.vram_size;
 
diff --git a/src/gallium/drivers/radeon/r600_gpu_load.c b/src/gallium/drivers/radeon/r600_gpu_load.c
index 411dcfe..c1fdf20 100644
--- a/src/gallium/drivers/radeon/r600_gpu_load.c
+++ b/src/gallium/drivers/radeon/r600_gpu_load.c
@@ -24,21 +24,21 @@
 /* The GPU load is measured as follows.
  *
  * There is a thread which samples the GRBM_STATUS register at a certain
  * frequency and the "busy" or "idle" counter is incremented based on
  * whether the GUI_ACTIVE bit is set or not.
  *
  * Then, the user can sample the counters twice and calculate the average
  * GPU load between the two samples.
  */
 
-#include "r600_pipe_common.h"
+#include "radeonsi/si_pipe.h"
 #include "r600_query.h"
 #include "util/os_time.h"
 
 /* For good accuracy at 1000 fps or lower. This will be inaccurate for higher
  * fps (there are too few samples per frame). */
 #define SAMPLES_PER_SEC 10000
 
 #define GRBM_STATUS		0x8010
 #define TA_BUSY(x)		(((x) >> 14) & 0x1)
 #define GDS_BUSY(x)		(((x) >> 15) & 0x1)
@@ -69,212 +69,212 @@
 #define IDENTITY(x) x
 
 #define UPDATE_COUNTER(field, mask)					\
 	do {								\
 		if (mask(value))					\
 			p_atomic_inc(&counters->named.field.busy);	\
 		else							\
 			p_atomic_inc(&counters->named.field.idle);	\
 	} while (0)
 
-static void r600_update_mmio_counters(struct r600_common_screen *rscreen,
+static void r600_update_mmio_counters(struct si_screen *sscreen,
 				      union r600_mmio_counters *counters)
 {
 	uint32_t value = 0;
 	bool gui_busy, sdma_busy = false;
 
 	/* GRBM_STATUS */
-	rscreen->ws->read_registers(rscreen->ws, GRBM_STATUS, 1, &value);
+	sscreen->ws->read_registers(sscreen->ws, GRBM_STATUS, 1, &value);
 
 	UPDATE_COUNTER(ta, TA_BUSY);
 	UPDATE_COUNTER(gds, GDS_BUSY);
 	UPDATE_COUNTER(vgt, VGT_BUSY);
 	UPDATE_COUNTER(ia, IA_BUSY);
 	UPDATE_COUNTER(sx, SX_BUSY);
 	UPDATE_COUNTER(wd, WD_BUSY);
 	UPDATE_COUNTER(spi, SPI_BUSY);
 	UPDATE_COUNTER(bci, BCI_BUSY);
 	UPDATE_COUNTER(sc, SC_BUSY);
 	UPDATE_COUNTER(pa, PA_BUSY);
 	UPDATE_COUNTER(db, DB_BUSY);
 	UPDATE_COUNTER(cp, CP_BUSY);
 	UPDATE_COUNTER(cb, CB_BUSY);
 	UPDATE_COUNTER(gui, GUI_ACTIVE);
 	gui_busy = GUI_ACTIVE(value);
 
-	if (rscreen->chip_class == CIK || rscreen->chip_class == VI) {
+	if (sscreen->info.chip_class == CIK || sscreen->info.chip_class == VI) {
 		/* SRBM_STATUS2 */
-		rscreen->ws->read_registers(rscreen->ws, SRBM_STATUS2, 1, &value);
+		sscreen->ws->read_registers(sscreen->ws, SRBM_STATUS2, 1, &value);
 
 		UPDATE_COUNTER(sdma, SDMA_BUSY);
 		sdma_busy = SDMA_BUSY(value);
 	}
 
-	if (rscreen->chip_class >= VI) {
+	if (sscreen->info.chip_class >= VI) {
 		/* CP_STAT */
-		rscreen->ws->read_registers(rscreen->ws, CP_STAT, 1, &value);
+		sscreen->ws->read_registers(sscreen->ws, CP_STAT, 1, &value);
 
 		UPDATE_COUNTER(pfp, PFP_BUSY);
 		UPDATE_COUNTER(meq, MEQ_BUSY);
 		UPDATE_COUNTER(me, ME_BUSY);
 		UPDATE_COUNTER(surf_sync, SURFACE_SYNC_BUSY);
 		UPDATE_COUNTER(cp_dma, DMA_BUSY);
 		UPDATE_COUNTER(scratch_ram, SCRATCH_RAM_BUSY);
 	}
 
 	value = gui_busy || sdma_busy;
 	UPDATE_COUNTER(gpu, IDENTITY);
 }
 
 #undef UPDATE_COUNTER
 
 static int
 r600_gpu_load_thread(void *param)
 {
-	struct r600_common_screen *rscreen = (struct r600_common_screen*)param;
+	struct si_screen *sscreen = (struct si_screen*)param;
 	const int period_us = 1000000 / SAMPLES_PER_SEC;
 	int sleep_us = period_us;
 	int64_t cur_time, last_time = os_time_get();
 
-	while (!p_atomic_read(&rscreen->gpu_load_stop_thread)) {
+	while (!p_atomic_read(&sscreen->gpu_load_stop_thread)) {
 		if (sleep_us)
 			os_time_sleep(sleep_us);
 
 		/* Make sure we sleep the ideal amount of time to match
 		 * the expected frequency. */
 		cur_time = os_time_get();
 
 		if (os_time_timeout(last_time, last_time + period_us,
 				    cur_time))
 			sleep_us = MAX2(sleep_us - 1, 1);
 		else
 			sleep_us += 1;
 
 		/*printf("Hz: %.1f\n", 1000000.0 / (cur_time - last_time));*/
 		last_time = cur_time;
 
 		/* Update the counters. */
-		r600_update_mmio_counters(rscreen, &rscreen->mmio_counters);
+		r600_update_mmio_counters(sscreen, &sscreen->mmio_counters);
 	}
-	p_atomic_dec(&rscreen->gpu_load_stop_thread);
+	p_atomic_dec(&sscreen->gpu_load_stop_thread);
 	return 0;
 }
 
-void si_gpu_load_kill_thread(struct r600_common_screen *rscreen)
+void si_gpu_load_kill_thread(struct si_screen *sscreen)
 {
-	if (!rscreen->gpu_load_thread)
+	if (!sscreen->gpu_load_thread)
 		return;
 
-	p_atomic_inc(&rscreen->gpu_load_stop_thread);
-	thrd_join(rscreen->gpu_load_thread, NULL);
-	rscreen->gpu_load_thread = 0;
+	p_atomic_inc(&sscreen->gpu_load_stop_thread);
+	thrd_join(sscreen->gpu_load_thread, NULL);
+	sscreen->gpu_load_thread = 0;
 }
 
-static uint64_t r600_read_mmio_counter(struct r600_common_screen *rscreen,
+static uint64_t r600_read_mmio_counter(struct si_screen *sscreen,
 				       unsigned busy_index)
 {
 	/* Start the thread if needed. */
-	if (!rscreen->gpu_load_thread) {
-		mtx_lock(&rscreen->gpu_load_mutex);
+	if (!sscreen->gpu_load_thread) {
+		mtx_lock(&sscreen->gpu_load_mutex);
 		/* Check again inside the mutex. */
-		if (!rscreen->gpu_load_thread)
-			rscreen->gpu_load_thread =
-				u_thread_create(r600_gpu_load_thread, rscreen);
-		mtx_unlock(&rscreen->gpu_load_mutex);
+		if (!sscreen->gpu_load_thread)
+			sscreen->gpu_load_thread =
+				u_thread_create(r600_gpu_load_thread, sscreen);
+		mtx_unlock(&sscreen->gpu_load_mutex);
 	}
 
-	unsigned busy = p_atomic_read(&rscreen->mmio_counters.array[busy_index]);
-	unsigned idle = p_atomic_read(&rscreen->mmio_counters.array[busy_index + 1]);
+	unsigned busy = p_atomic_read(&sscreen->mmio_counters.array[busy_index]);
+	unsigned idle = p_atomic_read(&sscreen->mmio_counters.array[busy_index + 1]);
 
 	return busy | ((uint64_t)idle << 32);
 }
 
-static unsigned r600_end_mmio_counter(struct r600_common_screen *rscreen,
+static unsigned r600_end_mmio_counter(struct si_screen *sscreen,
 				      uint64_t begin, unsigned busy_index)
 {
-	uint64_t end = r600_read_mmio_counter(rscreen, busy_index);
+	uint64_t end = r600_read_mmio_counter(sscreen, busy_index);
 	unsigned busy = (end & 0xffffffff) - (begin & 0xffffffff);
 	unsigned idle = (end >> 32) - (begin >> 32);
 
 	/* Calculate the % of time the busy counter was being incremented.
 	 *
 	 * If no counters were incremented, return the current counter status.
 	 * It's for the case when the load is queried faster than
 	 * the counters are updated.
 	 */
 	if (idle || busy) {
 		return busy*100 / (busy + idle);
 	} else {
 		union r600_mmio_counters counters;
 
 		memset(&counters, 0, sizeof(counters));
-		r600_update_mmio_counters(rscreen, &counters);
+		r600_update_mmio_counters(sscreen, &counters);
 		return counters.array[busy_index] ? 100 : 0;
 	}
 }
 
 #define BUSY_INDEX(rscreen, field) (&rscreen->mmio_counters.named.field.busy - \
 				    rscreen->mmio_counters.array)
 
-static unsigned busy_index_from_type(struct r600_common_screen *rscreen,
+static unsigned busy_index_from_type(struct si_screen *sscreen,
 				     unsigned type)
 {
 	switch (type) {
 	case R600_QUERY_GPU_LOAD:
-		return BUSY_INDEX(rscreen, gpu);
+		return BUSY_INDEX(sscreen, gpu);
 	case R600_QUERY_GPU_SHADERS_BUSY:
-		return BUSY_INDEX(rscreen, spi);
+		return BUSY_INDEX(sscreen, spi);
 	case R600_QUERY_GPU_TA_BUSY:
-		return BUSY_INDEX(rscreen, ta);
+		return BUSY_INDEX(sscreen, ta);
 	case R600_QUERY_GPU_GDS_BUSY:
-		return BUSY_INDEX(rscreen, gds);
+		return BUSY_INDEX(sscreen, gds);
 	case R600_QUERY_GPU_VGT_BUSY:
-		return BUSY_INDEX(rscreen, vgt);
+		return BUSY_INDEX(sscreen, vgt);
 	case R600_QUERY_GPU_IA_BUSY:
-		return BUSY_INDEX(rscreen, ia);
+		return BUSY_INDEX(sscreen, ia);
 	case R600_QUERY_GPU_SX_BUSY:
-		return BUSY_INDEX(rscreen, sx);
+		return BUSY_INDEX(sscreen, sx);
 	case R600_QUERY_GPU_WD_BUSY:
-		return BUSY_INDEX(rscreen, wd);
+		return BUSY_INDEX(sscreen, wd);
 	case R600_QUERY_GPU_BCI_BUSY:
-		return BUSY_INDEX(rscreen, bci);
+		return BUSY_INDEX(sscreen, bci);
 	case R600_QUERY_GPU_SC_BUSY:
-		return BUSY_INDEX(rscreen, sc);
+		return BUSY_INDEX(sscreen, sc);
 	case R600_QUERY_GPU_PA_BUSY:
-		return BUSY_INDEX(rscreen, pa);
+		return BUSY_INDEX(sscreen, pa);
 	case R600_QUERY_GPU_DB_BUSY:
-		return BUSY_INDEX(rscreen, db);
+		return BUSY_INDEX(sscreen, db);
 	case R600_QUERY_GPU_CP_BUSY:
-		return BUSY_INDEX(rscreen, cp);
+		return BUSY_INDEX(sscreen, cp);
 	case R600_QUERY_GPU_CB_BUSY:
-		return BUSY_INDEX(rscreen, cb);
+		return BUSY_INDEX(sscreen, cb);
 	case R600_QUERY_GPU_SDMA_BUSY:
-		return BUSY_INDEX(rscreen, sdma);
+		return BUSY_INDEX(sscreen, sdma);
 	case R600_QUERY_GPU_PFP_BUSY:
-		return BUSY_INDEX(rscreen, pfp);
+		return BUSY_INDEX(sscreen, pfp);
 	case R600_QUERY_GPU_MEQ_BUSY:
-		return BUSY_INDEX(rscreen, meq);
+		return BUSY_INDEX(sscreen, meq);
 	case R600_QUERY_GPU_ME_BUSY:
-		return BUSY_INDEX(rscreen, me);
+		return BUSY_INDEX(sscreen, me);
 	case R600_QUERY_GPU_SURF_SYNC_BUSY:
-		return BUSY_INDEX(rscreen, surf_sync);
+		return BUSY_INDEX(sscreen, surf_sync);
 	case R600_QUERY_GPU_CP_DMA_BUSY:
-		return BUSY_INDEX(rscreen, cp_dma);
+		return BUSY_INDEX(sscreen, cp_dma);
 	case R600_QUERY_GPU_SCRATCH_RAM_BUSY:
-		return BUSY_INDEX(rscreen, scratch_ram);
+		return BUSY_INDEX(sscreen, scratch_ram);
 	default:
 		unreachable("invalid query type");
 	}
 }
 
-uint64_t si_begin_counter(struct r600_common_screen *rscreen, unsigned type)
+uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type)
 {
-	unsigned busy_index = busy_index_from_type(rscreen, type);
-	return r600_read_mmio_counter(rscreen, busy_index);
+	unsigned busy_index = busy_index_from_type(sscreen, type);
+	return r600_read_mmio_counter(sscreen, busy_index);
 }
 
-unsigned si_end_counter(struct r600_common_screen *rscreen, unsigned type,
+unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
 			uint64_t begin)
 {
-	unsigned busy_index = busy_index_from_type(rscreen, type);
-	return r600_end_mmio_counter(rscreen, begin, busy_index);
+	unsigned busy_index = busy_index_from_type(sscreen, type);
+	return r600_end_mmio_counter(sscreen, begin, busy_index);
 }
diff --git a/src/gallium/drivers/radeon/r600_perfcounter.c b/src/gallium/drivers/radeon/r600_perfcounter.c
index d88accc..711baef 100644
--- a/src/gallium/drivers/radeon/r600_perfcounter.c
+++ b/src/gallium/drivers/radeon/r600_perfcounter.c
@@ -16,21 +16,21 @@
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
  */
 
 #include "util/u_memory.h"
 #include "r600_query.h"
-#include "r600_pipe_common.h"
+#include "radeonsi/si_pipe.h"
 #include "amd/common/sid.h"
 
 /* Max counters per HW block */
 #define R600_QUERY_MAX_COUNTERS 16
 
 static struct r600_perfcounter_block *
 lookup_counter(struct r600_perfcounters *pc, unsigned index,
 	       unsigned *base_gid, unsigned *sub_index)
 {
 	struct r600_perfcounter_block *block = pc->blocks;
@@ -88,37 +88,37 @@ struct r600_pc_counter {
 
 struct r600_query_pc {
 	struct r600_query_hw b;
 
 	unsigned shaders;
 	unsigned num_counters;
 	struct r600_pc_counter *counters;
 	struct r600_pc_group *groups;
 };
 
-static void r600_pc_query_destroy(struct r600_common_screen *rscreen,
+static void r600_pc_query_destroy(struct si_screen *sscreen,
 				  struct r600_query *rquery)
 {
 	struct r600_query_pc *query = (struct r600_query_pc *)rquery;
 
 	while (query->groups) {
 		struct r600_pc_group *group = query->groups;
 		query->groups = group->next;
 		FREE(group);
 	}
 
 	FREE(query->counters);
 
-	si_query_hw_destroy(rscreen, rquery);
+	si_query_hw_destroy(sscreen, rquery);
 }
 
-static bool r600_pc_query_prepare_buffer(struct r600_common_screen *screen,
+static bool r600_pc_query_prepare_buffer(struct si_screen *screen,
 					 struct r600_query_hw *hwquery,
 					 struct r600_resource *buffer)
 {
 	/* no-op */
 	return true;
 }
 
 static void r600_pc_query_emit_start(struct r600_common_context *ctx,
 				     struct r600_query_hw *hwquery,
 				     struct r600_resource *buffer, uint64_t va)
@@ -185,21 +185,21 @@ static void r600_pc_query_emit_stop(struct r600_common_context *ctx,
 }
 
 static void r600_pc_query_clear_result(struct r600_query_hw *hwquery,
 				       union pipe_query_result *result)
 {
 	struct r600_query_pc *query = (struct r600_query_pc *)hwquery;
 
 	memset(result, 0, sizeof(result->batch[0]) * query->num_counters);
 }
 
-static void r600_pc_query_add_result(struct r600_common_screen *rscreen,
+static void r600_pc_query_add_result(struct si_screen *sscreen,
 				     struct r600_query_hw *hwquery,
 				     void *buffer,
 				     union pipe_query_result *result)
 {
 	struct r600_query_pc *query = (struct r600_query_pc *)hwquery;
 	uint64_t *results = buffer;
 	unsigned i, j;
 
 	for (i = 0; i < query->num_counters; ++i) {
 		struct r600_pc_counter *counter = &query->counters[i];
@@ -219,21 +219,21 @@ static struct r600_query_ops batch_query_ops = {
 };
 
 static struct r600_query_hw_ops batch_query_hw_ops = {
 	.prepare_buffer = r600_pc_query_prepare_buffer,
 	.emit_start = r600_pc_query_emit_start,
 	.emit_stop = r600_pc_query_emit_stop,
 	.clear_result = r600_pc_query_clear_result,
 	.add_result = r600_pc_query_add_result,
 };
 
-static struct r600_pc_group *get_group_state(struct r600_common_screen *screen,
+static struct r600_pc_group *get_group_state(struct si_screen *screen,
 					     struct r600_query_pc *query,
 					     struct r600_perfcounter_block *block,
 					     unsigned sub_gid)
 {
 	struct r600_pc_group *group = query->groups;
 
 	while (group) {
 		if (group->block == block && group->sub_gid == sub_gid)
 			return group;
 		group = group->next;
@@ -290,22 +290,22 @@ static struct r600_pc_group *get_group_state(struct r600_common_screen *screen,
 	group->next = query->groups;
 	query->groups = group;
 
 	return group;
 }
 
 struct pipe_query *si_create_batch_query(struct pipe_context *ctx,
 					 unsigned num_queries,
 					 unsigned *query_types)
 {
-	struct r600_common_screen *screen =
-		(struct r600_common_screen *)ctx->screen;
+	struct si_screen *screen =
+		(struct si_screen *)ctx->screen;
 	struct r600_perfcounters *pc = screen->perfcounters;
 	struct r600_perfcounter_block *block;
 	struct r600_pc_group *group;
 	struct r600_query_pc *query;
 	unsigned base_gid, sub_gid, sub_index;
 	unsigned i, j;
 
 	if (!pc)
 		return NULL;
 
@@ -416,21 +416,21 @@ struct pipe_query *si_create_batch_query(struct pipe_context *ctx,
 	if (!si_query_hw_init(screen, &query->b))
 		goto error;
 
 	return (struct pipe_query *)query;
 
 error:
 	r600_pc_query_destroy(screen, &query->b.b);
 	return NULL;
 }
 
-static bool r600_init_block_names(struct r600_common_screen *screen,
+static bool r600_init_block_names(struct si_screen *screen,
 				  struct r600_perfcounter_block *block)
 {
 	unsigned i, j, k;
 	unsigned groups_shader = 1, groups_se = 1, groups_instance = 1;
 	unsigned namelen;
 	char *groupname;
 	char *p;
 
 	if (block->flags & R600_PC_BLOCK_INSTANCE_GROUPS)
 		groups_instance = block->num_instances;
@@ -500,21 +500,21 @@ static bool r600_init_block_names(struct r600_common_screen *screen,
 		for (j = 0; j < block->num_selectors; ++j) {
 			sprintf(p, "%s_%03d", groupname, j);
 			p += block->selector_name_stride;
 		}
 		groupname += block->group_name_stride;
 	}
 
 	return true;
 }
 
-int si_get_perfcounter_info(struct r600_common_screen *screen,
+int si_get_perfcounter_info(struct si_screen *screen,
 			    unsigned index,
 			    struct pipe_driver_query_info *info)
 {
 	struct r600_perfcounters *pc = screen->perfcounters;
 	struct r600_perfcounter_block *block;
 	unsigned base_gid, sub;
 
 	if (!pc)
 		return 0;
 
@@ -542,21 +542,21 @@ int si_get_perfcounter_info(struct r600_common_screen *screen,
 	info->max_value.u64 = 0;
 	info->type = PIPE_DRIVER_QUERY_TYPE_UINT64;
 	info->result_type = PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE;
 	info->group_id = base_gid + sub / block->num_selectors;
 	info->flags = PIPE_DRIVER_QUERY_FLAG_BATCH;
 	if (sub > 0 && sub + 1 < block->num_selectors * block->num_groups)
 		info->flags |= PIPE_DRIVER_QUERY_FLAG_DONT_LIST;
 	return 1;
 }
 
-int si_get_perfcounter_group_info(struct r600_common_screen *screen,
+int si_get_perfcounter_group_info(struct si_screen *screen,
 				  unsigned index,
 				  struct pipe_driver_query_group_info *info)
 {
 	struct r600_perfcounters *pc = screen->perfcounters;
 	struct r600_perfcounter_block *block;
 
 	if (!pc)
 		return 0;
 
 	if (!info)
@@ -569,40 +569,40 @@ int si_get_perfcounter_group_info(struct r600_common_screen *screen,
 	if (!block->group_names) {
 		if (!r600_init_block_names(screen, block))
 			return 0;
 	}
 	info->name = block->group_names + index * block->group_name_stride;
 	info->num_queries = block->num_selectors;
 	info->max_active_queries = block->num_counters;
 	return 1;
 }
 
-void si_perfcounters_destroy(struct r600_common_screen *rscreen)
+void si_perfcounters_destroy(struct si_screen *sscreen)
 {
-	if (rscreen->perfcounters)
-		rscreen->perfcounters->cleanup(rscreen);
+	if (sscreen->perfcounters)
+		sscreen->perfcounters->cleanup(sscreen);
 }
 
 bool si_perfcounters_init(struct r600_perfcounters *pc,
 			    unsigned num_blocks)
 {
 	pc->blocks = CALLOC(num_blocks, sizeof(struct r600_perfcounter_block));
 	if (!pc->blocks)
 		return false;
 
 	pc->separate_se = debug_get_bool_option("RADEON_PC_SEPARATE_SE", false);
 	pc->separate_instance = debug_get_bool_option("RADEON_PC_SEPARATE_INSTANCE", false);
 
 	return true;
 }
 
-void si_perfcounters_add_block(struct r600_common_screen *rscreen,
+void si_perfcounters_add_block(struct si_screen *sscreen,
 			       struct r600_perfcounters *pc,
 			       const char *name, unsigned flags,
 			       unsigned counters, unsigned selectors,
 			       unsigned instances, void *data)
 {
 	struct r600_perfcounter_block *block = &pc->blocks[pc->num_blocks];
 
 	assert(counters <= R600_QUERY_MAX_COUNTERS);
 
 	block->basename = name;
@@ -617,21 +617,21 @@ void si_perfcounters_add_block(struct r600_common_screen *rscreen,
 	if (pc->separate_instance && block->num_instances > 1)
 		block->flags |= R600_PC_BLOCK_INSTANCE_GROUPS;
 
 	if (block->flags & R600_PC_BLOCK_INSTANCE_GROUPS) {
 		block->num_groups = block->num_instances;
 	} else {
 		block->num_groups = 1;
 	}
 
 	if (block->flags & R600_PC_BLOCK_SE_GROUPS)
-		block->num_groups *= rscreen->info.max_se;
+		block->num_groups *= sscreen->info.max_se;
 	if (block->flags & R600_PC_BLOCK_SHADER)
 		block->num_groups *= pc->num_shader_types;
 
 	++pc->num_blocks;
 	pc->num_groups += block->num_groups;
 }
 
 void si_perfcounters_do_destroy(struct r600_perfcounters *pc)
 {
 	unsigned i;
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index e8ee792..08eb406 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -120,26 +120,26 @@ void si_gfx_write_event_eop(struct r600_common_context *ctx,
 		radeon_emit(cs, new_fence); /* immediate data */
 		radeon_emit(cs, 0); /* unused */
 	}
 
 	if (buf) {
 		radeon_add_to_buffer_list(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
 					  RADEON_PRIO_QUERY);
 	}
 }
 
-unsigned si_gfx_write_fence_dwords(struct r600_common_screen *screen)
+unsigned si_gfx_write_fence_dwords(struct si_screen *screen)
 {
 	unsigned dwords = 6;
 
-	if (screen->chip_class == CIK ||
-	    screen->chip_class == VI)
+	if (screen->info.chip_class == CIK ||
+	    screen->info.chip_class == VI)
 		dwords *= 2;
 
 	if (!screen->info.has_virtual_memory)
 		dwords += 2;
 
 	return dwords;
 }
 
 void si_gfx_wait_fence(struct r600_common_context *ctx,
 		       uint64_t va, uint32_t ref, uint32_t mask)
@@ -396,76 +396,76 @@ static bool r600_resource_commit(struct pipe_context *pctx,
 
 	ctx->ws->cs_sync_flush(ctx->dma.cs);
 	ctx->ws->cs_sync_flush(ctx->gfx.cs);
 
 	assert(resource->target == PIPE_BUFFER);
 
 	return ctx->ws->buffer_commit(res->buf, box->x, box->width, commit);
 }
 
 bool si_common_context_init(struct r600_common_context *rctx,
-			    struct r600_common_screen *rscreen,
+			    struct si_screen *sscreen,
 			    unsigned context_flags)
 {
-	slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
-	slab_create_child(&rctx->pool_transfers_unsync, &rscreen->pool_transfers);
+	slab_create_child(&rctx->pool_transfers, &sscreen->pool_transfers);
+	slab_create_child(&rctx->pool_transfers_unsync, &sscreen->pool_transfers);
 
-	rctx->screen = rscreen;
-	rctx->ws = rscreen->ws;
-	rctx->family = rscreen->family;
-	rctx->chip_class = rscreen->chip_class;
+	rctx->screen = sscreen;
+	rctx->ws = sscreen->ws;
+	rctx->family = sscreen->info.family;
+	rctx->chip_class = sscreen->info.chip_class;
 
 	rctx->b.resource_commit = r600_resource_commit;
 
-	if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
+	if (sscreen->info.drm_major == 2 && sscreen->info.drm_minor >= 43) {
 		rctx->b.get_device_reset_status = r600_get_reset_status;
 		rctx->gpu_reset_counter =
 			rctx->ws->query_value(rctx->ws,
 					      RADEON_GPU_RESET_COUNTER);
 	}
 
 	rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
 
 	si_init_context_texture_functions(rctx);
 	si_init_query_functions(rctx);
 
 	if (rctx->chip_class == CIK ||
 	    rctx->chip_class == VI ||
 	    rctx->chip_class == GFX9) {
 		rctx->eop_bug_scratch = (struct r600_resource*)
-			pipe_buffer_create(&rscreen->b, 0, PIPE_USAGE_DEFAULT,
-					   16 * rscreen->info.num_render_backends);
+			pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
+					   16 * sscreen->info.num_render_backends);
 		if (!rctx->eop_bug_scratch)
 			return false;
 	}
 
 	rctx->allocator_zeroed_memory =
-		u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
+		u_suballocator_create(&rctx->b, sscreen->info.gart_page_size,
 				      0, PIPE_USAGE_DEFAULT, 0, true);
 	if (!rctx->allocator_zeroed_memory)
 		return false;
 
 	rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
 						  0, PIPE_USAGE_STREAM);
 	if (!rctx->b.stream_uploader)
 		return false;
 
 	rctx->b.const_uploader = u_upload_create(&rctx->b, 128 * 1024,
 						 0, PIPE_USAGE_DEFAULT);
 	if (!rctx->b.const_uploader)
 		return false;
 
 	rctx->ctx = rctx->ws->ctx_create(rctx->ws);
 	if (!rctx->ctx)
 		return false;
 
-	if (rscreen->info.num_sdma_rings && !(rscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
+	if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
 		rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
 						   r600_flush_dma_ring,
 						   rctx);
 		rctx->dma.flush = r600_flush_dma_ring;
 	}
 
 	return true;
 }
 
 void si_common_context_cleanup(struct r600_common_context *rctx)
@@ -504,20 +504,20 @@ void si_common_context_cleanup(struct r600_common_context *rctx)
 
 	if (rctx->allocator_zeroed_memory) {
 		u_suballocator_destroy(rctx->allocator_zeroed_memory);
 	}
 	rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
 	rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
 	r600_resource_reference(&rctx->eop_bug_scratch, NULL);
 }
 
 
-void si_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
+void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
 			    uint64_t offset, uint64_t size, unsigned value)
 {
-	struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
+	struct r600_common_context *rctx = (struct r600_common_context*)sscreen->aux_context;
 
-	mtx_lock(&rscreen->aux_context_lock);
+	mtx_lock(&sscreen->aux_context_lock);
 	rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
-	rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
-	mtx_unlock(&rscreen->aux_context_lock);
+	sscreen->aux_context->flush(sscreen->aux_context, NULL, 0);
+	mtx_unlock(&sscreen->aux_context_lock);
 }
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index e9b6d46..498a741 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -352,92 +352,20 @@ union r600_mmio_counters {
 	unsigned array[0];
 };
 
 struct r600_memory_object {
 	struct pipe_memory_object	b;
 	struct pb_buffer		*buf;
 	uint32_t			stride;
 	uint32_t			offset;
 };
 
-struct r600_common_screen {
-	struct pipe_screen		b;
-	struct radeon_winsys		*ws;
-	enum radeon_family		family;
-	enum chip_class			chip_class;
-	struct radeon_info		info;
-	uint64_t			debug_flags;
-	bool				has_rbplus;     /* if RB+ registers exist */
-	bool				rbplus_allowed; /* if RB+ is allowed */
-	bool				dcc_msaa_allowed;
-
-	struct disk_cache		*disk_shader_cache;
-
-	struct slab_parent_pool		pool_transfers;
-
-	/* Texture filter settings. */
-	int				force_aniso; /* -1 = disabled */
-
-	/* Auxiliary context. Mainly used to initialize resources.
-	 * It must be locked prior to using and flushed before unlocking. */
-	struct pipe_context		*aux_context;
-	mtx_t				aux_context_lock;
-
-	/* This must be in the screen, because UE4 uses one context for
-	 * compilation and another one for rendering.
-	 */
-	unsigned			num_compilations;
-	/* Along with ST_DEBUG=precompile, this should show if applications
-	 * are loading shaders on demand. This is a monotonic counter.
-	 */
-	unsigned			num_shaders_created;
-	unsigned			num_shader_cache_hits;
-
-	/* GPU load thread. */
-	mtx_t				gpu_load_mutex;
-	thrd_t				gpu_load_thread;
-	union r600_mmio_counters	mmio_counters;
-	volatile unsigned		gpu_load_stop_thread; /* bool */
-
-	char				renderer_string[100];
-
-	/* Performance counters. */
-	struct r600_perfcounters	*perfcounters;
-
-	/* If pipe_screen wants to recompute and re-emit the framebuffer,
-	 * sampler, and image states of all contexts, it should atomically
-	 * increment this.
-	 *
-	 * Each context will compare this with its own last known value of
-	 * the counter before drawing and re-emit the states accordingly.
-	 */
-	unsigned			dirty_tex_counter;
-
-	/* Atomically increment this counter when an existing texture's
-	 * metadata is enabled or disabled in a way that requires changing
-	 * contexts' compressed texture binding masks.
-	 */
-	unsigned			compressed_colortex_counter;
-
-	struct {
-		/* Context flags to set so that all writes from earlier jobs
-		 * in the CP are seen by L2 clients.
-		 */
-		unsigned cp_to_L2;
-
-		/* Context flags to set so that all writes from earlier jobs
-		 * that end in L2 are seen by CP.
-		 */
-		unsigned L2_to_cp;
-	} barrier_flags;
-};
-
 /* This encapsulates a state or an operation which can emitted into the GPU
  * command stream. */
 struct r600_atom {
 	void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 	unsigned short		id;
 };
 
 struct r600_ring {
 	struct radeon_winsys_cs		*cs;
 	void (*flush)(void *ctx, unsigned flags,
@@ -449,21 +377,21 @@ struct radeon_saved_cs {
 	uint32_t			*ib;
 	unsigned			num_dw;
 
 	struct radeon_bo_list_item	*bo_list;
 	unsigned			bo_count;
 };
 
 struct r600_common_context {
 	struct pipe_context b; /* base class */
 
-	struct r600_common_screen	*screen;
+	struct si_screen		*screen;
 	struct radeon_winsys		*ws;
 	struct radeon_winsys_ctx	*ctx;
 	enum radeon_family		family;
 	enum chip_class			chip_class;
 	struct r600_ring		gfx;
 	struct r600_ring		dma;
 	struct pipe_fence_handle	*last_gfx_fence;
 	struct pipe_fence_handle	*last_sdma_fence;
 	struct r600_resource		*eop_bug_scratch;
 	unsigned			num_gfx_cs_flushes;
@@ -594,92 +522,92 @@ struct r600_common_context {
 				enum ring_type ring);
 };
 
 /* r600_buffer_common.c */
 bool si_rings_is_buffer_referenced(struct r600_common_context *ctx,
 				   struct pb_buffer *buf,
 				   enum radeon_bo_usage usage);
 void *si_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 				    struct r600_resource *resource,
 				    unsigned usage);
-void si_init_resource_fields(struct r600_common_screen *rscreen,
+void si_init_resource_fields(struct si_screen *sscreen,
 			     struct r600_resource *res,
 			     uint64_t size, unsigned alignment);
-bool si_alloc_resource(struct r600_common_screen *rscreen,
+bool si_alloc_resource(struct si_screen *sscreen,
 		       struct r600_resource *res);
 struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
 					       unsigned flags,
 					       unsigned usage,
 					       unsigned size,
 					       unsigned alignment);
 void si_replace_buffer_storage(struct pipe_context *ctx,
 			       struct pipe_resource *dst,
 			       struct pipe_resource *src);
 void si_init_screen_buffer_functions(struct si_screen *sscreen);
 void si_init_buffer_functions(struct si_context *sctx);
 
 /* r600_common_pipe.c */
 void si_gfx_write_event_eop(struct r600_common_context *ctx,
 			    unsigned event, unsigned event_flags,
 			    unsigned data_sel,
 			    struct r600_resource *buf, uint64_t va,
 			    uint32_t new_fence, unsigned query_type);
-unsigned si_gfx_write_fence_dwords(struct r600_common_screen *screen);
+unsigned si_gfx_write_fence_dwords(struct si_screen *screen);
 void si_gfx_wait_fence(struct r600_common_context *ctx,
 		       uint64_t va, uint32_t ref, uint32_t mask);
 bool si_common_context_init(struct r600_common_context *rctx,
-			    struct r600_common_screen *rscreen,
+			    struct si_screen *sscreen,
 			    unsigned context_flags);
 void si_common_context_cleanup(struct r600_common_context *rctx);
-void si_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
+void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
 			    uint64_t offset, uint64_t size, unsigned value);
 void si_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
 		       struct r600_resource *dst, struct r600_resource *src);
 void si_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
 		struct radeon_saved_cs *saved, bool get_buffer_list);
 void si_clear_saved_cs(struct radeon_saved_cs *saved);
 bool si_check_device_reset(struct r600_common_context *rctx);
 
 /* r600_gpu_load.c */
-void si_gpu_load_kill_thread(struct r600_common_screen *rscreen);
-uint64_t si_begin_counter(struct r600_common_screen *rscreen, unsigned type);
-unsigned si_end_counter(struct r600_common_screen *rscreen, unsigned type,
+void si_gpu_load_kill_thread(struct si_screen *sscreen);
+uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
+unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
 			uint64_t begin);
 
 /* r600_perfcounters.c */
-void si_perfcounters_destroy(struct r600_common_screen *rscreen);
+void si_perfcounters_destroy(struct si_screen *sscreen);
 
 /* r600_query.c */
-void si_init_screen_query_functions(struct r600_common_screen *rscreen);
+void si_init_screen_query_functions(struct si_screen *sscreen);
 void si_init_query_functions(struct r600_common_context *rctx);
 void si_suspend_queries(struct r600_common_context *ctx);
 void si_resume_queries(struct r600_common_context *ctx);
 
 /* r600_texture.c */
 bool si_prepare_for_dma_blit(struct r600_common_context *rctx,
 			     struct r600_texture *rdst,
 			     unsigned dst_level, unsigned dstx,
 			     unsigned dsty, unsigned dstz,
 			     struct r600_texture *rsrc,
 			     unsigned src_level,
 			     const struct pipe_box *src_box);
-void si_texture_get_fmask_info(struct r600_common_screen *rscreen,
+void si_texture_get_fmask_info(struct si_screen *sscreen,
 			       struct r600_texture *rtex,
 			       unsigned nr_samples,
 			       struct r600_fmask_info *out);
-void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
+void si_texture_get_cmask_info(struct si_screen *sscreen,
 			       struct r600_texture *rtex,
 			       struct r600_cmask_info *out);
 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
 				   struct pipe_resource *texture,
 				   struct r600_texture **staging);
-void si_print_texture_info(struct r600_common_screen *rscreen,
+void si_print_texture_info(struct si_screen *sscreen,
 			   struct r600_texture *rtex, struct u_log_context *log);
 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
 					const struct pipe_resource *templ);
 bool vi_dcc_formats_compatible(enum pipe_format format1,
 			       enum pipe_format format2);
 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
 				     unsigned level,
 				     enum pipe_format view_format);
 void vi_disable_dcc_if_incompatible_format(struct r600_common_context *rctx,
 					   struct pipe_resource *tex,
@@ -694,21 +622,21 @@ unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
 void vi_separate_dcc_try_enable(struct r600_common_context *rctx,
 				struct r600_texture *tex);
 void vi_separate_dcc_start_query(struct pipe_context *ctx,
 				 struct r600_texture *tex);
 void vi_separate_dcc_stop_query(struct pipe_context *ctx,
 				struct r600_texture *tex);
 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
 					     struct r600_texture *tex);
 bool si_texture_disable_dcc(struct r600_common_context *rctx,
 			    struct r600_texture *rtex);
-void si_init_screen_texture_functions(struct r600_common_screen *rscreen);
+void si_init_screen_texture_functions(struct si_screen *sscreen);
 void si_init_context_texture_functions(struct r600_common_context *rctx);
 
 
 /* Inline helpers. */
 
 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 {
 	return (struct r600_resource*)r;
 }
 
diff --git a/src/gallium/drivers/radeon/r600_query.c b/src/gallium/drivers/radeon/r600_query.c
index de52167..ab0bcec 100644
--- a/src/gallium/drivers/radeon/r600_query.c
+++ b/src/gallium/drivers/radeon/r600_query.c
@@ -48,26 +48,26 @@ struct r600_query_sw {
 	uint64_t begin_result;
 	uint64_t end_result;
 
 	uint64_t begin_time;
 	uint64_t end_time;
 
 	/* Fence for GPU_FINISHED. */
 	struct pipe_fence_handle *fence;
 };
 
-static void r600_query_sw_destroy(struct r600_common_screen *rscreen,
+static void r600_query_sw_destroy(struct si_screen *sscreen,
 				  struct r600_query *rquery)
 {
 	struct r600_query_sw *query = (struct r600_query_sw *)rquery;
 
-	rscreen->b.fence_reference(&rscreen->b, &query->fence, NULL);
+	sscreen->b.fence_reference(&sscreen->b, &query->fence, NULL);
 	FREE(query);
 }
 
 static enum radeon_value_id winsys_id_from_type(unsigned type)
 {
 	switch (type) {
 	case R600_QUERY_REQUESTED_VRAM: return RADEON_REQUESTED_VRAM_MEMORY;
 	case R600_QUERY_REQUESTED_GTT: return RADEON_REQUESTED_GTT_MEMORY;
 	case R600_QUERY_MAPPED_VRAM: return RADEON_MAPPED_VRAM;
 	case R600_QUERY_MAPPED_GTT: return RADEON_MAPPED_GTT;
@@ -492,81 +492,81 @@ static struct pipe_query *r600_query_sw_create(unsigned query_type)
 	query = CALLOC_STRUCT(r600_query_sw);
 	if (!query)
 		return NULL;
 
 	query->b.type = query_type;
 	query->b.ops = &sw_query_ops;
 
 	return (struct pipe_query *)query;
 }
 
-void si_query_hw_destroy(struct r600_common_screen *rscreen,
+void si_query_hw_destroy(struct si_screen *sscreen,
 			 struct r600_query *rquery)
 {
 	struct r600_query_hw *query = (struct r600_query_hw *)rquery;
 	struct r600_query_buffer *prev = query->buffer.previous;
 
 	/* Release all query buffers. */
 	while (prev) {
 		struct r600_query_buffer *qbuf = prev;
 		prev = prev->previous;
 		r600_resource_reference(&qbuf->buf, NULL);
 		FREE(qbuf);
 	}
 
 	r600_resource_reference(&query->buffer.buf, NULL);
 	r600_resource_reference(&query->workaround_buf, NULL);
 	FREE(rquery);
 }
 
-static struct r600_resource *r600_new_query_buffer(struct r600_common_screen *rscreen,
+static struct r600_resource *r600_new_query_buffer(struct si_screen *sscreen,
 						   struct r600_query_hw *query)
 {
 	unsigned buf_size = MAX2(query->result_size,
-				 rscreen->info.min_alloc_size);
+				 sscreen->info.min_alloc_size);
 
 	/* Queries are normally read by the CPU after
 	 * being written by the gpu, hence staging is probably a good
 	 * usage pattern.
 	 */
 	struct r600_resource *buf = (struct r600_resource*)
-		pipe_buffer_create(&rscreen->b, 0,
+		pipe_buffer_create(&sscreen->b, 0,
 				   PIPE_USAGE_STAGING, buf_size);
 	if (!buf)
 		return NULL;
 
-	if (!query->ops->prepare_buffer(rscreen, query, buf)) {
+	if (!query->ops->prepare_buffer(sscreen, query, buf)) {
 		r600_resource_reference(&buf, NULL);
 		return NULL;
 	}
 
 	return buf;
 }
 
-static bool r600_query_hw_prepare_buffer(struct r600_common_screen *rscreen,
+static bool r600_query_hw_prepare_buffer(struct si_screen *sscreen,
 					 struct r600_query_hw *query,
 					 struct r600_resource *buffer)
 {
 	/* Callers ensure that the buffer is currently unused by the GPU. */
-	uint32_t *results = rscreen->ws->buffer_map(buffer->buf, NULL,
+	uint32_t *results = sscreen->ws->buffer_map(buffer->buf, NULL,
 						   PIPE_TRANSFER_WRITE |
 						   PIPE_TRANSFER_UNSYNCHRONIZED);
 	if (!results)
 		return false;
 
 	memset(results, 0, buffer->b.b.width0);
 
 	if (query->b.type == PIPE_QUERY_OCCLUSION_COUNTER ||
 	    query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE ||
 	    query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
-		unsigned max_rbs = rscreen->info.num_render_backends;
-		unsigned enabled_rb_mask = rscreen->info.enabled_rb_mask;
+		unsigned max_rbs = sscreen->info.num_render_backends;
+		unsigned enabled_rb_mask = sscreen->info.enabled_rb_mask;
 		unsigned num_results;
 		unsigned i, j;
 
 		/* Set top bits for unused backends. */
 		num_results = buffer->b.b.width0 / query->result_size;
 		for (j = 0; j < num_results; j++) {
 			for (i = 0; i < max_rbs; i++) {
 				if (!(enabled_rb_mask & (1<<i))) {
 					results[(i * 4)+1] = 0x80000000;
 					results[(i * 4)+3] = 0x80000000;
@@ -596,73 +596,73 @@ static struct r600_query_ops query_hw_ops = {
 };
 
 static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
 					struct r600_query_hw *query,
 					struct r600_resource *buffer,
 					uint64_t va);
 static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
 				       struct r600_query_hw *query,
 				       struct r600_resource *buffer,
 				       uint64_t va);
-static void r600_query_hw_add_result(struct r600_common_screen *rscreen,
+static void r600_query_hw_add_result(struct si_screen *sscreen,
 				     struct r600_query_hw *, void *buffer,
 				     union pipe_query_result *result);
 static void r600_query_hw_clear_result(struct r600_query_hw *,
 				       union pipe_query_result *);
 
 static struct r600_query_hw_ops query_hw_default_hw_ops = {
 	.prepare_buffer = r600_query_hw_prepare_buffer,
 	.emit_start = r600_query_hw_do_emit_start,
 	.emit_stop = r600_query_hw_do_emit_stop,
 	.clear_result = r600_query_hw_clear_result,
 	.add_result = r600_query_hw_add_result,
 };
 
-bool si_query_hw_init(struct r600_common_screen *rscreen,
+bool si_query_hw_init(struct si_screen *sscreen,
 		      struct r600_query_hw *query)
 {
-	query->buffer.buf = r600_new_query_buffer(rscreen, query);
+	query->buffer.buf = r600_new_query_buffer(sscreen, query);
 	if (!query->buffer.buf)
 		return false;
 
 	return true;
 }
 
-static struct pipe_query *r600_query_hw_create(struct r600_common_screen *rscreen,
+static struct pipe_query *r600_query_hw_create(struct si_screen *sscreen,
 					       unsigned query_type,
 					       unsigned index)
 {
 	struct r600_query_hw *query = CALLOC_STRUCT(r600_query_hw);
 	if (!query)
 		return NULL;
 
 	query->b.type = query_type;
 	query->b.ops = &query_hw_ops;
 	query->ops = &query_hw_default_hw_ops;
 
 	switch (query_type) {
 	case PIPE_QUERY_OCCLUSION_COUNTER:
 	case PIPE_QUERY_OCCLUSION_PREDICATE:
 	case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
-		query->result_size = 16 * rscreen->info.num_render_backends;
+		query->result_size = 16 * sscreen->info.num_render_backends;
 		query->result_size += 16; /* for the fence + alignment */
 		query->num_cs_dw_begin = 6;
-		query->num_cs_dw_end = 6 + si_gfx_write_fence_dwords(rscreen);
+		query->num_cs_dw_end = 6 + si_gfx_write_fence_dwords(sscreen);
 		break;
 	case PIPE_QUERY_TIME_ELAPSED:
 		query->result_size = 24;
 		query->num_cs_dw_begin = 8;
-		query->num_cs_dw_end = 8 + si_gfx_write_fence_dwords(rscreen);
+		query->num_cs_dw_end = 8 + si_gfx_write_fence_dwords(sscreen);
 		break;
 	case PIPE_QUERY_TIMESTAMP:
 		query->result_size = 16;
-		query->num_cs_dw_end = 8 + si_gfx_write_fence_dwords(rscreen);
+		query->num_cs_dw_end = 8 + si_gfx_write_fence_dwords(sscreen);
 		query->flags = R600_QUERY_HW_FLAG_NO_START;
 		break;
 	case PIPE_QUERY_PRIMITIVES_EMITTED:
 	case PIPE_QUERY_PRIMITIVES_GENERATED:
 	case PIPE_QUERY_SO_STATISTICS:
 	case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
 		/* NumPrimitivesWritten, PrimitiveStorageNeeded. */
 		query->result_size = 32;
 		query->num_cs_dw_begin = 6;
 		query->num_cs_dw_end = 6;
@@ -672,29 +672,29 @@ static struct pipe_query *r600_query_hw_create(struct r600_common_screen *rscree
 		/* NumPrimitivesWritten, PrimitiveStorageNeeded. */
 		query->result_size = 32 * R600_MAX_STREAMS;
 		query->num_cs_dw_begin = 6 * R600_MAX_STREAMS;
 		query->num_cs_dw_end = 6 * R600_MAX_STREAMS;
 		break;
 	case PIPE_QUERY_PIPELINE_STATISTICS:
 		/* 11 values on GCN. */
 		query->result_size = 11 * 16;
 		query->result_size += 8; /* for the fence + alignment */
 		query->num_cs_dw_begin = 6;
-		query->num_cs_dw_end = 6 + si_gfx_write_fence_dwords(rscreen);
+		query->num_cs_dw_end = 6 + si_gfx_write_fence_dwords(sscreen);
 		break;
 	default:
 		assert(0);
 		FREE(query);
 		return NULL;
 	}
 
-	if (!si_query_hw_init(rscreen, query)) {
+	if (!si_query_hw_init(sscreen, query)) {
 		FREE(query);
 		return NULL;
 	}
 
 	return (struct pipe_query *)query;
 }
 
 static void r600_update_occlusion_query_state(struct r600_common_context *rctx,
 					      unsigned type, int diff)
 {
@@ -1018,29 +1018,29 @@ static void r600_emit_query_predication(struct r600_common_context *ctx,
 				op |= PREDICATION_CONTINUE;
 			}
 
 			results_base += query->result_size;
 		}
 	}
 }
 
 static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type, unsigned index)
 {
-	struct r600_common_screen *rscreen =
-		(struct r600_common_screen *)ctx->screen;
+	struct si_screen *sscreen =
+		(struct si_screen *)ctx->screen;
 
 	if (query_type == PIPE_QUERY_TIMESTAMP_DISJOINT ||
 	    query_type == PIPE_QUERY_GPU_FINISHED ||
 	    query_type >= PIPE_QUERY_DRIVER_SPECIFIC)
 		return r600_query_sw_create(query_type);
 
-	return r600_query_hw_create(rscreen, query_type, index);
+	return r600_query_hw_create(sscreen, query_type, index);
 }
 
 static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
 {
 	struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 	struct r600_query *rquery = (struct r600_query *)query;
 
 	rquery->ops->destroy(rctx->screen, rquery);
 }
 
@@ -1212,26 +1212,26 @@ static unsigned r600_query_read_result(void *map, unsigned start_index, unsigned
 	end = (uint64_t)current_result[end_index] |
 	      (uint64_t)current_result[end_index+1] << 32;
 
 	if (!test_status_bit ||
 	    ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) {
 		return end - start;
 	}
 	return 0;
 }
 
-static void r600_query_hw_add_result(struct r600_common_screen *rscreen,
+static void r600_query_hw_add_result(struct si_screen *sscreen,
 				     struct r600_query_hw *query,
 				     void *buffer,
 				     union pipe_query_result *result)
 {
-	unsigned max_rbs = rscreen->info.num_render_backends;
+	unsigned max_rbs = sscreen->info.num_render_backends;
 
 	switch (query->b.type) {
 	case PIPE_QUERY_OCCLUSION_COUNTER: {
 		for (unsigned i = 0; i < max_rbs; ++i) {
 			unsigned results_base = i * 16;
 			result->u64 +=
 				r600_query_read_result(buffer + results_base, 0, 2, true);
 		}
 		break;
 	}
@@ -1355,51 +1355,51 @@ static void r600_get_query_result_resource(struct pipe_context *ctx,
 static void r600_query_hw_clear_result(struct r600_query_hw *query,
 				       union pipe_query_result *result)
 {
 	util_query_clear_result(result, query->b.type);
 }
 
 bool si_query_hw_get_result(struct r600_common_context *rctx,
 			    struct r600_query *rquery,
 			    bool wait, union pipe_query_result *result)
 {
-	struct r600_common_screen *rscreen = rctx->screen;
+	struct si_screen *sscreen = rctx->screen;
 	struct r600_query_hw *query = (struct r600_query_hw *)rquery;
 	struct r600_query_buffer *qbuf;
 
 	query->ops->clear_result(query, result);
 
 	for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
 		unsigned usage = PIPE_TRANSFER_READ |
 				 (wait ? 0 : PIPE_TRANSFER_DONTBLOCK);
 		unsigned results_base = 0;
 		void *map;
 
 		if (rquery->b.flushed)
 			map = rctx->ws->buffer_map(qbuf->buf->buf, NULL, usage);
 		else
 			map = si_buffer_map_sync_with_rings(rctx, qbuf->buf, usage);
 
 		if (!map)
 			return false;
 
 		while (results_base != qbuf->results_end) {
-			query->ops->add_result(rscreen, query, map + results_base,
+			query->ops->add_result(sscreen, query, map + results_base,
 					       result);
 			results_base += query->result_size;
 		}
 	}
 
 	/* Convert the time to expected units. */
 	if (rquery->type == PIPE_QUERY_TIME_ELAPSED ||
 	    rquery->type == PIPE_QUERY_TIMESTAMP) {
-		result->u64 = (1000000 * result->u64) / rscreen->info.clock_crystal_freq;
+		result->u64 = (1000000 * result->u64) / sscreen->info.clock_crystal_freq;
 	}
 	return true;
 }
 
 /* Create the compute shader that is used to collect the results.
  *
  * One compute grid with a single thread is launched for every query result
  * buffer. The thread (optionally) reads a previous summary buffer, then
  * accumulates data from the query result buffer, and writes the result either
  * to a summary buffer to be consumed by the next grid invocation or to the
@@ -1979,97 +1979,97 @@ static struct pipe_driver_query_info r600_driver_query_list[] = {
 	X("GPU-me-busy",		GPU_ME_BUSY,		UINT64, AVERAGE),
 	X("GPU-surf-sync-busy",		GPU_SURF_SYNC_BUSY,	UINT64, AVERAGE),
 	X("GPU-cp-dma-busy",		GPU_CP_DMA_BUSY,	UINT64, AVERAGE),
 	X("GPU-scratch-ram-busy",	GPU_SCRATCH_RAM_BUSY,	UINT64, AVERAGE),
 };
 
 #undef X
 #undef XG
 #undef XFULL
 
-static unsigned r600_get_num_queries(struct r600_common_screen *rscreen)
+static unsigned r600_get_num_queries(struct si_screen *sscreen)
 {
-	if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
+	if (sscreen->info.drm_major == 2 && sscreen->info.drm_minor >= 42)
 		return ARRAY_SIZE(r600_driver_query_list);
-	else if (rscreen->info.drm_major == 3) {
-		if (rscreen->chip_class >= VI)
+	else if (sscreen->info.drm_major == 3) {
+		if (sscreen->info.chip_class >= VI)
 			return ARRAY_SIZE(r600_driver_query_list);
 		else
 			return ARRAY_SIZE(r600_driver_query_list) - 7;
 	}
 	else
 		return ARRAY_SIZE(r600_driver_query_list) - 25;
 }
 
 static int r600_get_driver_query_info(struct pipe_screen *screen,
 				      unsigned index,
 				      struct pipe_driver_query_info *info)
 {
-	struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
-	unsigned num_queries = r600_get_num_queries(rscreen);
+	struct si_screen *sscreen = (struct si_screen*)screen;
+	unsigned num_queries = r600_get_num_queries(sscreen);
 
 	if (!info) {
 		unsigned num_perfcounters =
-			si_get_perfcounter_info(rscreen, 0, NULL);
+			si_get_perfcounter_info(sscreen, 0, NULL);
 
 		return num_queries + num_perfcounters;
 	}
 
 	if (index >= num_queries)
-		return si_get_perfcounter_info(rscreen, index - num_queries, info);
+		return si_get_perfcounter_info(sscreen, index - num_queries, info);
 
 	*info = r600_driver_query_list[index];
 
 	switch (info->query_type) {
 	case R600_QUERY_REQUESTED_VRAM:
 	case R600_QUERY_VRAM_USAGE:
 	case R600_QUERY_MAPPED_VRAM:
-		info->max_value.u64 = rscreen->info.vram_size;
+		info->max_value.u64 = sscreen->info.vram_size;
 		break;
 	case R600_QUERY_REQUESTED_GTT:
 	case R600_QUERY_GTT_USAGE:
 	case R600_QUERY_MAPPED_GTT:
-		info->max_value.u64 = rscreen->info.gart_size;
+		info->max_value.u64 = sscreen->info.gart_size;
 		break;
 	case R600_QUERY_GPU_TEMPERATURE:
 		info->max_value.u64 = 125;
 		break;
 	case R600_QUERY_VRAM_VIS_USAGE:
-		info->max_value.u64 = rscreen->info.vram_vis_size;
+		info->max_value.u64 = sscreen->info.vram_vis_size;
 		break;
 	}
 
-	if (info->group_id != ~(unsigned)0 && rscreen->perfcounters)
-		info->group_id += rscreen->perfcounters->num_groups;
+	if (info->group_id != ~(unsigned)0 && sscreen->perfcounters)
+		info->group_id += sscreen->perfcounters->num_groups;
 
 	return 1;
 }
 
 /* Note: Unfortunately, GPUPerfStudio hardcodes the order of hardware
  * performance counter groups, so be careful when changing this and related
  * functions.
  */
 static int r600_get_driver_query_group_info(struct pipe_screen *screen,
 					    unsigned index,
 					    struct pipe_driver_query_group_info *info)
 {
-	struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
+	struct si_screen *sscreen = (struct si_screen *)screen;
 	unsigned num_pc_groups = 0;
 
-	if (rscreen->perfcounters)
-		num_pc_groups = rscreen->perfcounters->num_groups;
+	if (sscreen->perfcounters)
+		num_pc_groups = sscreen->perfcounters->num_groups;
 
 	if (!info)
 		return num_pc_groups + R600_NUM_SW_QUERY_GROUPS;
 
 	if (index < num_pc_groups)
-		return si_get_perfcounter_group_info(rscreen, index, info);
+		return si_get_perfcounter_group_info(sscreen, index, info);
 
 	index -= num_pc_groups;
 	if (index >= R600_NUM_SW_QUERY_GROUPS)
 		return 0;
 
 	info->name = "GPIN";
 	info->max_active_queries = 5;
 	info->num_queries = 5;
 	return 1;
 }
@@ -2078,21 +2078,21 @@ void si_init_query_functions(struct r600_common_context *rctx)
 {
 	rctx->b.create_query = r600_create_query;
 	rctx->b.create_batch_query = si_create_batch_query;
 	rctx->b.destroy_query = r600_destroy_query;
 	rctx->b.begin_query = r600_begin_query;
 	rctx->b.end_query = r600_end_query;
 	rctx->b.get_query_result = r600_get_query_result;
 	rctx->b.get_query_result_resource = r600_get_query_result_resource;
 	rctx->render_cond_atom.emit = r600_emit_query_predication;
 
-	if (((struct r600_common_screen*)rctx->b.screen)->info.num_render_backends > 0)
+	if (((struct si_screen*)rctx->b.screen)->info.num_render_backends > 0)
 	    rctx->b.render_condition = r600_render_condition;
 
 	LIST_INITHEAD(&rctx->active_queries);
 }
 
-void si_init_screen_query_functions(struct r600_common_screen *rscreen)
+void si_init_screen_query_functions(struct si_screen *sscreen)
 {
-	rscreen->b.get_driver_query_info = r600_get_driver_query_info;
-	rscreen->b.get_driver_query_group_info = r600_get_driver_query_group_info;
+	sscreen->b.get_driver_query_info = r600_get_driver_query_info;
+	sscreen->b.get_driver_query_group_info = r600_get_driver_query_group_info;
 }
diff --git a/src/gallium/drivers/radeon/r600_query.h b/src/gallium/drivers/radeon/r600_query.h
index bb81e50..db86dc1 100644
--- a/src/gallium/drivers/radeon/r600_query.h
+++ b/src/gallium/drivers/radeon/r600_query.h
@@ -24,21 +24,21 @@
 #ifndef R600_QUERY_H
 #define R600_QUERY_H
 
 #include "util/u_threaded_context.h"
 
 struct pipe_context;
 struct pipe_query;
 struct pipe_resource;
 
 struct r600_common_context;
-struct r600_common_screen;
+struct si_screen;
 struct r600_query;
 struct r600_query_hw;
 struct r600_resource;
 
 enum {
 	R600_QUERY_DRAW_CALLS = PIPE_QUERY_DRIVER_SPECIFIC,
 	R600_QUERY_DECOMPRESS_CALLS,
 	R600_QUERY_MRT_DRAW_CALLS,
 	R600_QUERY_PRIM_RESTART_CALLS,
 	R600_QUERY_SPILL_DRAW_CALLS,
@@ -111,21 +111,21 @@ enum {
 
 	R600_QUERY_FIRST_PERFCOUNTER = PIPE_QUERY_DRIVER_SPECIFIC + 100,
 };
 
 enum {
 	R600_QUERY_GROUP_GPIN = 0,
 	R600_NUM_SW_QUERY_GROUPS
 };
 
 struct r600_query_ops {
-	void (*destroy)(struct r600_common_screen *, struct r600_query *);
+	void (*destroy)(struct si_screen *, struct r600_query *);
 	bool (*begin)(struct r600_common_context *, struct r600_query *);
 	bool (*end)(struct r600_common_context *, struct r600_query *);
 	bool (*get_result)(struct r600_common_context *,
 			   struct r600_query *, bool wait,
 			   union pipe_query_result *result);
 	void (*get_result_resource)(struct r600_common_context *,
 				    struct r600_query *, bool wait,
 				    enum pipe_query_value_type result_type,
 				    int index,
 				    struct pipe_resource *resource,
@@ -141,31 +141,31 @@ struct r600_query {
 };
 
 enum {
 	R600_QUERY_HW_FLAG_NO_START = (1 << 0),
 	/* gap */
 	/* whether begin_query doesn't clear the result */
 	R600_QUERY_HW_FLAG_BEGIN_RESUMES = (1 << 2),
 };
 
 struct r600_query_hw_ops {
-	bool (*prepare_buffer)(struct r600_common_screen *,
+	bool (*prepare_buffer)(struct si_screen *,
 			       struct r600_query_hw *,
 			       struct r600_resource *);
 	void (*emit_start)(struct r600_common_context *,
 			   struct r600_query_hw *,
 			   struct r600_resource *buffer, uint64_t va);
 	void (*emit_stop)(struct r600_common_context *,
 			  struct r600_query_hw *,
 			  struct r600_resource *buffer, uint64_t va);
 	void (*clear_result)(struct r600_query_hw *, union pipe_query_result *);
-	void (*add_result)(struct r600_common_screen *screen,
+	void (*add_result)(struct si_screen *screen,
 			   struct r600_query_hw *, void *buffer,
 			   union pipe_query_result *result);
 };
 
 struct r600_query_buffer {
 	/* The buffer where query results are stored. */
 	struct r600_resource		*buf;
 	/* Offset of the next free result after current query data */
 	unsigned			results_end;
 	/* If a query buffer is full, a new buffer is created and the old one
@@ -190,23 +190,23 @@ struct r600_query_hw {
 	/* Linked list of queries */
 	struct list_head list;
 	/* For transform feedback: which stream the query is for */
 	unsigned stream;
 
 	/* Workaround via compute shader */
 	struct r600_resource *workaround_buf;
 	unsigned workaround_offset;
 };
 
-bool si_query_hw_init(struct r600_common_screen *rscreen,
+bool si_query_hw_init(struct si_screen *sscreen,
 		      struct r600_query_hw *query);
-void si_query_hw_destroy(struct r600_common_screen *rscreen,
+void si_query_hw_destroy(struct si_screen *sscreen,
 			 struct r600_query *rquery);
 bool si_query_hw_begin(struct r600_common_context *rctx,
 		       struct r600_query *rquery);
 bool si_query_hw_end(struct r600_common_context *rctx,
 		     struct r600_query *rquery);
 bool si_query_hw_get_result(struct r600_common_context *rctx,
 			    struct r600_query *rquery,
 			    bool wait,
 			    union pipe_query_result *result);
 
@@ -281,39 +281,39 @@ struct r600_perfcounters {
 			    unsigned count, unsigned *selectors);
 	void (*emit_start)(struct r600_common_context *,
 			  struct r600_resource *buffer, uint64_t va);
 	void (*emit_stop)(struct r600_common_context *,
 			  struct r600_resource *buffer, uint64_t va);
 	void (*emit_read)(struct r600_common_context *,
 			  struct r600_perfcounter_block *,
 			  unsigned count, unsigned *selectors,
 			  struct r600_resource *buffer, uint64_t va);
 
-	void (*cleanup)(struct r600_common_screen *);
+	void (*cleanup)(struct si_screen *);
 
 	bool separate_se;
 	bool separate_instance;
 };
 
 struct pipe_query *si_create_batch_query(struct pipe_context *ctx,
 					 unsigned num_queries,
 					 unsigned *query_types);
 
-int si_get_perfcounter_info(struct r600_common_screen *,
+int si_get_perfcounter_info(struct si_screen *,
 			    unsigned index,
 			    struct pipe_driver_query_info *info);
-int si_get_perfcounter_group_info(struct r600_common_screen *,
+int si_get_perfcounter_group_info(struct si_screen *,
 				  unsigned index,
 				  struct pipe_driver_query_group_info *info);
 
 bool si_perfcounters_init(struct r600_perfcounters *, unsigned num_blocks);
-void si_perfcounters_add_block(struct r600_common_screen *,
+void si_perfcounters_add_block(struct si_screen *,
 			       struct r600_perfcounters *,
 			       const char *name, unsigned flags,
 			       unsigned counters, unsigned selectors,
 			       unsigned instances, void *data);
 void si_perfcounters_do_destroy(struct r600_perfcounters *);
 void si_query_hw_reset_buffers(struct r600_common_context *rctx,
 			       struct r600_query_hw *query);
 
 struct r600_qbo_state {
 	void *saved_compute;
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 1051a3b..bc72e73 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -29,24 +29,24 @@
 #include "util/u_memory.h"
 #include "util/u_pack_color.h"
 #include "util/u_resource.h"
 #include "util/u_surface.h"
 #include "util/os_time.h"
 #include <errno.h>
 #include <inttypes.h>
 #include "state_tracker/drm_driver.h"
 #include "amd/common/sid.h"
 
-static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
+static void r600_texture_discard_cmask(struct si_screen *sscreen,
 				       struct r600_texture *rtex);
 static enum radeon_surf_mode
-r600_choose_tiling(struct r600_common_screen *rscreen,
+r600_choose_tiling(struct si_screen *sscreen,
 		   const struct pipe_resource *templ);
 
 
 bool si_prepare_for_dma_blit(struct r600_common_context *rctx,
 			     struct r600_texture *rdst,
 			     unsigned dst_level, unsigned dstx,
 			     unsigned dsty, unsigned dstz,
 			     struct r600_texture *rsrc,
 			     unsigned src_level,
 			     const struct pipe_box *src_box)
@@ -171,27 +171,27 @@ static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600
 					   transfer->box.x, transfer->box.y, transfer->box.z,
 					   src, 0, &sbox);
 		return;
 	}
 
 	rctx->dma_copy(ctx, dst, transfer->level,
 		       transfer->box.x, transfer->box.y, transfer->box.z,
 		       src, 0, &sbox);
 }
 
-static unsigned r600_texture_get_offset(struct r600_common_screen *rscreen,
+static unsigned r600_texture_get_offset(struct si_screen *sscreen,
 					struct r600_texture *rtex, unsigned level,
 					const struct pipe_box *box,
 					unsigned *stride,
 					unsigned *layer_stride)
 {
-	if (rscreen->chip_class >= GFX9) {
+	if (sscreen->info.chip_class >= GFX9) {
 		*stride = rtex->surface.u.gfx9.surf_pitch * rtex->surface.bpe;
 		*layer_stride = rtex->surface.u.gfx9.surf_slice_size;
 
 		if (!box)
 			return 0;
 
 		/* Each texture is an array of slices. Each slice is an array
 		 * of mipmap levels. */
 		return box->z * rtex->surface.u.gfx9.surf_slice_size +
 		       rtex->surface.u.gfx9.offset[level] +
@@ -210,21 +210,21 @@ static unsigned r600_texture_get_offset(struct r600_common_screen *rscreen,
 		/* Each texture is an array of mipmap levels. Each level is
 		 * an array of slices. */
 		return rtex->surface.u.legacy.level[level].offset +
 		       box->z * (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 +
 		       (box->y / rtex->surface.blk_h *
 		        rtex->surface.u.legacy.level[level].nblk_x +
 		        box->x / rtex->surface.blk_w) * rtex->surface.bpe;
 	}
 }
 
-static int r600_init_surface(struct r600_common_screen *rscreen,
+static int r600_init_surface(struct si_screen *sscreen,
 			     struct radeon_surf *surface,
 			     const struct pipe_resource *ptex,
 			     enum radeon_surf_mode array_mode,
 			     unsigned pitch_in_bytes_override,
 			     unsigned offset,
 			     bool is_imported,
 			     bool is_scanout,
 			     bool is_flushed_depth,
 			     bool tc_compatible_htile)
 {
@@ -242,115 +242,115 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
 		bpe = 4; /* stencil is allocated separately on evergreen */
 	} else {
 		bpe = util_format_get_blocksize(ptex->format);
 		assert(util_is_power_of_two(bpe));
 	}
 
 	if (!is_flushed_depth && is_depth) {
 		flags |= RADEON_SURF_ZBUFFER;
 
 		if (tc_compatible_htile &&
-		    (rscreen->chip_class >= GFX9 ||
+		    (sscreen->info.chip_class >= GFX9 ||
 		     array_mode == RADEON_SURF_MODE_2D)) {
 			/* TC-compatible HTILE only supports Z32_FLOAT.
 			 * GFX9 also supports Z16_UNORM.
 			 * On VI, promote Z16 to Z32. DB->CB copies will convert
 			 * the format for transfers.
 			 */
-			if (rscreen->chip_class == VI)
+			if (sscreen->info.chip_class == VI)
 				bpe = 4;
 
 			flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
 		}
 
 		if (is_stencil)
 			flags |= RADEON_SURF_SBUFFER;
 	}
 
-	if (rscreen->chip_class >= VI &&
+	if (sscreen->info.chip_class >= VI &&
 	    (ptex->flags & R600_RESOURCE_FLAG_DISABLE_DCC ||
 	     ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT ||
 	     /* DCC MSAA array textures are disallowed due to incomplete clear impl. */
 	     (ptex->nr_samples >= 2 &&
-	      (!rscreen->dcc_msaa_allowed || ptex->array_size > 1))))
+	      (!sscreen->dcc_msaa_allowed || ptex->array_size > 1))))
 		flags |= RADEON_SURF_DISABLE_DCC;
 
 	if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
 		/* This should catch bugs in gallium users setting incorrect flags. */
 		assert(ptex->nr_samples <= 1 &&
 		       ptex->array_size == 1 &&
 		       ptex->depth0 == 1 &&
 		       ptex->last_level == 0 &&
 		       !(flags & RADEON_SURF_Z_OR_SBUFFER));
 
 		flags |= RADEON_SURF_SCANOUT;
 	}
 
 	if (ptex->bind & PIPE_BIND_SHARED)
 		flags |= RADEON_SURF_SHAREABLE;
 	if (is_imported)
 		flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
 	if (!(ptex->flags & R600_RESOURCE_FLAG_FORCE_TILING))
 		flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
 
-	r = rscreen->ws->surface_init(rscreen->ws, ptex, flags, bpe,
+	r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe,
 				      array_mode, surface);
 	if (r) {
 		return r;
 	}
 
-	if (rscreen->chip_class >= GFX9) {
+	if (sscreen->info.chip_class >= GFX9) {
 		assert(!pitch_in_bytes_override ||
 		       pitch_in_bytes_override == surface->u.gfx9.surf_pitch * bpe);
 		surface->u.gfx9.surf_offset = offset;
 	} else {
 		if (offset) {
 			for (i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
 				surface->u.legacy.level[i].offset += offset;
 		}
 	}
 	return 0;
 }
 
-static void r600_texture_init_metadata(struct r600_common_screen *rscreen,
+static void r600_texture_init_metadata(struct si_screen *sscreen,
 				       struct r600_texture *rtex,
 				       struct radeon_bo_metadata *metadata)
 {
 	struct radeon_surf *surface = &rtex->surface;
 
 	memset(metadata, 0, sizeof(*metadata));
 
-	if (rscreen->chip_class >= GFX9) {
+	if (sscreen->info.chip_class >= GFX9) {
 		metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
 	} else {
 		metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
 					   RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
 		metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
 					   RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
 		metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
 		metadata->u.legacy.bankw = surface->u.legacy.bankw;
 		metadata->u.legacy.bankh = surface->u.legacy.bankh;
 		metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
 		metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
 		metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
 		metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
 		metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
 	}
 }
 
-static void r600_surface_import_metadata(struct r600_common_screen *rscreen,
+static void r600_surface_import_metadata(struct si_screen *sscreen,
 					 struct radeon_surf *surf,
 					 struct radeon_bo_metadata *metadata,
 					 enum radeon_surf_mode *array_mode,
 					 bool *is_scanout)
 {
-	if (rscreen->chip_class >= GFX9) {
+	if (sscreen->info.chip_class >= GFX9) {
 		if (metadata->u.gfx9.swizzle_mode > 0)
 			*array_mode = RADEON_SURF_MODE_2D;
 		else
 			*array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
 
 		*is_scanout = metadata->u.gfx9.swizzle_mode == 0 ||
 			      metadata->u.gfx9.swizzle_mode % 4 == 2;
 
 		surf->u.gfx9.surf.swizzle_mode = metadata->u.gfx9.swizzle_mode;
 	} else {
@@ -368,77 +368,77 @@ static void r600_surface_import_metadata(struct r600_common_screen *rscreen,
 		else
 			*array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
 
 		*is_scanout = metadata->u.legacy.scanout;
 	}
 }
 
 static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx,
 					    struct r600_texture *rtex)
 {
-	struct r600_common_screen *rscreen = rctx->screen;
+	struct si_screen *sscreen = rctx->screen;
 	struct pipe_context *ctx = &rctx->b;
 
-	if (ctx == rscreen->aux_context)
-		mtx_lock(&rscreen->aux_context_lock);
+	if (ctx == sscreen->aux_context)
+		mtx_lock(&sscreen->aux_context_lock);
 
 	ctx->flush_resource(ctx, &rtex->resource.b.b);
 	ctx->flush(ctx, NULL, 0);
 
-	if (ctx == rscreen->aux_context)
-		mtx_unlock(&rscreen->aux_context_lock);
+	if (ctx == sscreen->aux_context)
+		mtx_unlock(&sscreen->aux_context_lock);
 }
 
-static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
+static void r600_texture_discard_cmask(struct si_screen *sscreen,
 				       struct r600_texture *rtex)
 {
 	if (!rtex->cmask.size)
 		return;
 
 	assert(rtex->resource.b.b.nr_samples <= 1);
 
 	/* Disable CMASK. */
 	memset(&rtex->cmask, 0, sizeof(rtex->cmask));
 	rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
 	rtex->dirty_level_mask = 0;
 
 	rtex->cb_color_info &= ~S_028C70_FAST_CLEAR(1);
 
 	if (rtex->cmask_buffer != &rtex->resource)
 	    r600_resource_reference(&rtex->cmask_buffer, NULL);
 
 	/* Notify all contexts about the change. */
-	p_atomic_inc(&rscreen->dirty_tex_counter);
-	p_atomic_inc(&rscreen->compressed_colortex_counter);
+	p_atomic_inc(&sscreen->dirty_tex_counter);
+	p_atomic_inc(&sscreen->compressed_colortex_counter);
 }
 
 static bool r600_can_disable_dcc(struct r600_texture *rtex)
 {
 	/* We can't disable DCC if it can be written by another process. */
 	return rtex->dcc_offset &&
 	       (!rtex->resource.b.is_shared ||
 		!(rtex->resource.external_usage & PIPE_HANDLE_USAGE_WRITE));
 }
 
-static bool r600_texture_discard_dcc(struct r600_common_screen *rscreen,
+static bool r600_texture_discard_dcc(struct si_screen *sscreen,
 				     struct r600_texture *rtex)
 {
 	if (!r600_can_disable_dcc(rtex))
 		return false;
 
 	assert(rtex->dcc_separate_buffer == NULL);
 
 	/* Disable DCC. */
 	rtex->dcc_offset = 0;
 
 	/* Notify all contexts about the change. */
-	p_atomic_inc(&rscreen->dirty_tex_counter);
+	p_atomic_inc(&sscreen->dirty_tex_counter);
 	return true;
 }
 
 /**
  * Disable DCC for the texture. (first decompress, then discard metadata).
  *
  * There is unresolved multi-context synchronization issue between
  * screen::aux_context and the current context. If applications do this with
  * multiple contexts, it's already undefined behavior for them and we don't
  * have to worry about that. The scenario is:
@@ -452,36 +452,36 @@ static bool r600_texture_discard_dcc(struct r600_common_screen *rscreen,
  *   context 2 flushes (new compressed tiles written by the draw calls)
  *   context 1 & 2 read garbage, because DCC is disabled, yet there are
  *   compressed tiled
  *
  * \param rctx  the current context if you have one, or rscreen->aux_context
  *              if you don't.
  */
 bool si_texture_disable_dcc(struct r600_common_context *rctx,
 			    struct r600_texture *rtex)
 {
-	struct r600_common_screen *rscreen = rctx->screen;
+	struct si_screen *sscreen = rctx->screen;
 
 	if (!r600_can_disable_dcc(rtex))
 		return false;
 
-	if (&rctx->b == rscreen->aux_context)
-		mtx_lock(&rscreen->aux_context_lock);
+	if (&rctx->b == sscreen->aux_context)
+		mtx_lock(&sscreen->aux_context_lock);
 
 	/* Decompress DCC. */
 	rctx->decompress_dcc(&rctx->b, rtex);
 	rctx->b.flush(&rctx->b, NULL, 0);
 
-	if (&rctx->b == rscreen->aux_context)
-		mtx_unlock(&rscreen->aux_context_lock);
+	if (&rctx->b == sscreen->aux_context)
+		mtx_unlock(&sscreen->aux_context_lock);
 
-	return r600_texture_discard_dcc(rscreen, rtex);
+	return r600_texture_discard_dcc(sscreen, rtex);
 }
 
 static void r600_reallocate_texture_inplace(struct r600_common_context *rctx,
 					    struct r600_texture *rtex,
 					    unsigned new_bind_flag,
 					    bool invalidate_storage)
 {
 	struct pipe_screen *screen = rctx->b.screen;
 	struct r600_texture *new_tex;
 	struct pipe_resource templ = rtex->resource.b.b;
@@ -558,61 +558,60 @@ static void r600_reallocate_texture_inplace(struct r600_common_context *rctx,
 		assert(!rtex->fmask.size);
 		assert(!rtex->dcc_offset);
 		assert(!rtex->is_depth);
 	}
 
 	r600_texture_reference(&new_tex, NULL);
 
 	p_atomic_inc(&rctx->screen->dirty_tex_counter);
 }
 
-static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
+static uint32_t si_get_bo_metadata_word1(struct si_screen *sscreen)
 {
-	return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
+	return (ATI_VENDOR_ID << 16) | sscreen->info.pci_id;
 }
 
-static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
+static void si_query_opaque_metadata(struct si_screen *sscreen,
 				     struct r600_texture *rtex,
 			             struct radeon_bo_metadata *md)
 {
-	struct si_screen *sscreen = (struct si_screen*)rscreen;
 	struct pipe_resource *res = &rtex->resource.b.b;
 	static const unsigned char swizzle[] = {
 		PIPE_SWIZZLE_X,
 		PIPE_SWIZZLE_Y,
 		PIPE_SWIZZLE_Z,
 		PIPE_SWIZZLE_W
 	};
 	uint32_t desc[8], i;
 	bool is_array = util_resource_is_array_texture(res);
 
 	/* DRM 2.x.x doesn't support this. */
-	if (rscreen->info.drm_major != 3)
+	if (sscreen->info.drm_major != 3)
 		return;
 
 	assert(rtex->dcc_separate_buffer == NULL);
 	assert(rtex->fmask.size == 0);
 
 	/* Metadata image format format version 1:
 	 * [0] = 1 (metadata format identifier)
 	 * [1] = (VENDOR_ID << 16) | PCI_ID
 	 * [2:9] = image descriptor for the whole resource
 	 *         [2] is always 0, because the base address is cleared
 	 *         [9] is the DCC offset bits [39:8] from the beginning of
 	 *             the buffer
 	 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
 	 */
 
 	md->metadata[0] = 1; /* metadata image format version 1 */
 
 	/* TILE_MODE_INDEX is ambiguous without a PCI ID. */
-	md->metadata[1] = si_get_bo_metadata_word1(rscreen);
+	md->metadata[1] = si_get_bo_metadata_word1(sscreen);
 
 	si_make_texture_descriptor(sscreen, rtex, true,
 				   res->target, res->format,
 				   swizzle, 0, res->last_level, 0,
 				   is_array ? res->array_size - 1 : 0,
 				   res->width0, res->height0, res->depth0,
 				   desc, NULL);
 
 	si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
 				       0, 0, rtex->surface.blk_w, false, desc);
@@ -620,80 +619,80 @@ static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
 	/* Clear the base address and set the relative DCC offset. */
 	desc[0] = 0;
 	desc[1] &= C_008F14_BASE_ADDRESS_HI;
 	desc[7] = rtex->dcc_offset >> 8;
 
 	/* Dwords [2:9] contain the image descriptor. */
 	memcpy(&md->metadata[2], desc, sizeof(desc));
 	md->size_metadata = 10 * 4;
 
 	/* Dwords [10:..] contain the mipmap level offsets. */
-	if (rscreen->chip_class <= VI) {
+	if (sscreen->info.chip_class <= VI) {
 		for (i = 0; i <= res->last_level; i++)
 			md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
 
 		md->size_metadata += (1 + res->last_level) * 4;
 	}
 }
 
-static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
+static void si_apply_opaque_metadata(struct si_screen *sscreen,
 				     struct r600_texture *rtex,
 			             struct radeon_bo_metadata *md)
 {
 	uint32_t *desc = &md->metadata[2];
 
-	if (rscreen->chip_class < VI)
+	if (sscreen->info.chip_class < VI)
 		return;
 
 	/* Return if DCC is enabled. The texture should be set up with it
 	 * already.
 	 */
 	if (md->size_metadata >= 11 * 4 &&
 	    md->metadata[0] != 0 &&
-	    md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
+	    md->metadata[1] == si_get_bo_metadata_word1(sscreen) &&
 	    G_008F28_COMPRESSION_EN(desc[6])) {
 		rtex->dcc_offset = (uint64_t)desc[7] << 8;
 		return;
 	}
 
 	/* Disable DCC. These are always set by texture_from_handle and must
 	 * be cleared here.
 	 */
 	rtex->dcc_offset = 0;
 }
 
 static boolean r600_texture_get_handle(struct pipe_screen* screen,
 				       struct pipe_context *ctx,
 				       struct pipe_resource *resource,
 				       struct winsys_handle *whandle,
                                        unsigned usage)
 {
-	struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
+	struct si_screen *sscreen = (struct si_screen*)screen;
 	struct r600_common_context *rctx;
 	struct r600_resource *res = (struct r600_resource*)resource;
 	struct r600_texture *rtex = (struct r600_texture*)resource;
 	struct radeon_bo_metadata metadata;
 	bool update_metadata = false;
 	unsigned stride, offset, slice_size;
 
 	ctx = threaded_context_unwrap_sync(ctx);
-	rctx = (struct r600_common_context*)(ctx ? ctx : rscreen->aux_context);
+	rctx = (struct r600_common_context*)(ctx ? ctx : sscreen->aux_context);
 
 	if (resource->target != PIPE_BUFFER) {
 		/* This is not supported now, but it might be required for OpenCL
 		 * interop in the future.
 		 */
 		if (resource->nr_samples > 1 || rtex->is_depth)
 			return false;
 
 		/* Move a suballocated texture into a non-suballocated allocation. */
-		if (rscreen->ws->buffer_is_suballocated(res->buf) ||
+		if (sscreen->ws->buffer_is_suballocated(res->buf) ||
 		    rtex->surface.tile_swizzle ||
 		    (rtex->resource.flags & RADEON_FLAG_NO_INTERPROCESS_SHARING &&
 		     whandle->type != DRM_API_HANDLE_TYPE_KMS)) {
 			assert(!res->b.is_shared);
 			r600_reallocate_texture_inplace(rctx, rtex,
 							PIPE_BIND_SHARED, false);
 			rctx->b.flush(&rctx->b, NULL, 0);
 			assert(res->b.b.bind & PIPE_BIND_SHARED);
 			assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
 			assert(!(res->flags & RADEON_FLAG_NO_INTERPROCESS_SHARING));
@@ -711,45 +710,45 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
 
 		if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
 		    (rtex->cmask.size || rtex->dcc_offset)) {
 			/* Eliminate fast clear (both CMASK and DCC) */
 			r600_eliminate_fast_color_clear(rctx, rtex);
 
 			/* Disable CMASK if flush_resource isn't going
 			 * to be called.
 			 */
 			if (rtex->cmask.size)
-				r600_texture_discard_cmask(rscreen, rtex);
+				r600_texture_discard_cmask(sscreen, rtex);
 		}
 
 		/* Set metadata. */
 		if (!res->b.is_shared || update_metadata) {
-			r600_texture_init_metadata(rscreen, rtex, &metadata);
-			si_query_opaque_metadata(rscreen, rtex, &metadata);
+			r600_texture_init_metadata(sscreen, rtex, &metadata);
+			si_query_opaque_metadata(sscreen, rtex, &metadata);
 
-			rscreen->ws->buffer_set_metadata(res->buf, &metadata);
+			sscreen->ws->buffer_set_metadata(res->buf, &metadata);
 		}
 
-		if (rscreen->chip_class >= GFX9) {
+		if (sscreen->info.chip_class >= GFX9) {
 			offset = rtex->surface.u.gfx9.surf_offset;
 			stride = rtex->surface.u.gfx9.surf_pitch *
 				 rtex->surface.bpe;
 			slice_size = rtex->surface.u.gfx9.surf_slice_size;
 		} else {
 			offset = rtex->surface.u.legacy.level[0].offset;
 			stride = rtex->surface.u.legacy.level[0].nblk_x *
 				 rtex->surface.bpe;
 			slice_size = (uint64_t)rtex->surface.u.legacy.level[0].slice_size_dw * 4;
 		}
 	} else {
 		/* Move a suballocated buffer into a non-suballocated allocation. */
-		if (rscreen->ws->buffer_is_suballocated(res->buf)) {
+		if (sscreen->ws->buffer_is_suballocated(res->buf)) {
 			assert(!res->b.is_shared);
 
 			/* Allocate a new buffer with PIPE_BIND_SHARED. */
 			struct pipe_resource templ = res->b.b;
 			templ.bind |= PIPE_BIND_SHARED;
 
 			struct pipe_resource *newb =
 				screen->resource_create(screen, &templ);
 			if (!newb)
 				return false;
@@ -778,21 +777,21 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
 		 * doesn't set it.
 		 */
 		res->external_usage |= usage & ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
 		if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
 			res->external_usage &= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
 	} else {
 		res->b.is_shared = true;
 		res->external_usage = usage;
 	}
 
-	return rscreen->ws->buffer_get_handle(res->buf, stride, offset,
+	return sscreen->ws->buffer_get_handle(res->buf, stride, offset,
 					      slice_size, whandle);
 }
 
 static void r600_texture_destroy(struct pipe_screen *screen,
 				 struct pipe_resource *ptex)
 {
 	struct r600_texture *rtex = (struct r600_texture*)ptex;
 	struct r600_resource *resource = &rtex->resource;
 
 	r600_texture_reference(&rtex->flushed_depth_texture, NULL);
@@ -802,33 +801,33 @@ static void r600_texture_destroy(struct pipe_screen *screen,
 	}
 	pb_reference(&resource->buf, NULL);
 	r600_resource_reference(&rtex->dcc_separate_buffer, NULL);
 	r600_resource_reference(&rtex->last_dcc_separate_buffer, NULL);
 	FREE(rtex);
 }
 
 static const struct u_resource_vtbl r600_texture_vtbl;
 
 /* The number of samples can be specified independently of the texture. */
-void si_texture_get_fmask_info(struct r600_common_screen *rscreen,
+void si_texture_get_fmask_info(struct si_screen *sscreen,
 			       struct r600_texture *rtex,
 			       unsigned nr_samples,
 			       struct r600_fmask_info *out)
 {
 	/* FMASK is allocated like an ordinary texture. */
 	struct pipe_resource templ = rtex->resource.b.b;
 	struct radeon_surf fmask = {};
 	unsigned flags, bpe;
 
 	memset(out, 0, sizeof(*out));
 
-	if (rscreen->chip_class >= GFX9) {
+	if (sscreen->info.chip_class >= GFX9) {
 		out->alignment = rtex->surface.u.gfx9.fmask_alignment;
 		out->size = rtex->surface.u.gfx9.fmask_size;
 		return;
 	}
 
 	templ.nr_samples = 1;
 	flags = rtex->surface.flags | RADEON_SURF_FMASK;
 
 	switch (nr_samples) {
 	case 2:
@@ -836,59 +835,59 @@ void si_texture_get_fmask_info(struct r600_common_screen *rscreen,
 		bpe = 1;
 		break;
 	case 8:
 		bpe = 4;
 		break;
 	default:
 		R600_ERR("Invalid sample count for FMASK allocation.\n");
 		return;
 	}
 
-	if (rscreen->ws->surface_init(rscreen->ws, &templ, flags, bpe,
+	if (sscreen->ws->surface_init(sscreen->ws, &templ, flags, bpe,
 				      RADEON_SURF_MODE_2D, &fmask)) {
 		R600_ERR("Got error in surface_init while allocating FMASK.\n");
 		return;
 	}
 
 	assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
 
 	out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
 	if (out->slice_tile_max)
 		out->slice_tile_max -= 1;
 
 	out->tile_mode_index = fmask.u.legacy.tiling_index[0];
 	out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
 	out->bank_height = fmask.u.legacy.bankh;
 	out->tile_swizzle = fmask.tile_swizzle;
 	out->alignment = MAX2(256, fmask.surf_alignment);
 	out->size = fmask.surf_size;
 }
 
-static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
+static void r600_texture_allocate_fmask(struct si_screen *sscreen,
 					struct r600_texture *rtex)
 {
-	si_texture_get_fmask_info(rscreen, rtex,
+	si_texture_get_fmask_info(sscreen, rtex,
 				    rtex->resource.b.b.nr_samples, &rtex->fmask);
 
 	rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment);
 	rtex->size = rtex->fmask.offset + rtex->fmask.size;
 }
 
-void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
+void si_texture_get_cmask_info(struct si_screen *sscreen,
 			       struct r600_texture *rtex,
 			       struct r600_cmask_info *out)
 {
-	unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
-	unsigned num_pipes = rscreen->info.num_tile_pipes;
+	unsigned pipe_interleave_bytes = sscreen->info.pipe_interleave_bytes;
+	unsigned num_pipes = sscreen->info.num_tile_pipes;
 	unsigned cl_width, cl_height;
 
-	if (rscreen->chip_class >= GFX9) {
+	if (sscreen->info.chip_class >= GFX9) {
 		out->alignment = rtex->surface.u.gfx9.cmask_alignment;
 		out->size = rtex->surface.u.gfx9.cmask_size;
 		return;
 	}
 
 	switch (num_pipes) {
 	case 2:
 		cl_width = 32;
 		cl_height = 16;
 		break;
@@ -920,56 +919,56 @@ void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
 
 	out->slice_tile_max = (width * height) / (128*128);
 	if (out->slice_tile_max)
 		out->slice_tile_max -= 1;
 
 	out->alignment = MAX2(256, base_align);
 	out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
 		    align(slice_bytes, base_align);
 }
 
-static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
+static void r600_texture_allocate_cmask(struct si_screen *sscreen,
 					struct r600_texture *rtex)
 {
-	si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
+	si_texture_get_cmask_info(sscreen, rtex, &rtex->cmask);
 
 	rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
 	rtex->size = rtex->cmask.offset + rtex->cmask.size;
 
 	rtex->cb_color_info |= S_028C70_FAST_CLEAR(1);
 }
 
-static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
+static void r600_texture_get_htile_size(struct si_screen *sscreen,
 					struct r600_texture *rtex)
 {
 	unsigned cl_width, cl_height, width, height;
 	unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
-	unsigned num_pipes = rscreen->info.num_tile_pipes;
+	unsigned num_pipes = sscreen->info.num_tile_pipes;
 
-	assert(rscreen->chip_class <= VI);
+	assert(sscreen->info.chip_class <= VI);
 
 	rtex->surface.htile_size = 0;
 
 	/* HTILE is broken with 1D tiling on old kernels and CIK. */
-	if (rscreen->chip_class >= CIK &&
+	if (sscreen->info.chip_class >= CIK &&
 	    rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
-	    rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
+	    sscreen->info.drm_major == 2 && sscreen->info.drm_minor < 38)
 		return;
 
 	/* Overalign HTILE on P2 configs to work around GPU hangs in
 	 * piglit/depthstencil-render-miplevels 585.
 	 *
 	 * This has been confirmed to help Kabini & Stoney, where the hangs
 	 * are always reproducible. I think I have seen the test hang
 	 * on Carrizo too, though it was very rare there.
 	 */
-	if (rscreen->chip_class >= CIK && num_pipes < 4)
+	if (sscreen->info.chip_class >= CIK && num_pipes < 4)
 		num_pipes = 4;
 
 	switch (num_pipes) {
 	case 1:
 		cl_width = 32;
 		cl_height = 16;
 		break;
 	case 2:
 		cl_width = 32;
 		cl_height = 32;
@@ -990,59 +989,59 @@ static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
 		assert(0);
 		return;
 	}
 
 	width = align(rtex->resource.b.b.width0, cl_width * 8);
 	height = align(rtex->resource.b.b.height0, cl_height * 8);
 
 	slice_elements = (width * height) / (8 * 8);
 	slice_bytes = slice_elements * 4;
 
-	pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
+	pipe_interleave_bytes = sscreen->info.pipe_interleave_bytes;
 	base_align = num_pipes * pipe_interleave_bytes;
 
 	rtex->surface.htile_alignment = base_align;
 	rtex->surface.htile_size =
 		(util_max_layer(&rtex->resource.b.b, 0) + 1) *
 		align(slice_bytes, base_align);
 }
 
-static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
+static void r600_texture_allocate_htile(struct si_screen *sscreen,
 					struct r600_texture *rtex)
 {
-	if (rscreen->chip_class <= VI && !rtex->tc_compatible_htile)
-		r600_texture_get_htile_size(rscreen, rtex);
+	if (sscreen->info.chip_class <= VI && !rtex->tc_compatible_htile)
+		r600_texture_get_htile_size(sscreen, rtex);
 
 	if (!rtex->surface.htile_size)
 		return;
 
 	rtex->htile_offset = align(rtex->size, rtex->surface.htile_alignment);
 	rtex->size = rtex->htile_offset + rtex->surface.htile_size;
 }
 
-void si_print_texture_info(struct r600_common_screen *rscreen,
+void si_print_texture_info(struct si_screen *sscreen,
 			   struct r600_texture *rtex, struct u_log_context *log)
 {
 	int i;
 
 	/* Common parameters. */
 	u_log_printf(log, "  Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
 		"blk_h=%u, array_size=%u, last_level=%u, "
 		"bpe=%u, nsamples=%u, flags=0x%x, %s\n",
 		rtex->resource.b.b.width0, rtex->resource.b.b.height0,
 		rtex->resource.b.b.depth0, rtex->surface.blk_w,
 		rtex->surface.blk_h,
 		rtex->resource.b.b.array_size, rtex->resource.b.b.last_level,
 		rtex->surface.bpe, rtex->resource.b.b.nr_samples,
 		rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
 
-	if (rscreen->chip_class >= GFX9) {
+	if (sscreen->info.chip_class >= GFX9) {
 		u_log_printf(log, "  Surf: size=%"PRIu64", slice_size=%"PRIu64", "
 			"alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
 			rtex->surface.surf_size,
 			rtex->surface.u.gfx9.surf_slice_size,
 			rtex->surface.surf_alignment,
 			rtex->surface.u.gfx9.surf.swizzle_mode,
 			rtex->surface.u.gfx9.surf.epitch,
 			rtex->surface.u.gfx9.surf_pitch);
 
 		if (rtex->fmask.size) {
@@ -1169,21 +1168,21 @@ void si_print_texture_info(struct r600_common_screen *rscreen,
 
 /* Common processing for r600_texture_create and r600_texture_from_handle */
 static struct r600_texture *
 r600_texture_create_object(struct pipe_screen *screen,
 			   const struct pipe_resource *base,
 			   struct pb_buffer *buf,
 			   struct radeon_surf *surface)
 {
 	struct r600_texture *rtex;
 	struct r600_resource *resource;
-	struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
+	struct si_screen *sscreen = (struct si_screen*)screen;
 
 	rtex = CALLOC_STRUCT(r600_texture);
 	if (!rtex)
 		return NULL;
 
 	resource = &rtex->resource;
 	resource->b.b = *base;
 	resource->b.b.next = NULL;
 	resource->b.vtbl = &r600_texture_vtbl;
 	pipe_reference_init(&resource->b.b.reference, 1);
@@ -1196,21 +1195,21 @@ r600_texture_create_object(struct pipe_screen *screen,
 	rtex->size = rtex->surface.surf_size;
 
 	rtex->tc_compatible_htile = rtex->surface.htile_size != 0 &&
 				    (rtex->surface.flags &
 				     RADEON_SURF_TC_COMPATIBLE_HTILE);
 
 	/* TC-compatible HTILE:
 	 * - VI only supports Z32_FLOAT.
 	 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
 	if (rtex->tc_compatible_htile) {
-		if (rscreen->chip_class >= GFX9 &&
+		if (sscreen->info.chip_class >= GFX9 &&
 		    base->format == PIPE_FORMAT_Z16_UNORM)
 			rtex->db_render_format = base->format;
 		else {
 			rtex->db_render_format = PIPE_FORMAT_Z32_FLOAT;
 			rtex->upgraded_depth = base->format != PIPE_FORMAT_Z32_FLOAT &&
 					       base->format != PIPE_FORMAT_Z32_FLOAT_S8X24_UINT;
 		}
 	} else {
 		rtex->db_render_format = base->format;
 	}
@@ -1218,165 +1217,165 @@ r600_texture_create_object(struct pipe_screen *screen,
 	/* Applies to GCN. */
 	rtex->last_msaa_resolve_target_micro_mode = rtex->surface.micro_tile_mode;
 
 	/* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
 	 * between frames, so the only thing that can enable separate DCC
 	 * with DRI2 is multiple slow clears within a frame.
 	 */
 	rtex->ps_draw_ratio = 0;
 
 	if (rtex->is_depth) {
-		if (rscreen->chip_class >= GFX9) {
+		if (sscreen->info.chip_class >= GFX9) {
 			rtex->can_sample_z = true;
 			rtex->can_sample_s = true;
 		} else {
 			rtex->can_sample_z = !rtex->surface.u.legacy.depth_adjusted;
 			rtex->can_sample_s = !rtex->surface.u.legacy.stencil_adjusted;
 		}
 
 		if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
 				     R600_RESOURCE_FLAG_FLUSHED_DEPTH))) {
 			rtex->db_compatible = true;
 
-			if (!(rscreen->debug_flags & DBG(NO_HYPERZ)))
-				r600_texture_allocate_htile(rscreen, rtex);
+			if (!(sscreen->debug_flags & DBG(NO_HYPERZ)))
+				r600_texture_allocate_htile(sscreen, rtex);
 		}
 	} else {
 		if (base->nr_samples > 1) {
 			if (!buf) {
-				r600_texture_allocate_fmask(rscreen, rtex);
-				r600_texture_allocate_cmask(rscreen, rtex);
+				r600_texture_allocate_fmask(sscreen, rtex);
+				r600_texture_allocate_cmask(sscreen, rtex);
 				rtex->cmask_buffer = &rtex->resource;
 			}
 			if (!rtex->fmask.size || !rtex->cmask.size) {
 				FREE(rtex);
 				return NULL;
 			}
 		}
 
 		/* Shared textures must always set up DCC here.
 		 * If it's not present, it will be disabled by
 		 * apply_opaque_metadata later.
 		 */
 		if (rtex->surface.dcc_size &&
-		    (buf || !(rscreen->debug_flags & DBG(NO_DCC))) &&
+		    (buf || !(sscreen->debug_flags & DBG(NO_DCC))) &&
 		    !(rtex->surface.flags & RADEON_SURF_SCANOUT)) {
 			/* Reserve space for the DCC buffer. */
 			rtex->dcc_offset = align64(rtex->size, rtex->surface.dcc_alignment);
 			rtex->size = rtex->dcc_offset + rtex->surface.dcc_size;
 		}
 	}
 
 	/* Now create the backing buffer. */
 	if (!buf) {
-		si_init_resource_fields(rscreen, resource, rtex->size,
+		si_init_resource_fields(sscreen, resource, rtex->size,
 					  rtex->surface.surf_alignment);
 
-		if (!si_alloc_resource(rscreen, resource)) {
+		if (!si_alloc_resource(sscreen, resource)) {
 			FREE(rtex);
 			return NULL;
 		}
 	} else {
 		resource->buf = buf;
-		resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
+		resource->gpu_address = sscreen->ws->buffer_get_virtual_address(resource->buf);
 		resource->bo_size = buf->size;
 		resource->bo_alignment = buf->alignment;
-		resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
+		resource->domains = sscreen->ws->buffer_get_initial_domain(resource->buf);
 		if (resource->domains & RADEON_DOMAIN_VRAM)
 			resource->vram_usage = buf->size;
 		else if (resource->domains & RADEON_DOMAIN_GTT)
 			resource->gart_usage = buf->size;
 	}
 
 	if (rtex->cmask.size) {
 		/* Initialize the cmask to 0xCC (= compressed state). */
-		si_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
+		si_screen_clear_buffer(sscreen, &rtex->cmask_buffer->b.b,
 					 rtex->cmask.offset, rtex->cmask.size,
 					 0xCCCCCCCC);
 	}
 	if (rtex->htile_offset) {
 		uint32_t clear_value = 0;
 
-		if (rscreen->chip_class >= GFX9 || rtex->tc_compatible_htile)
+		if (sscreen->info.chip_class >= GFX9 || rtex->tc_compatible_htile)
 			clear_value = 0x0000030F;
 
-		si_screen_clear_buffer(rscreen, &rtex->resource.b.b,
+		si_screen_clear_buffer(sscreen, &rtex->resource.b.b,
 					 rtex->htile_offset,
 					 rtex->surface.htile_size,
 					 clear_value);
 	}
 
 	/* Initialize DCC only if the texture is not being imported. */
 	if (!buf && rtex->dcc_offset) {
-		si_screen_clear_buffer(rscreen, &rtex->resource.b.b,
+		si_screen_clear_buffer(sscreen, &rtex->resource.b.b,
 					 rtex->dcc_offset,
 					 rtex->surface.dcc_size,
 					 0xFFFFFFFF);
 	}
 
 	/* Initialize the CMASK base register value. */
 	rtex->cmask.base_address_reg =
 		(rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
 
-	if (rscreen->debug_flags & DBG(VM)) {
+	if (sscreen->debug_flags & DBG(VM)) {
 		fprintf(stderr, "VM start=0x%"PRIX64"  end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
 			rtex->resource.gpu_address,
 			rtex->resource.gpu_address + rtex->resource.buf->size,
 			base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
 			base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
 	}
 
-	if (rscreen->debug_flags & DBG(TEX)) {
+	if (sscreen->debug_flags & DBG(TEX)) {
 		puts("Texture:");
 		struct u_log_context log;
 		u_log_context_init(&log);
-		si_print_texture_info(rscreen, rtex, &log);
+		si_print_texture_info(sscreen, rtex, &log);
 		u_log_new_page_print(&log, stdout);
 		fflush(stdout);
 		u_log_context_destroy(&log);
 	}
 
 	return rtex;
 }
 
 static enum radeon_surf_mode
-r600_choose_tiling(struct r600_common_screen *rscreen,
+r600_choose_tiling(struct si_screen *sscreen,
 		   const struct pipe_resource *templ)
 {
 	const struct util_format_description *desc = util_format_description(templ->format);
 	bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
 	bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) &&
 				!(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
 
 	/* MSAA resources must be 2D tiled. */
 	if (templ->nr_samples > 1)
 		return RADEON_SURF_MODE_2D;
 
 	/* Transfer resources should be linear. */
 	if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
 		return RADEON_SURF_MODE_LINEAR_ALIGNED;
 
 	/* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
 	 * which requires 2D tiling.
 	 */
-	if (rscreen->chip_class == VI &&
+	if (sscreen->info.chip_class == VI &&
 	    is_depth_stencil &&
 	    (templ->flags & PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY))
 		return RADEON_SURF_MODE_2D;
 
 	/* Handle common candidates for the linear mode.
 	 * Compressed textures and DB surfaces must always be tiled.
 	 */
 	if (!force_tiling &&
 	    !is_depth_stencil &&
 	    !util_format_is_compressed(templ->format)) {
-		if (rscreen->debug_flags & DBG(NO_TILING))
+		if (sscreen->debug_flags & DBG(NO_TILING))
 			return RADEON_SURF_MODE_LINEAR_ALIGNED;
 
 		/* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
 		if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
 			return RADEON_SURF_MODE_LINEAR_ALIGNED;
 
 		/* Cursors are linear on SI.
 		 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
 		if (templ->bind & PIPE_BIND_CURSOR)
 			return RADEON_SURF_MODE_LINEAR_ALIGNED;
@@ -1393,97 +1392,97 @@ r600_choose_tiling(struct r600_common_screen *rscreen,
 			return RADEON_SURF_MODE_LINEAR_ALIGNED;
 
 		/* Textures likely to be mapped often. */
 		if (templ->usage == PIPE_USAGE_STAGING ||
 		    templ->usage == PIPE_USAGE_STREAM)
 			return RADEON_SURF_MODE_LINEAR_ALIGNED;
 	}
 
 	/* Make small textures 1D tiled. */
 	if (templ->width0 <= 16 || templ->height0 <= 16 ||
-	    (rscreen->debug_flags & DBG(NO_2D_TILING)))
+	    (sscreen->debug_flags & DBG(NO_2D_TILING)))
 		return RADEON_SURF_MODE_1D;
 
 	/* The allocator will switch to 1D if needed. */
 	return RADEON_SURF_MODE_2D;
 }
 
 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
 					const struct pipe_resource *templ)
 {
-	struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
+	struct si_screen *sscreen = (struct si_screen*)screen;
 	struct radeon_surf surface = {0};
 	bool is_flushed_depth = templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH;
 	bool tc_compatible_htile =
-		rscreen->chip_class >= VI &&
+		sscreen->info.chip_class >= VI &&
 		(templ->flags & PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY) &&
-		!(rscreen->debug_flags & DBG(NO_HYPERZ)) &&
+		!(sscreen->debug_flags & DBG(NO_HYPERZ)) &&
 		!is_flushed_depth &&
 		templ->nr_samples <= 1 && /* TC-compat HTILE is less efficient with MSAA */
 		util_format_is_depth_or_stencil(templ->format);
 
 	int r;
 
-	r = r600_init_surface(rscreen, &surface, templ,
-			      r600_choose_tiling(rscreen, templ), 0, 0,
+	r = r600_init_surface(sscreen, &surface, templ,
+			      r600_choose_tiling(sscreen, templ), 0, 0,
 			      false, false, is_flushed_depth,
 			      tc_compatible_htile);
 	if (r) {
 		return NULL;
 	}
 
 	return (struct pipe_resource *)
 	       r600_texture_create_object(screen, templ, NULL, &surface);
 }
 
 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 						      const struct pipe_resource *templ,
 						      struct winsys_handle *whandle,
                                                       unsigned usage)
 {
-	struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
+	struct si_screen *sscreen = (struct si_screen*)screen;
 	struct pb_buffer *buf = NULL;
 	unsigned stride = 0, offset = 0;
 	enum radeon_surf_mode array_mode;
 	struct radeon_surf surface = {};
 	int r;
 	struct radeon_bo_metadata metadata = {};
 	struct r600_texture *rtex;
 	bool is_scanout;
 
 	/* Support only 2D textures without mipmaps */
 	if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 	      templ->depth0 != 1 || templ->last_level != 0)
 		return NULL;
 
-	buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride, &offset);
+	buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle, &stride, &offset);
 	if (!buf)
 		return NULL;
 
-	rscreen->ws->buffer_get_metadata(buf, &metadata);
-	r600_surface_import_metadata(rscreen, &surface, &metadata,
+	sscreen->ws->buffer_get_metadata(buf, &metadata);
+	r600_surface_import_metadata(sscreen, &surface, &metadata,
 				     &array_mode, &is_scanout);
 
-	r = r600_init_surface(rscreen, &surface, templ, array_mode, stride,
+	r = r600_init_surface(sscreen, &surface, templ, array_mode, stride,
 			      offset, true, is_scanout, false, false);
 	if (r) {
 		return NULL;
 	}
 
 	rtex = r600_texture_create_object(screen, templ, buf, &surface);
 	if (!rtex)
 		return NULL;
 
 	rtex->resource.b.is_shared = true;
 	rtex->resource.external_usage = usage;
 
-	si_apply_opaque_metadata(rscreen, rtex, &metadata);
+	si_apply_opaque_metadata(sscreen, rtex, &metadata);
 
 	assert(rtex->surface.tile_swizzle == 0);
 	return &rtex->resource.b.b;
 }
 
 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
 				   struct pipe_resource *texture,
 				   struct r600_texture **staging)
 {
 	struct r600_texture *rtex = (struct r600_texture*)texture;
@@ -1570,51 +1569,51 @@ static void r600_init_temp_resource_from_box(struct pipe_resource *res,
 
 	/* We must set the correct texture target and dimensions for a 3D box. */
 	if (box->depth > 1 && util_max_layer(orig, level) > 0) {
 		res->target = PIPE_TEXTURE_2D_ARRAY;
 		res->array_size = box->depth;
 	} else {
 		res->target = PIPE_TEXTURE_2D;
 	}
 }
 
-static bool r600_can_invalidate_texture(struct r600_common_screen *rscreen,
+static bool r600_can_invalidate_texture(struct si_screen *sscreen,
 					struct r600_texture *rtex,
 					unsigned transfer_usage,
 					const struct pipe_box *box)
 {
 	return !rtex->resource.b.is_shared &&
 		!(transfer_usage & PIPE_TRANSFER_READ) &&
 		rtex->resource.b.b.last_level == 0 &&
 		util_texrange_covers_whole_level(&rtex->resource.b.b, 0,
 						 box->x, box->y, box->z,
 						 box->width, box->height,
 						 box->depth);
 }
 
 static void r600_texture_invalidate_storage(struct r600_common_context *rctx,
 					    struct r600_texture *rtex)
 {
-	struct r600_common_screen *rscreen = rctx->screen;
+	struct si_screen *sscreen = rctx->screen;
 
 	/* There is no point in discarding depth and tiled buffers. */
 	assert(!rtex->is_depth);
 	assert(rtex->surface.is_linear);
 
 	/* Reallocate the buffer in the same pipe_resource. */
-	si_alloc_resource(rscreen, &rtex->resource);
+	si_alloc_resource(sscreen, &rtex->resource);
 
 	/* Initialize the CMASK base address (needed even without CMASK). */
 	rtex->cmask.base_address_reg =
 		(rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
 
-	p_atomic_inc(&rscreen->dirty_tex_counter);
+	p_atomic_inc(&sscreen->dirty_tex_counter);
 
 	rctx->num_alloc_tex_transfer_bytes += rtex->size;
 }
 
 static void *r600_texture_transfer_map(struct pipe_context *ctx,
 				       struct pipe_resource *texture,
 				       unsigned level,
 				       unsigned usage,
 				       const struct pipe_box *box,
 				       struct pipe_transfer **ptransfer)
@@ -2333,29 +2332,29 @@ void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
 		 * decompression that re-sets framebuffer state
 		 */
 	}
 }
 
 static struct pipe_memory_object *
 r600_memobj_from_handle(struct pipe_screen *screen,
 			struct winsys_handle *whandle,
 			bool dedicated)
 {
-	struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
+	struct si_screen *sscreen = (struct si_screen*)screen;
 	struct r600_memory_object *memobj = CALLOC_STRUCT(r600_memory_object);
 	struct pb_buffer *buf = NULL;
 	uint32_t stride, offset;
 
 	if (!memobj)
 		return NULL;
 
-	buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
+	buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle,
 					      &stride, &offset);
 	if (!buf) {
 		free(memobj);
 		return NULL;
 	}
 
 	memobj->b.dedicated = dedicated;
 	memobj->buf = buf;
 	memobj->stride = stride;
 	memobj->offset = offset;
@@ -2374,32 +2373,32 @@ r600_memobj_destroy(struct pipe_screen *screen,
 	free(memobj);
 }
 
 static struct pipe_resource *
 r600_texture_from_memobj(struct pipe_screen *screen,
 			 const struct pipe_resource *templ,
 			 struct pipe_memory_object *_memobj,
 			 uint64_t offset)
 {
 	int r;
-	struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
+	struct si_screen *sscreen = (struct si_screen*)screen;
 	struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
 	struct r600_texture *rtex;
 	struct radeon_surf surface = {};
 	struct radeon_bo_metadata metadata = {};
 	enum radeon_surf_mode array_mode;
 	bool is_scanout;
 	struct pb_buffer *buf = NULL;
 
 	if (memobj->b.dedicated) {
-		rscreen->ws->buffer_get_metadata(memobj->buf, &metadata);
-		r600_surface_import_metadata(rscreen, &surface, &metadata,
+		sscreen->ws->buffer_get_metadata(memobj->buf, &metadata);
+		r600_surface_import_metadata(sscreen, &surface, &metadata,
 				     &array_mode, &is_scanout);
 	} else {
 		/**
 		 * The bo metadata is unset for un-dedicated images. So we fall
 		 * back to linear. See answer to question 5 of the
 		 * VK_KHX_external_memory spec for some details.
 		 *
 		 * It is possible that this case isn't going to work if the
 		 * surface pitch isn't correctly aligned by default.
 		 *
@@ -2415,40 +2414,40 @@ r600_texture_from_memobj(struct pipe_screen *screen,
 		 *
 		 * A possible alternative is to attempt to reconstruct the
 		 * tiling information when the TexParameter TEXTURE_TILING_EXT
 		 * is set.
 		 */
 		array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
 		is_scanout = false;
 
 	}
 
-	r = r600_init_surface(rscreen, &surface, templ,
+	r = r600_init_surface(sscreen, &surface, templ,
 			      array_mode, memobj->stride,
 			      offset, true, is_scanout,
 			      false, false);
 	if (r)
 		return NULL;
 
 	rtex = r600_texture_create_object(screen, templ, memobj->buf, &surface);
 	if (!rtex)
 		return NULL;
 
 	/* r600_texture_create_object doesn't increment refcount of
 	 * memobj->buf, so increment it here.
 	 */
 	pb_reference(&buf, memobj->buf);
 
 	rtex->resource.b.is_shared = true;
 	rtex->resource.external_usage = PIPE_HANDLE_USAGE_READ_WRITE;
 
-	si_apply_opaque_metadata(rscreen, rtex, &metadata);
+	si_apply_opaque_metadata(sscreen, rtex, &metadata);
 
 	return &rtex->resource.b.b;
 }
 
 static bool si_check_resource_capability(struct pipe_screen *screen,
 					 struct pipe_resource *resource,
 					 unsigned bind)
 {
 	struct r600_texture *tex = (struct r600_texture*)resource;
 
@@ -2459,25 +2458,25 @@ static bool si_check_resource_capability(struct pipe_screen *screen,
 	if (bind & PIPE_BIND_LINEAR && !tex->surface.is_linear)
 		return false;
 
 	if (bind & PIPE_BIND_SCANOUT && !tex->surface.is_displayable)
 		return false;
 
 	/* TODO: PIPE_BIND_CURSOR - do we care? */
 	return true;
 }
 
-void si_init_screen_texture_functions(struct r600_common_screen *rscreen)
+void si_init_screen_texture_functions(struct si_screen *sscreen)
 {
-	rscreen->b.resource_from_handle = r600_texture_from_handle;
-	rscreen->b.resource_get_handle = r600_texture_get_handle;
-	rscreen->b.resource_from_memobj = r600_texture_from_memobj;
-	rscreen->b.memobj_create_from_handle = r600_memobj_from_handle;
-	rscreen->b.memobj_destroy = r600_memobj_destroy;
-	rscreen->b.check_resource_capability = si_check_resource_capability;
+	sscreen->b.resource_from_handle = r600_texture_from_handle;
+	sscreen->b.resource_get_handle = r600_texture_get_handle;
+	sscreen->b.resource_from_memobj = r600_texture_from_memobj;
+	sscreen->b.memobj_create_from_handle = r600_memobj_from_handle;
+	sscreen->b.memobj_destroy = r600_memobj_destroy;
+	sscreen->b.check_resource_capability = si_check_resource_capability;
 }
 
 void si_init_context_texture_functions(struct r600_common_context *rctx)
 {
 	rctx->b.create_surface = r600_create_surface;
 	rctx->b.surface_destroy = r600_surface_destroy;
 }
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c
index cd58c66..afa8836 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -32,21 +32,21 @@
 #include <stdio.h>
 
 #include "pipe/p_video_codec.h"
 
 #include "util/u_memory.h"
 #include "util/u_video.h"
 
 #include "vl/vl_defines.h"
 #include "vl/vl_mpeg12_decoder.h"
 
-#include "r600_pipe_common.h"
+#include "radeonsi/si_pipe.h"
 #include "radeon_video.h"
 #include "radeon_uvd.h"
 
 #define NUM_BUFFERS 4
 
 #define NUM_MPEG2_REFS 6
 #define NUM_H264_REFS 17
 #define NUM_VC1_REFS 5
 
 #define FB_BUFFER_OFFSET 0x1000
@@ -322,21 +322,21 @@ static unsigned calc_ctx_size_h265_main10(struct ruvd_decoder *dec, struct pipe_
 	max_mb_address = (unsigned) ceil(height * 8 / 2048.0);
 
 	cm_buffer_size = max_references * context_buffer_size_per_ctb_row * height_in_ctb;
 	db_left_tile_pxl_size = coeff_10bit * (max_mb_address * 2 * 2048 + 1024);
 
 	return cm_buffer_size + db_left_tile_ctx_size + db_left_tile_pxl_size;
 }
 
 static unsigned get_db_pitch_alignment(struct ruvd_decoder *dec)
 {
-	if (((struct r600_common_screen*)dec->screen)->family < CHIP_VEGA10)
+	if (((struct si_screen*)dec->screen)->info.family < CHIP_VEGA10)
 		return 16;
 	else
 		return 32;
 }
 
 /* calculate size of reference picture buffer */
 static unsigned calc_dpb_size(struct ruvd_decoder *dec)
 {
 	unsigned width_in_mb, height_in_mb, image_size, dpb_size;
 
@@ -387,31 +387,31 @@ static unsigned calc_dpb_size(struct ruvd_decoder *dec)
 				num_dpb_buffer = 184320 / fs_in_mb;
 				break;
 			default:
 				num_dpb_buffer = 184320 / fs_in_mb;
 				break;
 			}
 			num_dpb_buffer++;
 			max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
 			dpb_size = image_size * max_references;
 			if ((dec->stream_type != RUVD_CODEC_H264_PERF) ||
-			    (((struct r600_common_screen*)dec->screen)->family < CHIP_POLARIS10)) {
+			    (((struct si_screen*)dec->screen)->info.family < CHIP_POLARIS10)) {
 				dpb_size += max_references * align(width_in_mb * height_in_mb  * 192, alignment);
 				dpb_size += align(width_in_mb * height_in_mb * 32, alignment);
 			}
 		} else {
 			// the firmware seems to allways assume a minimum of ref frames
 			max_references = MAX2(NUM_H264_REFS, max_references);
 			// reference picture buffer
 			dpb_size = image_size * max_references;
 			if ((dec->stream_type != RUVD_CODEC_H264_PERF) ||
-			    (((struct r600_common_screen*)dec->screen)->family < CHIP_POLARIS10)) {
+			    (((struct si_screen*)dec->screen)->info.family < CHIP_POLARIS10)) {
 				// macroblock context buffer
 				dpb_size += width_in_mb * height_in_mb * max_references * 192;
 				// IT surface buffer
 				dpb_size += width_in_mb * height_in_mb * 32;
 			}
 		}
 		break;
 	}
 
 	case PIPE_VIDEO_FORMAT_HEVC:
@@ -597,21 +597,21 @@ static struct ruvd_h265 get_h265_msg(struct ruvd_decoder *dec, struct pipe_video
 	result.sps_info_flags = 0;
 	result.sps_info_flags |= pic->pps->sps->scaling_list_enabled_flag << 0;
 	result.sps_info_flags |= pic->pps->sps->amp_enabled_flag << 1;
 	result.sps_info_flags |= pic->pps->sps->sample_adaptive_offset_enabled_flag << 2;
 	result.sps_info_flags |= pic->pps->sps->pcm_enabled_flag << 3;
 	result.sps_info_flags |= pic->pps->sps->pcm_loop_filter_disabled_flag << 4;
 	result.sps_info_flags |= pic->pps->sps->long_term_ref_pics_present_flag << 5;
 	result.sps_info_flags |= pic->pps->sps->sps_temporal_mvp_enabled_flag << 6;
 	result.sps_info_flags |= pic->pps->sps->strong_intra_smoothing_enabled_flag << 7;
 	result.sps_info_flags |= pic->pps->sps->separate_colour_plane_flag << 8;
-	if (((struct r600_common_screen*)dec->screen)->family == CHIP_CARRIZO)
+	if (((struct si_screen*)dec->screen)->info.family == CHIP_CARRIZO)
 		result.sps_info_flags |= 1 << 9;
 	if (pic->UseRefPicList == true)
 		result.sps_info_flags |= 1 << 10;
 
 	result.chroma_format = pic->pps->sps->chroma_format_idc;
 	result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
 	result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
 	result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
 	result.sps_max_dec_pic_buffering_minus1 = pic->pps->sps->sps_max_dec_pic_buffering_minus1;
 	result.log2_min_luma_coding_block_size_minus3 = pic->pps->sps->log2_min_luma_coding_block_size_minus3;
@@ -1238,25 +1238,25 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder,
 		dec->msg->body.decode.width_in_samples = align(dec->msg->body.decode.width_in_samples, 16) / 16;
 		dec->msg->body.decode.height_in_samples = align(dec->msg->body.decode.height_in_samples, 16) / 16;
 	}
 
 	if (dec->dpb.res)
 		dec->msg->body.decode.dpb_size = dec->dpb.res->buf->size;
 	dec->msg->body.decode.bsd_size = bs_size;
 	dec->msg->body.decode.db_pitch = align(dec->base.width, get_db_pitch_alignment(dec));
 
 	if (dec->stream_type == RUVD_CODEC_H264_PERF &&
-	    ((struct r600_common_screen*)dec->screen)->family >= CHIP_POLARIS10)
+	    ((struct si_screen*)dec->screen)->info.family >= CHIP_POLARIS10)
 		dec->msg->body.decode.dpb_reserved = dec->ctx.res->buf->size;
 
 	dt = dec->set_dtb(dec->msg, (struct vl_video_buffer *)target);
-	if (((struct r600_common_screen*)dec->screen)->family >= CHIP_STONEY)
+	if (((struct si_screen*)dec->screen)->info.family >= CHIP_STONEY)
 		dec->msg->body.decode.dt_wa_chroma_top_offset = dec->msg->body.decode.dt_pitch / 2;
 
 	switch (u_reduce_video_profile(picture->profile)) {
 	case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 		dec->msg->body.decode.codec.h264 = get_h264_msg(dec, (struct pipe_h264_picture_desc*)picture);
 		break;
 
 	case PIPE_VIDEO_FORMAT_HEVC:
 		dec->msg->body.decode.codec.h265 = get_h265_msg(dec, target, (struct pipe_h265_picture_desc*)picture);
 		if (dec->ctx.res == NULL) {
diff --git a/src/gallium/drivers/radeon/radeon_vce.c b/src/gallium/drivers/radeon/radeon_vce.c
index c7e6333..7594421 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -27,21 +27,21 @@
 
 #include <stdio.h>
 
 #include "pipe/p_video_codec.h"
 
 #include "util/u_video.h"
 #include "util/u_memory.h"
 
 #include "vl/vl_video_buffer.h"
 
-#include "r600_pipe_common.h"
+#include "radeonsi/si_pipe.h"
 #include "radeon_video.h"
 #include "radeon_vce.h"
 
 #define FW_40_2_2 ((40 << 24) | (2 << 16) | (2 << 8))
 #define FW_50_0_1 ((50 << 24) | (0 << 16) | (1 << 8))
 #define FW_50_1_2 ((50 << 24) | (1 << 16) | (2 << 8))
 #define FW_50_10_2 ((50 << 24) | (10 << 16) | (2 << 8))
 #define FW_50_17_3 ((50 << 24) | (17 << 16) | (3 << 8))
 #define FW_52_0_3 ((52 << 24) | (0 << 16) | (3 << 8))
 #define FW_52_4_3 ((52 << 24) | (4 << 16) | (3 << 8))
@@ -212,24 +212,24 @@ struct rvce_cpb_slot *si_l1_slot(struct rvce_encoder *enc)
 {
 	return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next->next, list);
 }
 
 /**
  * Calculate the offsets into the CPB
  */
 void si_vce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
 			 signed *luma_offset, signed *chroma_offset)
 {
-	struct r600_common_screen *rscreen = (struct r600_common_screen *)enc->screen;
+	struct si_screen *sscreen = (struct si_screen *)enc->screen;
 	unsigned pitch, vpitch, fsize;
 
-	if (rscreen->chip_class < GFX9) {
+	if (sscreen->info.chip_class < GFX9) {
 		pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe, 128);
 		vpitch = align(enc->luma->u.legacy.level[0].nblk_y, 16);
 	} else {
 		pitch = align(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe, 256);
 		vpitch = align(enc->luma->u.gfx9.surf_height, 16);
 	}
 	fsize = pitch * (vpitch + vpitch / 2);
 
 	*luma_offset = slot->index * fsize;
 	*chroma_offset = *luma_offset + pitch * vpitch;
@@ -382,54 +382,54 @@ static void rvce_cs_flush(void *ctx, unsigned flags,
 			  struct pipe_fence_handle **fence)
 {
 	// just ignored
 }
 
 struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context,
 					       const struct pipe_video_codec *templ,
 					       struct radeon_winsys* ws,
 					       rvce_get_buffer get_buffer)
 {
-	struct r600_common_screen *rscreen = (struct r600_common_screen *)context->screen;
+	struct si_screen *sscreen = (struct si_screen *)context->screen;
 	struct r600_common_context *rctx = (struct r600_common_context*)context;
 	struct rvce_encoder *enc;
 	struct pipe_video_buffer *tmp_buf, templat = {};
 	struct radeon_surf *tmp_surf;
 	unsigned cpb_size;
 
-	if (!rscreen->info.vce_fw_version) {
+	if (!sscreen->info.vce_fw_version) {
 		RVID_ERR("Kernel doesn't supports VCE!\n");
 		return NULL;
 
-	} else if (!si_vce_is_fw_version_supported(rscreen)) {
+	} else if (!si_vce_is_fw_version_supported(sscreen)) {
 		RVID_ERR("Unsupported VCE fw version loaded!\n");
 		return NULL;
 	}
 
 	enc = CALLOC_STRUCT(rvce_encoder);
 	if (!enc)
 		return NULL;
 
-	if (rscreen->info.drm_major == 3)
+	if (sscreen->info.drm_major == 3)
 		enc->use_vm = true;
-	if ((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42) ||
-            rscreen->info.drm_major == 3)
+	if ((sscreen->info.drm_major == 2 && sscreen->info.drm_minor >= 42) ||
+            sscreen->info.drm_major == 3)
 		enc->use_vui = true;
-	if (rscreen->info.family >= CHIP_TONGA &&
-	    rscreen->info.family != CHIP_STONEY &&
-	    rscreen->info.family != CHIP_POLARIS11 &&
-	    rscreen->info.family != CHIP_POLARIS12)
+	if (sscreen->info.family >= CHIP_TONGA &&
+	    sscreen->info.family != CHIP_STONEY &&
+	    sscreen->info.family != CHIP_POLARIS11 &&
+	    sscreen->info.family != CHIP_POLARIS12)
 		enc->dual_pipe = true;
 	/* TODO enable B frame with dual instance */
-	if ((rscreen->info.family >= CHIP_TONGA) &&
+	if ((sscreen->info.family >= CHIP_TONGA) &&
 		(templ->max_references == 1) &&
-		(rscreen->info.vce_harvest_config == 0))
+		(sscreen->info.vce_harvest_config == 0))
 		enc->dual_inst = true;
 
 	enc->base = *templ;
 	enc->base.context = context;
 
 	enc->base.destroy = rvce_destroy;
 	enc->base.begin_frame = rvce_begin_frame;
 	enc->base.encode_bitstream = rvce_encode_bitstream;
 	enc->base.end_frame = rvce_end_frame;
 	enc->base.flush = rvce_flush;
@@ -453,21 +453,21 @@ struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context,
 		RVID_ERR("Can't create video buffer.\n");
 		goto error;
 	}
 
 	enc->cpb_num = get_cpb_num(enc);
 	if (!enc->cpb_num)
 		goto error;
 
 	get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
 
-	cpb_size = (rscreen->chip_class < GFX9) ?
+	cpb_size = (sscreen->info.chip_class < GFX9) ?
 		align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
 		align(tmp_surf->u.legacy.level[0].nblk_y, 32) :
 
 		align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
 		align(tmp_surf->u.gfx9.surf_height, 32);
 
 	cpb_size = cpb_size * 3 / 2;
 	cpb_size = cpb_size * enc->cpb_num;
 	if (enc->dual_pipe)
 		cpb_size +=  RVCE_MAX_AUX_BUFFER_NUM *
@@ -477,21 +477,21 @@ struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context,
 		RVID_ERR("Can't create CPB buffer.\n");
 		goto error;
 	}
 
 	enc->cpb_array = CALLOC(enc->cpb_num, sizeof(struct rvce_cpb_slot));
 	if (!enc->cpb_array)
 		goto error;
 
 	reset_cpb(enc);
 
-	switch (rscreen->info.vce_fw_version) {
+	switch (sscreen->info.vce_fw_version) {
 	case FW_40_2_2:
 		si_vce_40_2_2_init(enc);
 		si_get_pic_param = si_vce_40_2_2_get_param;
 		break;
 
 	case FW_50_0_1:
 	case FW_50_1_2:
 	case FW_50_10_2:
 	case FW_50_17_3:
 		si_vce_50_init(enc);
@@ -499,21 +499,21 @@ struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context,
 		break;
 
 	case FW_52_0_3:
 	case FW_52_4_3:
 	case FW_52_8_3:
 		si_vce_52_init(enc);
 		si_get_pic_param = si_vce_52_get_param;
 		break;
 
 	default:
-		if ((rscreen->info.vce_fw_version & (0xff << 24)) == FW_53) {
+		if ((sscreen->info.vce_fw_version & (0xff << 24)) == FW_53) {
 			si_vce_52_init(enc);
 			si_get_pic_param = si_vce_52_get_param;
 		} else
 			goto error;
 	}
 
 	return &enc->base;
 
 error:
 	if (enc->cs)
@@ -522,34 +522,34 @@ error:
 	si_vid_destroy_buffer(&enc->cpb);
 
 	FREE(enc->cpb_array);
 	FREE(enc);
 	return NULL;
 }
 
 /**
  * check if kernel has the right fw version loaded
  */
-bool si_vce_is_fw_version_supported(struct r600_common_screen *rscreen)
+bool si_vce_is_fw_version_supported(struct si_screen *sscreen)
 {
-	switch (rscreen->info.vce_fw_version) {
+	switch (sscreen->info.vce_fw_version) {
 	case FW_40_2_2:
 	case FW_50_0_1:
 	case FW_50_1_2:
 	case FW_50_10_2:
 	case FW_50_17_3:
 	case FW_52_0_3:
 	case FW_52_4_3:
 	case FW_52_8_3:
 		return true;
 	default:
-		if ((rscreen->info.vce_fw_version & (0xff << 24)) == FW_53)
+		if ((sscreen->info.vce_fw_version & (0xff << 24)) == FW_53)
 			return true;
 		else
 			return false;
 	}
 }
 
 /**
  * Add the buffer as relocation to the current command submission
  */
 void si_vce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf,
diff --git a/src/gallium/drivers/radeon/radeon_vce.h b/src/gallium/drivers/radeon/radeon_vce.h
index f7ce583..7f30877 100644
--- a/src/gallium/drivers/radeon/radeon_vce.h
+++ b/src/gallium/drivers/radeon/radeon_vce.h
@@ -35,21 +35,21 @@
 	uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
 	RVCE_CS(cmd)
 #define RVCE_READ(buf, domain, off) si_vce_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
 #define RVCE_WRITE(buf, domain, off) si_vce_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
 #define RVCE_READWRITE(buf, domain, off) si_vce_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
 #define RVCE_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; }
 
 #define RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE (4096 * 16 * 2.5)
 #define RVCE_MAX_AUX_BUFFER_NUM 4
 
-struct r600_common_screen;
+struct si_screen;
 
 /* driver dependent callback */
 typedef void (*rvce_get_buffer)(struct pipe_resource *resource,
 				struct pb_buffer **handle,
 				struct radeon_surf **surface);
 
 /* Coded picture buffer slot */
 struct rvce_cpb_slot {
 	struct list_head		list;
 
@@ -415,21 +415,21 @@ struct rvce_cpb_slot *si_current_slot(struct rvce_encoder *enc);
 struct rvce_cpb_slot *si_l0_slot(struct rvce_encoder *enc);
 struct rvce_cpb_slot *si_l1_slot(struct rvce_encoder *enc);
 void si_vce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
 			 signed *luma_offset, signed *chroma_offset);
 
 struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context,
 					       const struct pipe_video_codec *templat,
 					       struct radeon_winsys* ws,
 					       rvce_get_buffer get_buffer);
 
-bool si_vce_is_fw_version_supported(struct r600_common_screen *rscreen);
+bool si_vce_is_fw_version_supported(struct si_screen *sscreen);
 
 void si_vce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf,
 		       enum radeon_bo_usage usage, enum radeon_bo_domain domain,
 		       signed offset);
 
 /* init vce fw 40.2.2 specific callbacks */
 void si_vce_40_2_2_init(struct rvce_encoder *enc);
 
 /* init vce fw 50 specific callbacks */
 void si_vce_50_init(struct rvce_encoder *enc);
diff --git a/src/gallium/drivers/radeon/radeon_vce_52.c b/src/gallium/drivers/radeon/radeon_vce_52.c
index 3f2e6cb..10bf718 100644
--- a/src/gallium/drivers/radeon/radeon_vce_52.c
+++ b/src/gallium/drivers/radeon/radeon_vce_52.c
@@ -27,21 +27,21 @@
 
 #include <stdio.h>
 
 #include "pipe/p_video_codec.h"
 
 #include "util/u_video.h"
 #include "util/u_memory.h"
 
 #include "vl/vl_video_buffer.h"
 
-#include "r600_pipe_common.h"
+#include "radeonsi/si_pipe.h"
 #include "radeon_video.h"
 #include "radeon_vce.h"
 
 static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
 
 static void get_rate_control_param(struct rvce_encoder *enc, struct pipe_h264_enc_picture_desc *pic)
 {
 	enc->enc_pic.rc.rc_method = pic->rate_ctrl.rate_ctrl_method;
 	enc->enc_pic.rc.target_bitrate = pic->rate_ctrl.target_bitrate;
 	enc->enc_pic.rc.peak_bitrate = pic->rate_ctrl.peak_bitrate;
@@ -160,54 +160,54 @@ void si_vce_52_get_param(struct rvce_encoder *enc, struct pipe_h264_enc_picture_
 	enc->enc_pic.not_referenced = pic->not_referenced;
 	if (enc->dual_inst)
 		enc->enc_pic.addrmode_arraymode_disrdo_distwoinstants = 0x00000201;
 	else
 		enc->enc_pic.addrmode_arraymode_disrdo_distwoinstants = 0x01000201;
 	enc->enc_pic.is_idr = pic->is_idr;
 }
 
 static void create(struct rvce_encoder *enc)
 {
-	struct r600_common_screen *rscreen = (struct r600_common_screen *)enc->screen;
+	struct si_screen *sscreen = (struct si_screen *)enc->screen;
 	enc->task_info(enc, 0x00000000, 0, 0, 0);
 
 	RVCE_BEGIN(0x01000001); // create cmd
 	RVCE_CS(enc->enc_pic.ec.enc_use_circular_buffer);
 	RVCE_CS(profiles[enc->base.profile -
 		PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE]); // encProfile
 	RVCE_CS(enc->base.level); // encLevel
 	RVCE_CS(enc->enc_pic.ec.enc_pic_struct_restriction);
 	RVCE_CS(enc->base.width); // encImageWidth
 	RVCE_CS(enc->base.height); // encImageHeight
 
-	if (rscreen->chip_class < GFX9) {
+	if (sscreen->info.chip_class < GFX9) {
 		RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch
 		RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch
 		RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16) / 8); // encRefYHeightInQw
 	} else {
 		RVCE_CS(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe); // encRefPicLumaPitch
 		RVCE_CS(enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe); // encRefPicChromaPitch
 		RVCE_CS(align(enc->luma->u.gfx9.surf_height, 16) / 8); // encRefYHeightInQw
 	}
 
 	RVCE_CS(enc->enc_pic.addrmode_arraymode_disrdo_distwoinstants);
 
 	RVCE_CS(enc->enc_pic.ec.enc_pre_encode_context_buffer_offset);
 	RVCE_CS(enc->enc_pic.ec.enc_pre_encode_input_luma_buffer_offset);
 	RVCE_CS(enc->enc_pic.ec.enc_pre_encode_input_chroma_buffer_offset);
 	RVCE_CS(enc->enc_pic.ec.enc_pre_encode_mode_chromaflag_vbaqmode_scenechangesensitivity);
 	RVCE_END();
 }
 
 static void encode(struct rvce_encoder *enc)
 {
-	struct r600_common_screen *rscreen = (struct r600_common_screen *)enc->screen;
+	struct si_screen *sscreen = (struct si_screen *)enc->screen;
 	signed luma_offset, chroma_offset, bs_offset;
 	unsigned dep, bs_idx = enc->bs_idx++;
 	int i;
 
 	if (enc->dual_inst) {
 		if (bs_idx == 0)
 			dep = 1;
 		else if (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
 			dep = 0;
 		else
@@ -243,21 +243,21 @@ static void encode(struct rvce_encoder *enc)
 
 	RVCE_BEGIN(0x03000001); // encode
 	RVCE_CS(enc->enc_pic.frame_num ? 0x0 : 0x11); // insertHeaders
 	RVCE_CS(enc->enc_pic.eo.picture_structure);
 	RVCE_CS(enc->bs_size); // allowedMaxBitstreamSize
 	RVCE_CS(enc->enc_pic.eo.force_refresh_map);
 	RVCE_CS(enc->enc_pic.eo.insert_aud);
 	RVCE_CS(enc->enc_pic.eo.end_of_sequence);
 	RVCE_CS(enc->enc_pic.eo.end_of_stream);
 
-	if (rscreen->chip_class < GFX9) {
+	if (sscreen->info.chip_class < GFX9) {
 		RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
 			enc->luma->u.legacy.level[0].offset); // inputPictureLumaAddressHi/Lo
 		RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
 			enc->chroma->u.legacy.level[0].offset); // inputPictureChromaAddressHi/Lo
 		RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch
 		RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
 		RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
 	} else {
 		RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
 			enc->luma->u.gfx9.surf_offset); // inputPictureLumaAddressHi/Lo
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 2ece4a3..30cd607 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -28,21 +28,21 @@
 #include <assert.h>
 #include <stdio.h>
 
 #include "pipe/p_video_codec.h"
 
 #include "util/u_memory.h"
 #include "util/u_video.h"
 
 #include "vl/vl_mpeg12_decoder.h"
 
-#include "r600_pipe_common.h"
+#include "radeonsi/si_pipe.h"
 #include "radeon_video.h"
 #include "radeon_vcn_dec.h"
 
 #define FB_BUFFER_OFFSET		0x1000
 #define FB_BUFFER_SIZE			2048
 #define IT_SCALING_TABLE_SIZE		992
 #define RDECODE_SESSION_CONTEXT_SIZE	(128 * 1024)
 
 #define RDECODE_GPCOM_VCPU_CMD		0x2070c
 #define RDECODE_GPCOM_VCPU_DATA0	0x20710
@@ -192,21 +192,21 @@ static rvcn_dec_message_hevc_t get_h265_msg(struct radeon_decoder *dec,
 	result.sps_info_flags = 0;
 	result.sps_info_flags |= pic->pps->sps->scaling_list_enabled_flag << 0;
 	result.sps_info_flags |= pic->pps->sps->amp_enabled_flag << 1;
 	result.sps_info_flags |= pic->pps->sps->sample_adaptive_offset_enabled_flag << 2;
 	result.sps_info_flags |= pic->pps->sps->pcm_enabled_flag << 3;
 	result.sps_info_flags |= pic->pps->sps->pcm_loop_filter_disabled_flag << 4;
 	result.sps_info_flags |= pic->pps->sps->long_term_ref_pics_present_flag << 5;
 	result.sps_info_flags |= pic->pps->sps->sps_temporal_mvp_enabled_flag << 6;
 	result.sps_info_flags |= pic->pps->sps->strong_intra_smoothing_enabled_flag << 7;
 	result.sps_info_flags |= pic->pps->sps->separate_colour_plane_flag << 8;
-	if (((struct r600_common_screen*)dec->screen)->family == CHIP_CARRIZO)
+	if (((struct si_screen*)dec->screen)->info.family == CHIP_CARRIZO)
 		result.sps_info_flags |= 1 << 9;
 	if (pic->UseRefPicList == true)
 		result.sps_info_flags |= 1 << 10;
 
 	result.chroma_format = pic->pps->sps->chroma_format_idc;
 	result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
 	result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
 	result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
 	result.sps_max_dec_pic_buffering_minus1 = pic->pps->sps->sps_max_dec_pic_buffering_minus1;
 	result.log2_min_luma_coding_block_size_minus3 =
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.c b/src/gallium/drivers/radeon/radeon_vcn_enc.c
index 9806a69..4972d11 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.c
@@ -27,21 +27,21 @@
 
 #include <stdio.h>
 
 #include "pipe/p_video_codec.h"
 
 #include "util/u_video.h"
 #include "util/u_memory.h"
 
 #include "vl/vl_video_buffer.h"
 
-#include "r600_pipe_common.h"
+#include "radeonsi/si_pipe.h"
 #include "radeon_video.h"
 #include "radeon_vcn_enc.h"
 
 static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct pipe_h264_enc_picture_desc *pic)
 {
 	enc->enc_pic.picture_type = pic->picture_type;
 	enc->enc_pic.frame_num = pic->frame_num;
 	enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
 	enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
 	enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
@@ -214,21 +214,21 @@ static void radeon_enc_get_feedback(struct pipe_video_codec *encoder,
 
 	si_vid_destroy_buffer(fb);
 	FREE(fb);
 }
 
 struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
 		const struct pipe_video_codec *templ,
 		struct radeon_winsys* ws,
 		radeon_enc_get_buffer get_buffer)
 {
-	struct r600_common_screen *rscreen = (struct r600_common_screen *)context->screen;
+	struct si_screen *sscreen = (struct si_screen *)context->screen;
 	struct r600_common_context *rctx = (struct r600_common_context*)context;
 	struct radeon_encoder *enc;
 	struct pipe_video_buffer *tmp_buf, templat = {};
 	struct radeon_surf *tmp_surf;
 	unsigned cpb_size;
 
 	enc = CALLOC_STRUCT(radeon_encoder);
 
 	if (!enc)
 		return NULL;
@@ -268,21 +268,21 @@ struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
 		goto error;
 	}
 
 	enc->cpb_num = get_cpb_num(enc);
 
 	if (!enc->cpb_num)
 		goto error;
 
 	get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
 
-	cpb_size = (rscreen->chip_class < GFX9) ?
+	cpb_size = (sscreen->info.chip_class < GFX9) ?
 			   align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
 			   align(tmp_surf->u.legacy.level[0].nblk_y, 32) :
 			   align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
 			   align(tmp_surf->u.gfx9.surf_height, 32);
 
 	cpb_size = cpb_size * 3 / 2;
 	cpb_size = cpb_size * enc->cpb_num;
 	tmp_buf->destroy(tmp_buf);
 
 	if (!si_vid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) {
diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c
index a5505ab..d80410d 100644
--- a/src/gallium/drivers/radeon/radeon_video.c
+++ b/src/gallium/drivers/radeon/radeon_video.c
@@ -26,21 +26,21 @@
  **************************************************************************/
 
 #include <unistd.h>
 
 #include "util/u_memory.h"
 #include "util/u_video.h"
 
 #include "vl/vl_defines.h"
 #include "vl/vl_video_buffer.h"
 
-#include "r600_pipe_common.h"
+#include "radeonsi/si_pipe.h"
 #include "radeon_video.h"
 #include "radeon_vce.h"
 
 /* generate an stream handle */
 unsigned si_vid_alloc_stream_handle()
 {
 	static unsigned counter = 0;
 	unsigned stream_handle = 0;
 	unsigned pid = getpid();
 	int i;
@@ -73,22 +73,22 @@ bool si_vid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer
 /* destroy a buffer */
 void si_vid_destroy_buffer(struct rvid_buffer *buffer)
 {
 	r600_resource_reference(&buffer->res, NULL);
 }
 
 /* reallocate a buffer, preserving its content */
 bool si_vid_resize_buffer(struct pipe_screen *screen, struct radeon_winsys_cs *cs,
 			  struct rvid_buffer *new_buf, unsigned new_size)
 {
-	struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
-	struct radeon_winsys* ws = rscreen->ws;
+	struct si_screen *sscreen = (struct si_screen *)screen;
+	struct radeon_winsys* ws = sscreen->ws;
 	unsigned bytes = MIN2(new_buf->res->buf->size, new_size);
 	struct rvid_buffer old_buf = *new_buf;
 	void *src = NULL, *dst = NULL;
 
 	if (!si_vid_create_buffer(screen, new_buf, new_size, new_buf->usage))
 		goto error;
 
 	src = ws->buffer_map(old_buf.res->buf, cs, PIPE_TRANSFER_READ);
 	if (!src)
 		goto error;
diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c b/src/gallium/drivers/radeonsi/cik_sdma.c
index 8a18bbf..3e3b9cd 100644
--- a/src/gallium/drivers/radeonsi/cik_sdma.c
+++ b/src/gallium/drivers/radeonsi/cik_sdma.c
@@ -110,21 +110,21 @@ static void cik_sdma_clear_buffer(struct pipe_context *ctx,
 static unsigned minify_as_blocks(unsigned width, unsigned level, unsigned blk_w)
 {
 	width = u_minify(width, level);
 	return DIV_ROUND_UP(width, blk_w);
 }
 
 static unsigned encode_tile_info(struct si_context *sctx,
 				 struct r600_texture *tex, unsigned level,
 				 bool set_bpp)
 {
-	struct radeon_info *info = &sctx->screen->b.info;
+	struct radeon_info *info = &sctx->screen->info;
 	unsigned tile_index = tex->surface.u.legacy.tiling_index[level];
 	unsigned macro_tile_index = tex->surface.u.legacy.macro_tile_index;
 	unsigned tile_mode = info->si_tile_mode_array[tile_index];
 	unsigned macro_tile_mode = info->cik_macrotile_mode_array[macro_tile_index];
 
 	return (set_bpp ? util_logbase2(tex->surface.bpe) : 0) |
 		(G_009910_ARRAY_MODE(tile_mode) << 3) |
 		(G_009910_MICRO_TILE_MODE_NEW(tile_mode) << 8) |
 		/* Non-depth modes don't have TILE_SPLIT set. */
 		((util_logbase2(tex->surface.u.legacy.tile_split >> 6)) << 11) |
@@ -136,21 +136,21 @@ static unsigned encode_tile_info(struct si_context *sctx,
 }
 
 static bool cik_sdma_copy_texture(struct si_context *sctx,
 				  struct pipe_resource *dst,
 				  unsigned dst_level,
 				  unsigned dstx, unsigned dsty, unsigned dstz,
 				  struct pipe_resource *src,
 				  unsigned src_level,
 				  const struct pipe_box *src_box)
 {
-	struct radeon_info *info = &sctx->screen->b.info;
+	struct radeon_info *info = &sctx->screen->info;
 	struct r600_texture *rsrc = (struct r600_texture*)src;
 	struct r600_texture *rdst = (struct r600_texture*)dst;
 	unsigned bpp = rdst->surface.bpe;
 	uint64_t dst_address = rdst->resource.gpu_address +
 			       rdst->surface.u.legacy.level[dst_level].offset;
 	uint64_t src_address = rsrc->resource.gpu_address +
 			       rsrc->surface.u.legacy.level[src_level].offset;
 	unsigned dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
 	unsigned src_mode = rsrc->surface.u.legacy.level[src_level].mode;
 	unsigned dst_tile_index = rdst->surface.u.legacy.tiling_index[dst_level];
diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index 0e314e9..370ce04 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -765,21 +765,21 @@ static void si_decompress_resident_images(struct si_context *sctx)
 }
 
 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
 {
 	unsigned compressed_colortex_counter, mask;
 
 	if (sctx->blitter->running)
 		return;
 
 	/* Update the compressed_colortex_mask if necessary. */
-	compressed_colortex_counter = p_atomic_read(&sctx->screen->b.compressed_colortex_counter);
+	compressed_colortex_counter = p_atomic_read(&sctx->screen->compressed_colortex_counter);
 	if (compressed_colortex_counter != sctx->b.last_compressed_colortex_counter) {
 		sctx->b.last_compressed_colortex_counter = compressed_colortex_counter;
 		si_update_needs_color_decompress_masks(sctx);
 	}
 
 	/* Decompress color & depth textures if needed. */
 	mask = sctx->shader_needs_decompress_mask & shader_mask;
 	while (mask) {
 		unsigned i = u_bit_scan(&mask);
 
@@ -1233,21 +1233,21 @@ static void si_blit(struct pipe_context *ctx,
 					      info->src.level,
 					      info->src.format);
 	vi_disable_dcc_if_incompatible_format(&sctx->b, info->dst.resource,
 					      info->dst.level,
 					      info->dst.format);
 	si_decompress_subresource(ctx, info->src.resource, info->mask,
 				  info->src.level,
 				  info->src.box.z,
 				  info->src.box.z + info->src.box.depth - 1);
 
-	if (sctx->screen->b.debug_flags & DBG(FORCE_DMA) &&
+	if (sctx->screen->debug_flags & DBG(FORCE_DMA) &&
 	    util_try_blit_via_copy_region(ctx, info))
 		return;
 
 	si_blitter_begin(ctx, SI_BLIT |
 			 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
 	util_blitter_blit(sctx->blitter, info);
 	si_blitter_end(ctx);
 }
 
 static boolean si_generate_mipmap(struct pipe_context *ctx,
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 634d4cc..ba95ed5 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -34,41 +34,41 @@ enum {
 };
 
 static void si_alloc_separate_cmask(struct si_screen *sscreen,
 				    struct r600_texture *rtex)
 {
 	if (rtex->cmask_buffer)
                 return;
 
 	assert(rtex->cmask.size == 0);
 
-	si_texture_get_cmask_info(&sscreen->b, rtex, &rtex->cmask);
+	si_texture_get_cmask_info(sscreen, rtex, &rtex->cmask);
 	if (!rtex->cmask.size)
 		return;
 
 	rtex->cmask_buffer = (struct r600_resource *)
-		si_aligned_buffer_create(&sscreen->b.b,
+		si_aligned_buffer_create(&sscreen->b,
 					 R600_RESOURCE_FLAG_UNMAPPABLE,
 					 PIPE_USAGE_DEFAULT,
 					 rtex->cmask.size,
 					 rtex->cmask.alignment);
 	if (rtex->cmask_buffer == NULL) {
 		rtex->cmask.size = 0;
 		return;
 	}
 
 	/* update colorbuffer state bits */
 	rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
 
 	rtex->cb_color_info |= S_028C70_FAST_CLEAR(1);
 
-	p_atomic_inc(&sscreen->b.compressed_colortex_counter);
+	p_atomic_inc(&sscreen->compressed_colortex_counter);
 }
 
 static void si_set_clear_color(struct r600_texture *rtex,
 			       enum pipe_format surface_format,
 			       const union pipe_color_union *color)
 {
 	union util_color uc;
 
 	memset(&uc, 0, sizeof(uc));
 
@@ -238,25 +238,25 @@ void vi_dcc_clear_level(struct si_context *sctx,
  * src and dst micro tile modes match.
  */
 static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen,
 					   struct r600_texture *rtex)
 {
 	if (rtex->resource.b.is_shared ||
 	    rtex->resource.b.b.nr_samples <= 1 ||
 	    rtex->surface.micro_tile_mode == rtex->last_msaa_resolve_target_micro_mode)
 		return;
 
-	assert(sscreen->b.chip_class >= GFX9 ||
+	assert(sscreen->info.chip_class >= GFX9 ||
 	       rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
 	assert(rtex->resource.b.b.last_level == 0);
 
-	if (sscreen->b.chip_class >= GFX9) {
+	if (sscreen->info.chip_class >= GFX9) {
 		/* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
 		assert(rtex->surface.u.gfx9.surf.swizzle_mode >= 4);
 
 		/* If you do swizzle_mode % 4, you'll get:
 		 *   0 = Depth
 		 *   1 = Standard,
 		 *   2 = Displayable
 		 *   3 = Rotated
 		 *
 		 * Depth-sample order isn't allowed:
@@ -273,21 +273,21 @@ static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen,
 			rtex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
 			break;
 		case RADEON_MICRO_MODE_ROTATED:
 			rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
 			rtex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
 			break;
 		default: /* depth */
 			assert(!"unexpected micro mode");
 			return;
 		}
-	} else if (sscreen->b.chip_class >= CIK) {
+	} else if (sscreen->info.chip_class >= CIK) {
 		/* These magic numbers were copied from addrlib. It doesn't use
 		 * any definitions for them either. They are all 2D_TILED_THIN1
 		 * modes with different bpp and micro tile mode.
 		 */
 		switch (rtex->last_msaa_resolve_target_micro_mode) {
 		case RADEON_MICRO_MODE_DISPLAY:
 			rtex->surface.u.legacy.tiling_index[0] = 10;
 			break;
 		case RADEON_MICRO_MODE_THIN:
 			rtex->surface.u.legacy.tiling_index[0] = 14;
@@ -331,21 +331,21 @@ static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen,
 			}
 			break;
 		default: /* depth, thick */
 			assert(!"unexpected micro mode");
 			return;
 		}
 	}
 
 	rtex->surface.micro_tile_mode = rtex->last_msaa_resolve_target_micro_mode;
 
-	p_atomic_inc(&sscreen->b.dirty_tex_counter);
+	p_atomic_inc(&sscreen->dirty_tex_counter);
 }
 
 static void si_do_fast_color_clear(struct si_context *sctx,
 				   unsigned *buffers,
 				   const union pipe_color_union *color)
 {
 	struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
 	int i;
 
 	/* This function is broken in BE, so just disable this path for now */
@@ -390,61 +390,61 @@ static void si_do_fast_color_clear(struct si_context *sctx,
 		 * because there is no way to communicate the clear color among
 		 * all clients
 		 */
 		if (tex->resource.b.is_shared &&
 		    !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
 			continue;
 
 		/* fast color clear with 1D tiling doesn't work on old kernels and CIK */
 		if (sctx->b.chip_class == CIK &&
 		    tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
-		    sctx->screen->b.info.drm_major == 2 &&
-		    sctx->screen->b.info.drm_minor < 38) {
+		    sctx->screen->info.drm_major == 2 &&
+		    sctx->screen->info.drm_minor < 38) {
 			continue;
 		}
 
 		/* Fast clear is the most appropriate place to enable DCC for
 		 * displayable surfaces.
 		 */
 		if (sctx->b.chip_class >= VI &&
-		    !(sctx->screen->b.debug_flags & DBG(NO_DCC_FB))) {
+		    !(sctx->screen->debug_flags & DBG(NO_DCC_FB))) {
 			vi_separate_dcc_try_enable(&sctx->b, tex);
 
 			/* RB+ isn't supported with a CMASK clear only on Stoney,
 			 * so all clears are considered to be hypothetically slow
 			 * clears, which is weighed when determining whether to
 			 * enable separate DCC.
 			 */
 			if (tex->dcc_gather_statistics &&
 			    sctx->b.family == CHIP_STONEY)
 				tex->num_slow_clears++;
 		}
 
 		bool need_decompress_pass = false;
 
 		/* Use a slow clear for small surfaces where the cost of
 		 * the eliminate pass can be higher than the benefit of fast
 		 * clear. The closed driver does this, but the numbers may differ.
 		 *
 		 * Always use fast clear on APUs.
 		 */
-		bool too_small = sctx->screen->b.info.has_dedicated_vram &&
+		bool too_small = sctx->screen->info.has_dedicated_vram &&
 				 tex->resource.b.b.nr_samples <= 1 &&
 				 tex->resource.b.b.width0 <= 256 &&
 				 tex->resource.b.b.height0 <= 256;
 
 		/* Try to clear DCC first, otherwise try CMASK. */
 		if (vi_dcc_enabled(tex, 0)) {
 			uint32_t reset_value;
 			bool clear_words_needed;
 
-			if (sctx->screen->b.debug_flags & DBG(NO_DCC_CLEAR))
+			if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
 				continue;
 
 			/* This can only occur with MSAA. */
 			if (sctx->b.chip_class == VI &&
 			    !tex->surface.u.legacy.level[level].dcc_fast_clear_size)
 				continue;
 
 			if (!vi_get_fast_clear_parameters(fb->cbufs[i]->format,
 							  color, &reset_value,
 							  &clear_words_needed))
@@ -493,21 +493,21 @@ static void si_do_fast_color_clear(struct si_context *sctx,
 			/* Do the fast clear. */
 			si_clear_buffer(&sctx->b.b, &tex->cmask_buffer->b.b,
 					tex->cmask.offset, tex->cmask.size, 0,
 					R600_COHERENCY_CB_META);
 			need_decompress_pass = true;
 		}
 
 		if (need_decompress_pass &&
 		    !(tex->dirty_level_mask & (1 << level))) {
 			tex->dirty_level_mask |= 1 << level;
-			p_atomic_inc(&sctx->screen->b.compressed_colortex_counter);
+			p_atomic_inc(&sctx->screen->compressed_colortex_counter);
 		}
 
 		/* We can change the micro tile mode before a full clear. */
 		si_set_optimal_micro_tile_mode(sctx->screen, tex);
 
 		si_set_clear_color(tex, fb->cbufs[i]->format, color);
 
 		sctx->framebuffer.dirty_cbufs |= 1 << i;
 		si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
 		*buffers &= ~clear_bit;
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index f3dce65..ac4fab3 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -28,21 +28,21 @@
 #include "util/u_upload_mgr.h"
 
 #include "amd_kernel_code_t.h"
 #include "radeon/r600_cs.h"
 #include "si_pipe.h"
 #include "si_compute.h"
 #include "sid.h"
 
 #define COMPUTE_DBG(rscreen, fmt, args...) \
 	do { \
-		if ((rscreen->b.debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
+		if ((rscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
 	} while (0);
 
 struct dispatch_packet {
 	uint16_t header;
 	uint16_t setup;
 	uint16_t workgroup_size_x;
 	uint16_t workgroup_size_y;
 	uint16_t workgroup_size_z;
 	uint16_t reserved0;
 	uint32_t grid_size_x;
@@ -164,21 +164,21 @@ static void *si_create_compute_state(
 
 	if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
 		program->tokens = tgsi_dup_tokens(cso->prog);
 		if (!program->tokens) {
 			FREE(program);
 			return NULL;
 		}
 
 		program->compiler_ctx_state.debug = sctx->debug;
 		program->compiler_ctx_state.is_debug_context = sctx->is_debug;
-		p_atomic_inc(&sscreen->b.num_shaders_created);
+		p_atomic_inc(&sscreen->num_shaders_created);
 		util_queue_fence_init(&program->ready);
 
 		struct util_async_debug_callback async_debug;
 		bool wait =
 			(sctx->debug.debug_message && !sctx->debug.async) ||
 			sctx->is_debug ||
 			si_can_dump_shader(sscreen, PIPE_SHADER_COMPUTE);
 
 		if (wait) {
 			u_async_debug_init(&async_debug);
@@ -308,23 +308,23 @@ static void si_initialize_compute(struct si_context *sctx)
 	}
 
 	/* Set the pointer to border colors. */
 	bc_va = sctx->border_color_buffer->gpu_address;
 
 	if (sctx->b.chip_class >= CIK) {
 		radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
 		radeon_emit(cs, bc_va >> 8);  /* R_030E00_TA_CS_BC_BASE_ADDR */
 		radeon_emit(cs, bc_va >> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
 	} else {
-		if (sctx->screen->b.info.drm_major == 3 ||
-		    (sctx->screen->b.info.drm_major == 2 &&
-		     sctx->screen->b.info.drm_minor >= 48)) {
+		if (sctx->screen->info.drm_major == 3 ||
+		    (sctx->screen->info.drm_major == 2 &&
+		     sctx->screen->info.drm_minor >= 48)) {
 			radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
 					      bc_va >> 8);
 		}
 	}
 
 	sctx->cs_shader_state.emitted_program = NULL;
 	sctx->cs_shader_state.initialized = true;
 }
 
 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
@@ -334,21 +334,21 @@ static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
 	uint64_t scratch_bo_size, scratch_needed;
 	scratch_bo_size = 0;
 	scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
 	if (sctx->compute_scratch_buffer)
 		scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
 
 	if (scratch_bo_size < scratch_needed) {
 		r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
 
 		sctx->compute_scratch_buffer = (struct r600_resource*)
-			si_aligned_buffer_create(&sctx->screen->b.b,
+			si_aligned_buffer_create(&sctx->screen->b,
 						   R600_RESOURCE_FLAG_UNMAPPABLE,
 						   PIPE_USAGE_DEFAULT,
 						   scratch_needed, 256);
 
 		if (!sctx->compute_scratch_buffer)
 			return false;
 	}
 
 	if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
 		uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
@@ -617,21 +617,21 @@ static bool si_upload_compute_input(struct si_context *sctx,
 	uint32_t kernel_args_offset = 0;
 	uint32_t *kernel_args;
 	void *kernel_args_ptr;
 	uint64_t kernel_args_va;
 	unsigned i;
 
 	/* The extra num_work_size_bytes are for work group / work item size information */
 	kernel_args_size = program->input_size + num_work_size_bytes;
 
 	u_upload_alloc(sctx->b.b.const_uploader, 0, kernel_args_size,
-		       sctx->screen->b.info.tcc_cache_line_size,
+		       sctx->screen->info.tcc_cache_line_size,
 		       &kernel_args_offset,
 		       (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
 
 	if (unlikely(!kernel_args_ptr))
 		return false;
 
 	kernel_args = (uint32_t*)kernel_args_ptr;
 	kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
 
 	if (!code_object) {
@@ -721,22 +721,22 @@ static void si_emit_dispatch_packets(struct si_context *sctx,
 {
 	struct si_screen *sscreen = sctx->screen;
 	struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 	bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
 	unsigned waves_per_threadgroup =
 		DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
 	unsigned compute_resource_limits =
 		S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
 
 	if (sctx->b.chip_class >= CIK) {
-		unsigned num_cu_per_se = sscreen->b.info.num_good_compute_units /
-					 sscreen->b.info.max_se;
+		unsigned num_cu_per_se = sscreen->info.num_good_compute_units /
+					 sscreen->info.max_se;
 
 		/* Force even distribution on all SIMDs in CU if the workgroup
 		 * size is 64. This has shown some good improvements if # of CUs
 		 * per SE is not a multiple of 4.
 		 */
 		if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
 			compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
 	}
 
 	radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index 446ff2c..b665926 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -365,21 +365,21 @@ static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size,
 
 	assert(size < SI_CPDMA_ALIGNMENT);
 
 	/* Use the scratch buffer as the dummy buffer. The 3D engine should be
 	 * idle at this point.
 	 */
 	if (!sctx->scratch_buffer ||
 	    sctx->scratch_buffer->b.b.width0 < scratch_size) {
 		r600_resource_reference(&sctx->scratch_buffer, NULL);
 		sctx->scratch_buffer = (struct r600_resource*)
-			si_aligned_buffer_create(&sctx->screen->b.b,
+			si_aligned_buffer_create(&sctx->screen->b,
 						   R600_RESOURCE_FLAG_UNMAPPABLE,
 						   PIPE_USAGE_DEFAULT,
 						   scratch_size, 256);
 		if (!sctx->scratch_buffer)
 			return;
 
 		si_mark_atom_dirty(sctx, &sctx->scratch_state);
 	}
 
 	si_cp_dma_prepare(sctx, &sctx->scratch_buffer->b.b,
diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c
index 447b4ef..22609b7 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -227,30 +227,30 @@ static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f,
 {
 	struct radeon_winsys *ws = sctx->b.ws;
 	uint32_t value;
 
 	if (ws->read_registers(ws, offset, 1, &value))
 		ac_dump_reg(f, sctx->b.chip_class, offset, value, ~0);
 }
 
 static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
 {
-	if (sctx->screen->b.info.drm_major == 2 &&
-	    sctx->screen->b.info.drm_minor < 42)
+	if (sctx->screen->info.drm_major == 2 &&
+	    sctx->screen->info.drm_minor < 42)
 		return; /* no radeon support */
 
 	fprintf(f, "Memory-mapped registers:\n");
 	si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
 
 	/* No other registers can be read on DRM < 3.1.0. */
-	if (sctx->screen->b.info.drm_major < 3 ||
-	    sctx->screen->b.info.drm_minor < 1) {
+	if (sctx->screen->info.drm_major < 3 ||
+	    sctx->screen->info.drm_minor < 1) {
 		fprintf(f, "\n");
 		return;
 	}
 
 	si_dump_mmapped_reg(sctx, f, R_008008_GRBM_STATUS2);
 	si_dump_mmapped_reg(sctx, f, R_008014_GRBM_STATUS_SE0);
 	si_dump_mmapped_reg(sctx, f, R_008018_GRBM_STATUS_SE1);
 	si_dump_mmapped_reg(sctx, f, R_008038_GRBM_STATUS_SE2);
 	si_dump_mmapped_reg(sctx, f, R_00803C_GRBM_STATUS_SE3);
 	si_dump_mmapped_reg(sctx, f, R_00D034_SDMA0_STATUS_REG);
@@ -685,21 +685,21 @@ static void si_dump_descriptor_list(struct si_screen *screen,
 	}
 
 	struct si_log_chunk_desc_list *chunk =
 		CALLOC_VARIANT_LENGTH_STRUCT(si_log_chunk_desc_list,
 					     4 * element_dw_size * num_elements);
 	chunk->shader_name = shader_name;
 	chunk->elem_name = elem_name;
 	chunk->element_dw_size = element_dw_size;
 	chunk->num_elements = num_elements;
 	chunk->slot_remap = slot_remap;
-	chunk->chip_class = screen->b.chip_class;
+	chunk->chip_class = screen->info.chip_class;
 
 	r600_resource_reference(&chunk->buf, desc->buffer);
 	chunk->gpu_list = desc->gpu_list;
 
 	for (unsigned i = 0; i < num_elements; ++i) {
 		memcpy(&chunk->list[i * element_dw_size],
 		       &desc->list[slot_remap(i) * element_dw_size],
 		       4 * element_dw_size);
 	}
 
@@ -1096,14 +1096,14 @@ void si_check_vm_faults(struct r600_common_context *ctx,
 }
 
 void si_init_debug_functions(struct si_context *sctx)
 {
 	sctx->b.b.dump_debug_state = si_dump_debug_state;
 	sctx->b.check_vm_faults = si_check_vm_faults;
 
 	/* Set the initial dmesg timestamp for this context, so that
 	 * only new messages will be checked for VM faults.
 	 */
-	if (sctx->screen->b.debug_flags & DBG(CHECK_VM))
+	if (sctx->screen->debug_flags & DBG(CHECK_VM))
 		ac_vm_fault_occured(sctx->b.chip_class,
 				    &sctx->dmesg_timestamp, NULL);
 }
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index e91f923..7d7be84 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -318,66 +318,66 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 {
 	uint64_t va, meta_va = 0;
 
 	if (tex->is_depth && !si_can_sample_zs(tex, is_stencil)) {
 		tex = tex->flushed_depth_texture;
 		is_stencil = false;
 	}
 
 	va = tex->resource.gpu_address;
 
-	if (sscreen->b.chip_class >= GFX9) {
+	if (sscreen->info.chip_class >= GFX9) {
 		/* Only stencil_offset needs to be added here. */
 		if (is_stencil)
 			va += tex->surface.u.gfx9.stencil_offset;
 		else
 			va += tex->surface.u.gfx9.surf_offset;
 	} else {
 		va += base_level_info->offset;
 	}
 
 	state[0] = va >> 8;
 	state[1] &= C_008F14_BASE_ADDRESS_HI;
 	state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
 
 	/* Only macrotiled modes can set tile swizzle.
 	 * GFX9 doesn't use (legacy) base_level_info.
 	 */
-	if (sscreen->b.chip_class >= GFX9 ||
+	if (sscreen->info.chip_class >= GFX9 ||
 	    base_level_info->mode == RADEON_SURF_MODE_2D)
 		state[0] |= tex->surface.tile_swizzle;
 
-	if (sscreen->b.chip_class >= VI) {
+	if (sscreen->info.chip_class >= VI) {
 		state[6] &= C_008F28_COMPRESSION_EN;
 		state[7] = 0;
 
 		if (vi_dcc_enabled(tex, first_level)) {
 			meta_va = (!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
 				  tex->dcc_offset;
 
-			if (sscreen->b.chip_class == VI) {
+			if (sscreen->info.chip_class == VI) {
 				meta_va += base_level_info->dcc_offset;
 				assert(base_level_info->mode == RADEON_SURF_MODE_2D);
 			}
 
 			meta_va |= (uint32_t)tex->surface.tile_swizzle << 8;
 		} else if (vi_tc_compat_htile_enabled(tex, first_level)) {
 			meta_va = tex->resource.gpu_address + tex->htile_offset;
 		}
 
 		if (meta_va) {
 			state[6] |= S_008F28_COMPRESSION_EN(1);
 			state[7] = meta_va >> 8;
 		}
 	}
 
-	if (sscreen->b.chip_class >= GFX9) {
+	if (sscreen->info.chip_class >= GFX9) {
 		state[3] &= C_008F1C_SW_MODE;
 		state[4] &= C_008F20_PITCH_GFX9;
 
 		if (is_stencil) {
 			state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
 			state[4] |= S_008F20_PITCH_GFX9(tex->surface.u.gfx9.stencil.epitch);
 		} else {
 			state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode);
 			state[4] |= S_008F20_PITCH_GFX9(tex->surface.u.gfx9.surf.epitch);
 		}
@@ -1728,21 +1728,21 @@ static void si_rebind_buffer(struct pipe_context *ctx, struct pipe_resource *buf
  * idle by discarding its contents. Apps usually tell us when to do this using
  * map_buffer flags, for example.
  */
 static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
 {
 	struct si_context *sctx = (struct si_context*)ctx;
 	struct r600_resource *rbuffer = r600_resource(buf);
 	uint64_t old_va = rbuffer->gpu_address;
 
 	/* Reallocate the buffer in the same pipe_resource. */
-	si_alloc_resource(&sctx->screen->b, rbuffer);
+	si_alloc_resource(sctx->screen, rbuffer);
 
 	si_rebind_buffer(ctx, buf, old_va);
 }
 
 static void si_upload_bindless_descriptor(struct si_context *sctx,
 					  unsigned desc_slot,
 					  unsigned num_dwords)
 {
 	struct si_descriptors *desc = &sctx->bindless_descriptors;
 	struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
diff --git a/src/gallium/drivers/radeonsi/si_dma.c b/src/gallium/drivers/radeonsi/si_dma.c
index 6e22944..7a6d0b5 100644
--- a/src/gallium/drivers/radeonsi/si_dma.c
+++ b/src/gallium/drivers/radeonsi/si_dma.c
@@ -132,21 +132,21 @@ static void si_dma_copy_tile(struct si_context *ctx,
 {
 	struct radeon_winsys_cs *cs = ctx->b.dma.cs;
 	struct r600_texture *rsrc = (struct r600_texture*)src;
 	struct r600_texture *rdst = (struct r600_texture*)dst;
 	unsigned dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
 	bool detile = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
 	struct r600_texture *rlinear = detile ? rdst : rsrc;
 	struct r600_texture *rtiled = detile ? rsrc : rdst;
 	unsigned linear_lvl = detile ? dst_level : src_level;
 	unsigned tiled_lvl = detile ? src_level : dst_level;
-	struct radeon_info *info = &ctx->screen->b.info;
+	struct radeon_info *info = &ctx->screen->info;
 	unsigned index = rtiled->surface.u.legacy.tiling_index[tiled_lvl];
 	unsigned tile_mode = info->si_tile_mode_array[index];
 	unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
 	unsigned ncopy, height, cheight, i;
 	unsigned linear_x, linear_y, linear_z,  tiled_x, tiled_y, tiled_z;
 	unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, mt;
 	uint64_t base, addr;
 	unsigned pipe_config;
 
 	assert(dst_mode != rsrc->surface.u.legacy.level[src_level].mode);
diff --git a/src/gallium/drivers/radeonsi/si_fence.c b/src/gallium/drivers/radeonsi/si_fence.c
index 6110521..5f478af 100644
--- a/src/gallium/drivers/radeonsi/si_fence.c
+++ b/src/gallium/drivers/radeonsi/si_fence.c
@@ -60,21 +60,21 @@ static void si_add_fence_dependency(struct r600_common_context *rctx,
 
 	if (rctx->dma.cs)
 		ws->cs_add_fence_dependency(rctx->dma.cs, fence);
 	ws->cs_add_fence_dependency(rctx->gfx.cs, fence);
 }
 
 static void si_fence_reference(struct pipe_screen *screen,
 			       struct pipe_fence_handle **dst,
 			       struct pipe_fence_handle *src)
 {
-	struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
+	struct radeon_winsys *ws = ((struct si_screen*)screen)->ws;
 	struct si_multi_fence **rdst = (struct si_multi_fence **)dst;
 	struct si_multi_fence *rsrc = (struct si_multi_fence *)src;
 
 	if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
 		ws->fence_reference(&(*rdst)->gfx, NULL);
 		ws->fence_reference(&(*rdst)->sdma, NULL);
 		tc_unflushed_batch_token_reference(&(*rdst)->tc_token, NULL);
 		r600_resource_reference(&(*rdst)->fine.buf, NULL);
 		FREE(*rdst);
 	}
@@ -179,21 +179,21 @@ static void si_fine_fence_set(struct si_context *ctx,
 	} else {
 		assert(false);
 	}
 }
 
 static boolean si_fence_finish(struct pipe_screen *screen,
 			       struct pipe_context *ctx,
 			       struct pipe_fence_handle *fence,
 			       uint64_t timeout)
 {
-	struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
+	struct radeon_winsys *rws = ((struct si_screen*)screen)->ws;
 	struct si_multi_fence *rfence = (struct si_multi_fence *)fence;
 	int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
 
 	if (!util_queue_fence_is_signalled(&rfence->ready)) {
 		if (rfence->tc_token) {
 			/* Ensure that si_flush_from_st will be called for
 			 * this fence, but only if we're in the API thread
 			 * where the context is current.
 			 *
 			 * Note that the batch containing the flush may already
@@ -293,51 +293,51 @@ static boolean si_fence_finish(struct pipe_screen *screen,
 	if (rfence->fine.buf &&
 	    si_fine_fence_signaled(rws, &rfence->fine))
 		return true;
 
 	return false;
 }
 
 static void si_create_fence_fd(struct pipe_context *ctx,
 			       struct pipe_fence_handle **pfence, int fd)
 {
-	struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
-	struct radeon_winsys *ws = rscreen->ws;
+	struct si_screen *sscreen = (struct si_screen*)ctx->screen;
+	struct radeon_winsys *ws = sscreen->ws;
 	struct si_multi_fence *rfence;
 
 	*pfence = NULL;
 
-	if (!rscreen->info.has_sync_file)
+	if (!sscreen->info.has_sync_file)
 		return;
 
 	rfence = si_create_multi_fence();
 	if (!rfence)
 		return;
 
 	rfence->gfx = ws->fence_import_sync_file(ws, fd);
 	if (!rfence->gfx) {
 		FREE(rfence);
 		return;
 	}
 
 	*pfence = (struct pipe_fence_handle*)rfence;
 }
 
 static int si_fence_get_fd(struct pipe_screen *screen,
 			   struct pipe_fence_handle *fence)
 {
-	struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
-	struct radeon_winsys *ws = rscreen->ws;
+	struct si_screen *sscreen = (struct si_screen*)screen;
+	struct radeon_winsys *ws = sscreen->ws;
 	struct si_multi_fence *rfence = (struct si_multi_fence *)fence;
 	int gfx_fd = -1, sdma_fd = -1;
 
-	if (!rscreen->info.has_sync_file)
+	if (!sscreen->info.has_sync_file)
 		return -1;
 
 	util_queue_fence_wait(&rfence->ready);
 
 	/* Deferred fences aren't supported. */
 	assert(!rfence->gfx_unflushed.ctx);
 	if (rfence->gfx_unflushed.ctx)
 		return -1;
 
 	if (rfence->sdma) {
@@ -463,14 +463,14 @@ finish:
 
 void si_init_fence_functions(struct si_context *ctx)
 {
 	ctx->b.b.flush = si_flush_from_st;
 	ctx->b.b.create_fence_fd = si_create_fence_fd;
 	ctx->b.b.fence_server_sync = si_fence_server_sync;
 }
 
 void si_init_screen_fence_functions(struct si_screen *screen)
 {
-	screen->b.b.fence_finish = si_fence_finish;
-	screen->b.b.fence_reference = si_fence_reference;
-	screen->b.b.fence_get_fd = si_fence_get_fd;
+	screen->b.fence_finish = si_fence_finish;
+	screen->b.fence_reference = si_fence_reference;
+	screen->b.fence_get_fd = si_fence_get_fd;
 }
diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
index 56030f7..7646ea8 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -47,21 +47,21 @@ static const char *si_get_device_vendor(struct pipe_screen *pscreen)
 
 static const char *si_get_marketing_name(struct radeon_winsys *ws)
 {
 	if (!ws->get_chip_name)
 		return NULL;
 	return ws->get_chip_name(ws);
 }
 
 const char *si_get_family_name(const struct si_screen *sscreen)
 {
-	switch (sscreen->b.info.family) {
+	switch (sscreen->info.family) {
 	case CHIP_TAHITI: return "AMD TAHITI";
 	case CHIP_PITCAIRN: return "AMD PITCAIRN";
 	case CHIP_VERDE: return "AMD CAPE VERDE";
 	case CHIP_OLAND: return "AMD OLAND";
 	case CHIP_HAINAN: return "AMD HAINAN";
 	case CHIP_BONAIRE: return "AMD BONAIRE";
 	case CHIP_KAVERI: return "AMD KAVERI";
 	case CHIP_KABINI: return "AMD KABINI";
 	case CHIP_HAWAII: return "AMD HAWAII";
 	case CHIP_MULLINS: return "AMD MULLINS";
@@ -76,24 +76,24 @@ const char *si_get_family_name(const struct si_screen *sscreen)
 	case CHIP_VEGA10: return "AMD VEGA10";
 	case CHIP_RAVEN: return "AMD RAVEN";
 	default: return "AMD unknown";
 	}
 }
 
 static bool si_have_tgsi_compute(struct si_screen *sscreen)
 {
 	/* Old kernels disallowed some register writes for SI
 	 * that are used for indirect dispatches. */
-	return (sscreen->b.chip_class >= CIK ||
-		sscreen->b.info.drm_major == 3 ||
-		(sscreen->b.info.drm_major == 2 &&
-		 sscreen->b.info.drm_minor >= 45));
+	return (sscreen->info.chip_class >= CIK ||
+		sscreen->info.drm_major == 3 ||
+		(sscreen->info.drm_major == 2 &&
+		 sscreen->info.drm_minor >= 45));
 }
 
 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 {
 	struct si_screen *sscreen = (struct si_screen *)pscreen;
 
 	switch (param) {
 	/* Supported features (boolean caps). */
 	case PIPE_CAP_ACCELERATED:
 	case PIPE_CAP_TWO_SIDED_STENCIL:
@@ -193,74 +193,74 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 	case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 		return 1;
 
 	case PIPE_CAP_TGSI_VOTE:
 		return HAVE_LLVM >= 0x0400;
 
 	case PIPE_CAP_TGSI_BALLOT:
 		return HAVE_LLVM >= 0x0500;
 
 	case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
-		return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
+		return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 
 	case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
-		return (sscreen->b.info.drm_major == 2 &&
-			sscreen->b.info.drm_minor >= 43) ||
-		       sscreen->b.info.drm_major == 3;
+		return (sscreen->info.drm_major == 2 &&
+			sscreen->info.drm_minor >= 43) ||
+		       sscreen->info.drm_major == 3;
 
 	case PIPE_CAP_TEXTURE_MULTISAMPLE:
 		/* 2D tiling on CIK is supported since DRM 2.35.0 */
-		return sscreen->b.chip_class < CIK ||
-		       (sscreen->b.info.drm_major == 2 &&
-			sscreen->b.info.drm_minor >= 35) ||
-		       sscreen->b.info.drm_major == 3;
+		return sscreen->info.chip_class < CIK ||
+		       (sscreen->info.drm_major == 2 &&
+			sscreen->info.drm_minor >= 35) ||
+		       sscreen->info.drm_major == 3;
 
         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
                 return R600_MAP_BUFFER_ALIGNMENT;
 
 	case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 	case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 	case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 	case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 	case PIPE_CAP_MAX_VERTEX_STREAMS:
 	case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 		return 4;
 
 	case PIPE_CAP_GLSL_FEATURE_LEVEL:
-		if (sscreen->b.debug_flags & DBG(NIR))
+		if (sscreen->debug_flags & DBG(NIR))
 			return 140; /* no geometry and tessellation shaders yet */
 		if (si_have_tgsi_compute(sscreen))
 			return 450;
 		return 420;
 
 	case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
-		return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
+		return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 
 	case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 	case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 	case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 		/* SI doesn't support unaligned loads.
 		 * CIK needs DRM 2.50.0 on radeon. */
-		return sscreen->b.chip_class == SI ||
-		       (sscreen->b.info.drm_major == 2 &&
-			sscreen->b.info.drm_minor < 50);
+		return sscreen->info.chip_class == SI ||
+		       (sscreen->info.drm_major == 2 &&
+			sscreen->info.drm_minor < 50);
 
 	case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 		/* TODO: GFX9 hangs. */
-		if (sscreen->b.chip_class >= GFX9)
+		if (sscreen->info.chip_class >= GFX9)
 			return 0;
 		/* Disable on SI due to VM faults in CP DMA. Enable once these
 		 * faults are mitigated in software.
 		 */
-		if (sscreen->b.chip_class >= CIK &&
-		    sscreen->b.info.drm_major == 3 &&
-		    sscreen->b.info.drm_minor >= 13)
+		if (sscreen->info.chip_class >= CIK &&
+		    sscreen->info.drm_major == 3 &&
+		    sscreen->info.drm_minor >= 13)
 			return RADEON_SPARSE_PAGE_SIZE;
 		return 0;
 
 	/* Unsupported features. */
 	case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 	case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 	case PIPE_CAP_USER_VERTEX_BUFFERS:
 	case PIPE_CAP_FAKE_SW_MSAA:
 	case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
@@ -270,35 +270,35 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 	case PIPE_CAP_TGSI_FS_FBFETCH:
 	case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 	case PIPE_CAP_UMA:
 	case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 	case PIPE_CAP_POST_DEPTH_COVERAGE:
 	case PIPE_CAP_TILE_RASTER_ORDER:
 	case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 		return 0;
 
 	case PIPE_CAP_NATIVE_FENCE_FD:
-		return sscreen->b.info.has_sync_file;
+		return sscreen->info.has_sync_file;
 
 	case PIPE_CAP_QUERY_BUFFER_OBJECT:
 		return si_have_tgsi_compute(sscreen);
 
 	case PIPE_CAP_DRAW_PARAMETERS:
 	case PIPE_CAP_MULTI_DRAW_INDIRECT:
 	case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 		return sscreen->has_draw_indirect_multi;
 
 	case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 		return 30;
 
 	case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
-		return sscreen->b.chip_class <= VI ?
+		return sscreen->info.chip_class <= VI ?
 			PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 
 	/* Stream output. */
 	case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 	case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 		return 32*4;
 
 	/* Geometry shader output. */
 	case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 		return 1024;
@@ -333,31 +333,31 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 	case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 	case PIPE_CAP_MAX_TEXEL_OFFSET:
 		return 31;
 
 	case PIPE_CAP_ENDIANNESS:
 		return PIPE_ENDIAN_LITTLE;
 
 	case PIPE_CAP_VENDOR_ID:
 		return ATI_VENDOR_ID;
 	case PIPE_CAP_DEVICE_ID:
-		return sscreen->b.info.pci_id;
+		return sscreen->info.pci_id;
 	case PIPE_CAP_VIDEO_MEMORY:
-		return sscreen->b.info.vram_size >> 20;
+		return sscreen->info.vram_size >> 20;
 	case PIPE_CAP_PCI_GROUP:
-		return sscreen->b.info.pci_domain;
+		return sscreen->info.pci_domain;
 	case PIPE_CAP_PCI_BUS:
-		return sscreen->b.info.pci_bus;
+		return sscreen->info.pci_bus;
 	case PIPE_CAP_PCI_DEVICE:
-		return sscreen->b.info.pci_dev;
+		return sscreen->info.pci_dev;
 	case PIPE_CAP_PCI_FUNCTION:
-		return sscreen->b.info.pci_func;
+		return sscreen->info.pci_func;
 	}
 	return 0;
 }
 
 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 {
 	switch (param) {
 	case PIPE_CAPF_MAX_LINE_WIDTH:
 	case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 	case PIPE_CAPF_MAX_POINT_WIDTH:
@@ -443,21 +443,21 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
 	case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 	case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 		return SI_NUM_SAMPLERS;
 	case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 		return SI_NUM_SHADER_BUFFERS;
 	case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 		return SI_NUM_IMAGES;
 	case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 		return 32;
 	case PIPE_SHADER_CAP_PREFERRED_IR:
-		if (sscreen->b.debug_flags & DBG(NIR) &&
+		if (sscreen->debug_flags & DBG(NIR) &&
 		    (shader == PIPE_SHADER_VERTEX ||
 		     shader == PIPE_SHADER_FRAGMENT))
 			return PIPE_SHADER_IR_NIR;
 		return PIPE_SHADER_IR_TGSI;
 	case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 		return 4;
 
 	/* Supported boolean features. */
 	case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 	case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
@@ -531,28 +531,28 @@ si_get_compiler_options(struct pipe_screen *screen,
 
 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 {
 	ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 }
 
 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 {
 	struct si_screen *sscreen = (struct si_screen *)pscreen;
 
-	ac_compute_device_uuid(&sscreen->b.info, uuid, PIPE_UUID_SIZE);
+	ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 }
 
 static const char* si_get_name(struct pipe_screen *pscreen)
 {
 	struct si_screen *sscreen = (struct si_screen*)pscreen;
 
-	return sscreen->b.renderer_string;
+	return sscreen->renderer_string;
 }
 
 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 					enum pipe_video_profile profile,
 					enum pipe_video_entrypoint entrypoint,
 					enum pipe_video_cap param)
 {
 	switch (param) {
 	case PIPE_VIDEO_CAP_SUPPORTED:
 		return vl_profile_supported(screen, profile, entrypoint);
@@ -581,85 +581,85 @@ static int si_get_video_param(struct pipe_screen *screen,
 			      enum pipe_video_entrypoint entrypoint,
 			      enum pipe_video_cap param)
 {
 	struct si_screen *sscreen = (struct si_screen *)screen;
 	enum pipe_video_format codec = u_reduce_video_profile(profile);
 
 	if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 		switch (param) {
 		case PIPE_VIDEO_CAP_SUPPORTED:
 			return codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
-				(si_vce_is_fw_version_supported(&sscreen->b) ||
-				sscreen->b.family == CHIP_RAVEN);
+				(si_vce_is_fw_version_supported(sscreen) ||
+				sscreen->info.family == CHIP_RAVEN);
 		case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 			return 1;
 		case PIPE_VIDEO_CAP_MAX_WIDTH:
-			return (sscreen->b.family < CHIP_TONGA) ? 2048 : 4096;
+			return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 		case PIPE_VIDEO_CAP_MAX_HEIGHT:
-			return (sscreen->b.family < CHIP_TONGA) ? 1152 : 2304;
+			return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 		case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 			return PIPE_FORMAT_NV12;
 		case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 			return false;
 		case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 			return false;
 		case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 			return true;
 		case PIPE_VIDEO_CAP_STACKED_FRAMES:
-			return (sscreen->b.family < CHIP_TONGA) ? 1 : 2;
+			return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 		default:
 			return 0;
 		}
 	}
 
 	switch (param) {
 	case PIPE_VIDEO_CAP_SUPPORTED:
 		switch (codec) {
 		case PIPE_VIDEO_FORMAT_MPEG12:
 			return profile != PIPE_VIDEO_PROFILE_MPEG1;
 		case PIPE_VIDEO_FORMAT_MPEG4:
 			return 1;
 		case PIPE_VIDEO_FORMAT_MPEG4_AVC:
-			if ((sscreen->b.family == CHIP_POLARIS10 ||
-			     sscreen->b.family == CHIP_POLARIS11) &&
-			    sscreen->b.info.uvd_fw_version < UVD_FW_1_66_16 ) {
+			if ((sscreen->info.family == CHIP_POLARIS10 ||
+			     sscreen->info.family == CHIP_POLARIS11) &&
+			    sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 				RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 				return false;
 			}
 			return true;
 		case PIPE_VIDEO_FORMAT_VC1:
 			return true;
 		case PIPE_VIDEO_FORMAT_HEVC:
 			/* Carrizo only supports HEVC Main */
-			if (sscreen->b.family >= CHIP_STONEY)
+			if (sscreen->info.family >= CHIP_STONEY)
 				return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 					profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
-			else if (sscreen->b.family >= CHIP_CARRIZO)
+			else if (sscreen->info.family >= CHIP_CARRIZO)
 				return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 			return false;
 		case PIPE_VIDEO_FORMAT_JPEG:
-			if (sscreen->b.family < CHIP_CARRIZO || sscreen->b.family >= CHIP_VEGA10)
+			if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 				return false;
-			if (!(sscreen->b.info.drm_major == 3 && sscreen->b.info.drm_minor >= 19)) {
+			if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
 				RVID_ERR("No MJPEG support for the kernel version\n");
 				return false;
 			}
 			return true;
 		default:
 			return false;
 		}
 	case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 		return 1;
 	case PIPE_VIDEO_CAP_MAX_WIDTH:
-		return (sscreen->b.family < CHIP_TONGA) ? 2048 : 4096;
+		return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 	case PIPE_VIDEO_CAP_MAX_HEIGHT:
-		return (sscreen->b.family < CHIP_TONGA) ? 1152 : 4096;
+		return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 	case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 		if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 			return PIPE_FORMAT_P016;
 		else
 			return PIPE_FORMAT_NV12;
 
 	case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 	case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 		enum pipe_video_format format = u_reduce_video_profile(profile);
 
@@ -684,21 +684,21 @@ static int si_get_video_param(struct pipe_screen *screen,
 			return 5;
 		case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 			return 1;
 		case PIPE_VIDEO_PROFILE_VC1_MAIN:
 			return 2;
 		case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 			return 4;
 		case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 		case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 		case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
-			return (sscreen->b.family < CHIP_TONGA) ? 41 : 52;
+			return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 		case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 		case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 			return 186;
 		default:
 			return 0;
 		}
 	default:
 		return 0;
 	}
 }
@@ -720,21 +720,21 @@ static boolean si_vid_is_format_supported(struct pipe_screen *screen,
 	return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 }
 
 static unsigned get_max_threads_per_block(struct si_screen *screen,
 					  enum pipe_shader_ir ir_type)
 {
 	if (ir_type != PIPE_SHADER_IR_TGSI)
 		return 256;
 
 	/* Only 16 waves per thread-group on gfx9. */
-	if (screen->b.chip_class >= GFX9)
+	if (screen->info.chip_class >= GFX9)
 		return 1024;
 
 	/* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 	 * round number.
 	 */
 	return 2048;
 }
 
 static int si_get_compute_param(struct pipe_screen *screen,
 				enum pipe_shader_ir ir_type,
@@ -747,21 +747,21 @@ static int si_get_compute_param(struct pipe_screen *screen,
 	switch (param) {
 	case PIPE_COMPUTE_CAP_IR_TARGET: {
 		const char *gpu;
 		const char *triple;
 
 		if (HAVE_LLVM < 0x0400)
 			triple = "amdgcn--";
 		else
 			triple = "amdgcn-mesa-mesa3d";
 
-		gpu = ac_get_llvm_processor_name(sscreen->b.family);
+		gpu = ac_get_llvm_processor_name(sscreen->info.family);
 		if (ret) {
 			sprintf(ret, "%s-%s", gpu, triple);
 		}
 		/* +2 for dash and terminating NIL byte */
 		return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 	}
 	case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 		if (ret) {
 			uint64_t *grid_dimension = ret;
 			grid_dimension[0] = 3;
@@ -809,22 +809,22 @@ static int si_get_compute_param(struct pipe_screen *screen,
 				PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 				&max_mem_alloc_size);
 
 			/* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 			 * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 			 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 			 * make sure we never report more than
 			 * 4 * MAX_MEM_ALLOC_SIZE.
 			 */
 			*max_global_size = MIN2(4 * max_mem_alloc_size,
-						MAX2(sscreen->b.info.gart_size,
-						     sscreen->b.info.vram_size));
+						MAX2(sscreen->info.gart_size,
+						     sscreen->info.vram_size));
 		}
 		return sizeof(uint64_t);
 
 	case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 		if (ret) {
 			uint64_t *max_local_size = ret;
 			/* Value reported by the closed source driver. */
 			*max_local_size = 32768;
 		}
 		return sizeof(uint64_t);
@@ -834,35 +834,35 @@ static int si_get_compute_param(struct pipe_screen *screen,
 			uint64_t *max_input_size = ret;
 			/* Value reported by the closed source driver. */
 			*max_input_size = 1024;
 		}
 		return sizeof(uint64_t);
 
 	case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 		if (ret) {
 			uint64_t *max_mem_alloc_size = ret;
 
-			*max_mem_alloc_size = sscreen->b.info.max_alloc_size;
+			*max_mem_alloc_size = sscreen->info.max_alloc_size;
 		}
 		return sizeof(uint64_t);
 
 	case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 		if (ret) {
 			uint32_t *max_clock_frequency = ret;
-			*max_clock_frequency = sscreen->b.info.max_shader_clock;
+			*max_clock_frequency = sscreen->info.max_shader_clock;
 		}
 		return sizeof(uint32_t);
 
 	case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 		if (ret) {
 			uint32_t *max_compute_units = ret;
-			*max_compute_units = sscreen->b.info.num_good_compute_units;
+			*max_compute_units = sscreen->info.num_good_compute_units;
 		}
 		return sizeof(uint32_t);
 
 	case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 		if (ret) {
 			uint32_t *images_supported = ret;
 			*images_supported = 0;
 		}
 		return sizeof(uint32_t);
 	case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
@@ -885,33 +885,33 @@ static int si_get_compute_param(struct pipe_screen *screen,
 	}
 
         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
         return 0;
 }
 
 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 {
 	struct si_screen *sscreen = (struct si_screen*)screen;
 
-	return 1000000 * sscreen->b.ws->query_value(sscreen->b.ws, RADEON_TIMESTAMP) /
-			sscreen->b.info.clock_crystal_freq;
+	return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
+			sscreen->info.clock_crystal_freq;
 }
 
 static void si_query_memory_info(struct pipe_screen *screen,
 				 struct pipe_memory_info *info)
 {
 	struct si_screen *sscreen = (struct si_screen*)screen;
-	struct radeon_winsys *ws = sscreen->b.ws;
+	struct radeon_winsys *ws = sscreen->ws;
 	unsigned vram_usage, gtt_usage;
 
-	info->total_device_memory = sscreen->b.info.vram_size / 1024;
-	info->total_staging_memory = sscreen->b.info.gart_size / 1024;
+	info->total_device_memory = sscreen->info.vram_size / 1024;
+	info->total_staging_memory = sscreen->info.gart_size / 1024;
 
 	/* The real TTM memory usage is somewhat random, because:
 	 *
 	 * 1) TTM delays freeing memory, because it can only free it after
 	 *    fences expire.
 	 *
 	 * 2) The memory usage can be really low if big VRAM evictions are
 	 *    taking place, but the real usage is well above the size of VRAM.
 	 *
 	 * Instead, return statistics of this process.
@@ -922,38 +922,38 @@ static void si_query_memory_info(struct pipe_screen *screen,
 	info->avail_device_memory =
 		vram_usage <= info->total_device_memory ?
 				info->total_device_memory - vram_usage : 0;
 	info->avail_staging_memory =
 		gtt_usage <= info->total_staging_memory ?
 				info->total_staging_memory - gtt_usage : 0;
 
 	info->device_memory_evicted =
 		ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 
-	if (sscreen->b.info.drm_major == 3 && sscreen->b.info.drm_minor >= 4)
+	if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
 		info->nr_device_memory_evictions =
 			ws->query_value(ws, RADEON_NUM_EVICTIONS);
 	else
 		/* Just return the number of evicted 64KB pages. */
 		info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 }
 
 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 {
 	struct si_screen *sscreen = (struct si_screen*)pscreen;
 
-	return sscreen->b.disk_shader_cache;
+	return sscreen->disk_shader_cache;
 }
 
 static void si_init_renderer_string(struct si_screen *sscreen)
 {
-	struct radeon_winsys *ws = sscreen->b.ws;
+	struct radeon_winsys *ws = sscreen->ws;
 	char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
 	struct utsname uname_data;
 
 	const char *chip_name = si_get_marketing_name(ws);
 
 	if (chip_name)
 		snprintf(family_name, sizeof(family_name), "%s / ",
 			 si_get_family_name(sscreen) + 4);
 	else
 		chip_name = si_get_family_name(sscreen);
@@ -961,43 +961,43 @@ static void si_init_renderer_string(struct si_screen *sscreen)
 	if (uname(&uname_data) == 0)
 		snprintf(kernel_version, sizeof(kernel_version),
 			 " / %s", uname_data.release);
 
 	if (HAVE_LLVM > 0) {
 		snprintf(llvm_string, sizeof(llvm_string),
 			 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
 			 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
 	}
 
-	snprintf(sscreen->b.renderer_string, sizeof(sscreen->b.renderer_string),
+	snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 		 "%s (%sDRM %i.%i.%i%s%s)",
-		 chip_name, family_name, sscreen->b.info.drm_major,
-		 sscreen->b.info.drm_minor, sscreen->b.info.drm_patchlevel,
+		 chip_name, family_name, sscreen->info.drm_major,
+		 sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 		 kernel_version, llvm_string);
 }
 
 void si_init_screen_get_functions(struct si_screen *sscreen)
 {
-	sscreen->b.b.get_name = si_get_name;
-	sscreen->b.b.get_vendor = si_get_vendor;
-	sscreen->b.b.get_device_vendor = si_get_device_vendor;
-	sscreen->b.b.get_param = si_get_param;
-	sscreen->b.b.get_paramf = si_get_paramf;
-	sscreen->b.b.get_compute_param = si_get_compute_param;
-	sscreen->b.b.get_timestamp = si_get_timestamp;
-	sscreen->b.b.get_shader_param = si_get_shader_param;
-	sscreen->b.b.get_compiler_options = si_get_compiler_options;
-	sscreen->b.b.get_device_uuid = si_get_device_uuid;
-	sscreen->b.b.get_driver_uuid = si_get_driver_uuid;
-	sscreen->b.b.query_memory_info = si_query_memory_info;
-	sscreen->b.b.get_disk_shader_cache = si_get_disk_shader_cache;
-
-	if (sscreen->b.info.has_hw_decode) {
-		sscreen->b.b.get_video_param = si_get_video_param;
-		sscreen->b.b.is_video_format_supported = si_vid_is_format_supported;
+	sscreen->b.get_name = si_get_name;
+	sscreen->b.get_vendor = si_get_vendor;
+	sscreen->b.get_device_vendor = si_get_device_vendor;
+	sscreen->b.get_param = si_get_param;
+	sscreen->b.get_paramf = si_get_paramf;
+	sscreen->b.get_compute_param = si_get_compute_param;
+	sscreen->b.get_timestamp = si_get_timestamp;
+	sscreen->b.get_shader_param = si_get_shader_param;
+	sscreen->b.get_compiler_options = si_get_compiler_options;
+	sscreen->b.get_device_uuid = si_get_device_uuid;
+	sscreen->b.get_driver_uuid = si_get_driver_uuid;
+	sscreen->b.query_memory_info = si_query_memory_info;
+	sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
+
+	if (sscreen->info.has_hw_decode) {
+		sscreen->b.get_video_param = si_get_video_param;
+		sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 	} else {
-		sscreen->b.b.get_video_param = si_get_video_param_no_decode;
-		sscreen->b.b.is_video_format_supported = vl_video_buffer_is_format_supported;
+		sscreen->b.get_video_param = si_get_video_param_no_decode;
+		sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 	}
 
 	si_init_renderer_string(sscreen);
 }
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c
index 4e94c47..d46c109 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -75,21 +75,21 @@ void si_context_gfx_flush(void *context, unsigned flags,
 
 	if (ctx->gfx_flush_in_progress)
 		return;
 
 	if (!radeon_emitted(cs, ctx->b.initial_gfx_cs_size))
 		return;
 
 	if (si_check_device_reset(&ctx->b))
 		return;
 
-	if (ctx->screen->b.debug_flags & DBG(CHECK_VM))
+	if (ctx->screen->debug_flags & DBG(CHECK_VM))
 		flags &= ~RADEON_FLUSH_ASYNC;
 
 	/* If the state tracker is flushing the GFX IB, r600_flush_from_st is
 	 * responsible for flushing the DMA IB and merging the fences from both.
 	 * This code is only needed when the driver flushes the GFX IB
 	 * internally, and it never asks for a fence handle.
 	 */
 	if (radeon_emitted(ctx->b.dma.cs, 0)) {
 		assert(fence == NULL); /* internal flushes only */
 		ctx->b.dma.flush(ctx, flags, NULL);
@@ -129,21 +129,21 @@ void si_context_gfx_flush(void *context, unsigned flags,
 	/* Flush the CS. */
 	ws->cs_flush(cs, flags, &ctx->b.last_gfx_fence);
 	if (fence)
 		ws->fence_reference(fence, ctx->b.last_gfx_fence);
 
 	/* This must be after cs_flush returns, since the context's API
 	 * thread can concurrently read this value in si_fence_finish. */
 	ctx->b.num_gfx_cs_flushes++;
 
 	/* Check VM faults if needed. */
-	if (ctx->screen->b.debug_flags & DBG(CHECK_VM)) {
+	if (ctx->screen->debug_flags & DBG(CHECK_VM)) {
 		/* Use conservative timeout 800ms, after which we won't wait any
 		 * longer and assume the GPU is hung.
 		 */
 		ctx->b.ws->fence_wait(ctx->b.ws, ctx->b.last_gfx_fence, 800*1000*1000);
 
 		si_check_vm_faults(&ctx->b, &ctx->current_saved_cs->gfx, RING_GFX);
 	}
 
 	if (ctx->current_saved_cs)
 		si_saved_cs_reference(&ctx->current_saved_cs, NULL);
diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c b/src/gallium/drivers/radeonsi/si_perfcounter.c
index b742967..1cf004d 100644
--- a/src/gallium/drivers/radeonsi/si_perfcounter.c
+++ b/src/gallium/drivers/radeonsi/si_perfcounter.c
@@ -663,64 +663,64 @@ static void si_pc_emit_read(struct r600_common_context *ctx,
 					COPY_DATA_COUNT_SEL);
 			radeon_emit(cs, 0); /* immediate */
 			radeon_emit(cs, 0);
 			radeon_emit(cs, va);
 			radeon_emit(cs, va >> 32);
 			va += sizeof(uint64_t);
 		}
 	}
 }
 
-static void si_pc_cleanup(struct r600_common_screen *rscreen)
+static void si_pc_cleanup(struct si_screen *sscreen)
 {
-	si_perfcounters_do_destroy(rscreen->perfcounters);
-	rscreen->perfcounters = NULL;
+	si_perfcounters_do_destroy(sscreen->perfcounters);
+	sscreen->perfcounters = NULL;
 }
 
 void si_init_perfcounters(struct si_screen *screen)
 {
 	struct r600_perfcounters *pc;
 	struct si_pc_block *blocks;
 	unsigned num_blocks;
 	unsigned i;
 
-	switch (screen->b.chip_class) {
+	switch (screen->info.chip_class) {
 	case CIK:
 		blocks = groups_CIK;
 		num_blocks = ARRAY_SIZE(groups_CIK);
 		break;
 	case VI:
 		blocks = groups_VI;
 		num_blocks = ARRAY_SIZE(groups_VI);
 		break;
 	case GFX9:
 		blocks = groups_gfx9;
 		num_blocks = ARRAY_SIZE(groups_gfx9);
 		break;
 	case SI:
 	default:
 		return; /* not implemented */
 	}
 
-	if (screen->b.info.max_sh_per_se != 1) {
+	if (screen->info.max_sh_per_se != 1) {
 		/* This should not happen on non-SI chips. */
 		fprintf(stderr, "si_init_perfcounters: max_sh_per_se = %d not "
 			"supported (inaccurate performance counters)\n",
-			screen->b.info.max_sh_per_se);
+			screen->info.max_sh_per_se);
 	}
 
 	pc = CALLOC_STRUCT(r600_perfcounters);
 	if (!pc)
 		return;
 
 	pc->num_start_cs_dwords = 14;
-	pc->num_stop_cs_dwords = 14 + si_gfx_write_fence_dwords(&screen->b);
+	pc->num_stop_cs_dwords = 14 + si_gfx_write_fence_dwords(screen);
 	pc->num_instance_cs_dwords = 3;
 	pc->num_shaders_cs_dwords = 4;
 
 	pc->num_shader_types = ARRAY_SIZE(si_pc_shader_type_bits);
 	pc->shader_type_suffixes = si_pc_shader_type_suffixes;
 	pc->shader_type_bits = si_pc_shader_type_bits;
 
 	pc->get_size = si_pc_get_size;
 	pc->emit_instance = si_pc_emit_instance;
 	pc->emit_shaders = si_pc_emit_shaders;
@@ -731,29 +731,29 @@ void si_init_perfcounters(struct si_screen *screen)
 	pc->cleanup = si_pc_cleanup;
 
 	if (!si_perfcounters_init(pc, num_blocks))
 		goto error;
 
 	for (i = 0; i < num_blocks; ++i) {
 		struct si_pc_block *block = &blocks[i];
 		unsigned instances = block->instances;
 
 		if (!strcmp(block->b->name, "IA")) {
-			if (screen->b.info.max_se > 2)
+			if (screen->info.max_se > 2)
 				instances = 2;
 		}
 
-		si_perfcounters_add_block(&screen->b, pc,
+		si_perfcounters_add_block(screen, pc,
 					    block->b->name,
 					    block->b->flags,
 					    block->b->num_counters,
 					    block->selectors,
 					    instances,
 					    block);
 	}
 
-	screen->b.perfcounters = pc;
+	screen->perfcounters = pc;
 	return;
 
 error:
 	si_perfcounters_do_destroy(pc);
 }
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 6c4e183..5d7837d 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -200,26 +200,26 @@ static void si_emit_string_marker(struct pipe_context *ctx,
 	dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
 
 	if (sctx->b.log)
 		u_log_printf(sctx->b.log, "\nString marker: %*s\n", len, string);
 }
 
 static LLVMTargetMachineRef
 si_create_llvm_target_machine(struct si_screen *sscreen)
 {
 	enum ac_target_machine_options tm_options =
-		(sscreen->b.debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
-		(sscreen->b.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
-		(sscreen->b.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
+		(sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
+		(sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
+		(sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
 		(!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0);
 
-	return ac_create_target_machine(sscreen->b.family, tm_options);
+	return ac_create_target_machine(sscreen->info.family, tm_options);
 }
 
 static void si_set_debug_callback(struct pipe_context *ctx,
 				  const struct pipe_debug_callback *cb)
 {
 	struct si_context *sctx = (struct si_context *)ctx;
 	struct si_screen *screen = sctx->screen;
 
 	util_queue_finish(&screen->shader_compiler_queue);
 	util_queue_finish(&screen->shader_compiler_queue_low_priority);
@@ -238,55 +238,55 @@ static void si_set_log_context(struct pipe_context *ctx,
 
 	if (log)
 		u_log_add_auto_logger(log, si_auto_log_cs, sctx);
 }
 
 static struct pipe_context *si_create_context(struct pipe_screen *screen,
                                               unsigned flags)
 {
 	struct si_context *sctx = CALLOC_STRUCT(si_context);
 	struct si_screen* sscreen = (struct si_screen *)screen;
-	struct radeon_winsys *ws = sscreen->b.ws;
+	struct radeon_winsys *ws = sscreen->ws;
 	int shader, i;
 
 	if (!sctx)
 		return NULL;
 
 	if (flags & PIPE_CONTEXT_DEBUG)
 		sscreen->record_llvm_ir = true; /* racy but not critical */
 
 	sctx->b.b.screen = screen; /* this must be set first */
 	sctx->b.b.priv = NULL;
 	sctx->b.b.destroy = si_destroy_context;
 	sctx->b.b.emit_string_marker = si_emit_string_marker;
 	sctx->b.b.set_debug_callback = si_set_debug_callback;
 	sctx->b.b.set_log_context = si_set_log_context;
 	sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 	sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 	sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 
-	if (!si_common_context_init(&sctx->b, &sscreen->b, flags))
+	if (!si_common_context_init(&sctx->b, sscreen, flags))
 		goto fail;
 
-	if (sscreen->b.info.drm_major == 3)
+	if (sscreen->info.drm_major == 3)
 		sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 
 	si_init_buffer_functions(sctx);
 	si_init_clear_functions(sctx);
 	si_init_blit_functions(sctx);
 	si_init_compute_functions(sctx);
 	si_init_cp_dma_functions(sctx);
 	si_init_debug_functions(sctx);
 	si_init_msaa_functions(sctx);
 	si_init_streamout_functions(sctx);
 
-	if (sscreen->b.info.has_hw_decode) {
+	if (sscreen->info.has_hw_decode) {
 		sctx->b.b.create_video_codec = si_uvd_create_decoder;
 		sctx->b.b.create_video_buffer = si_video_buffer_create;
 	} else {
 		sctx->b.b.create_video_codec = vl_create_decoder;
 		sctx->b.b.create_video_buffer = vl_video_buffer_create;
 	}
 
 	sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 				       si_context_gfx_flush, sctx);
 	sctx->b.gfx.flush = si_context_gfx_flush;
@@ -315,21 +315,21 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
 	si_init_state_functions(sctx);
 	si_init_shader_functions(sctx);
 	si_init_viewport_functions(sctx);
 	si_init_ia_multi_vgt_param_table(sctx);
 
 	if (sctx->b.chip_class >= CIK)
 		cik_init_sdma_functions(sctx);
 	else
 		si_init_dma_functions(sctx);
 
-	if (sscreen->b.debug_flags & DBG(FORCE_DMA))
+	if (sscreen->debug_flags & DBG(FORCE_DMA))
 		sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 
 	sctx->blitter = util_blitter_create(&sctx->b.b);
 	if (sctx->blitter == NULL)
 		goto fail;
 	sctx->blitter->draw_rectangle = si_draw_rectangle;
 	sctx->blitter->skip_viewport_restore = true;
 
 	sctx->sample_mask.sample_mask = 0xffff;
 
@@ -353,21 +353,21 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
 		radeon_emit(cs, sctx->wait_mem_number);
 	}
 
 	/* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
 	 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
 	if (sctx->b.chip_class == CIK) {
 		sctx->null_const_buf.buffer =
 			si_aligned_buffer_create(screen,
 						   R600_RESOURCE_FLAG_UNMAPPABLE,
 						   PIPE_USAGE_DEFAULT, 16,
-						   sctx->screen->b.info.tcc_cache_line_size);
+						   sctx->screen->info.tcc_cache_line_size);
 		if (!sctx->null_const_buf.buffer)
 			goto fail;
 		sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 
 		for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 			for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 				sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 							      &sctx->null_const_buf);
 			}
 		}
@@ -399,21 +399,21 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
 	 * We can decrease the constant to decrease the scratch buffer size.
 	 *
 	 * sctx->scratch_waves must be >= the maximum posible size of
 	 * 1 threadgroup, so that the hw doesn't hang from being unable
 	 * to start any.
 	 *
 	 * The recommended value is 4 per CU at most. Higher numbers don't
 	 * bring much benefit, but they still occupy chip resources (think
 	 * async compute). I've seen ~2% performance difference between 4 and 32.
 	 */
-	sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
+	sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
 				   max_threads_per_block / 64);
 
 	sctx->tm = si_create_llvm_target_machine(sscreen);
 
 	/* Bindless handles. */
 	sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 						    _mesa_key_pointer_equal);
 	sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 						    _mesa_key_pointer_equal);
 
@@ -429,62 +429,62 @@ fail:
 	si_destroy_context(&sctx->b.b);
 	return NULL;
 }
 
 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
 						   void *priv, unsigned flags)
 {
 	struct si_screen *sscreen = (struct si_screen *)screen;
 	struct pipe_context *ctx;
 
-	if (sscreen->b.debug_flags & DBG(CHECK_VM))
+	if (sscreen->debug_flags & DBG(CHECK_VM))
 		flags |= PIPE_CONTEXT_DEBUG;
 
 	ctx = si_create_context(screen, flags);
 
 	if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
 		return ctx;
 
 	/* Clover (compute-only) is unsupported. */
 	if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
 		return ctx;
 
 	/* When shaders are logged to stderr, asynchronous compilation is
 	 * disabled too. */
-	if (sscreen->b.debug_flags & DBG_ALL_SHADERS)
+	if (sscreen->debug_flags & DBG_ALL_SHADERS)
 		return ctx;
 
 	/* Use asynchronous flushes only on amdgpu, since the radeon
 	 * implementation for fence_server_sync is incomplete. */
-	return threaded_context_create(ctx, &sscreen->b.pool_transfers,
+	return threaded_context_create(ctx, &sscreen->pool_transfers,
 				       si_replace_buffer_storage,
-				       sscreen->b.info.drm_major >= 3 ? si_create_fence : NULL,
+				       sscreen->info.drm_major >= 3 ? si_create_fence : NULL,
 				       &((struct si_context*)ctx)->b.tc);
 }
 
 /*
  * pipe_screen
  */
 
 static void si_destroy_screen(struct pipe_screen* pscreen)
 {
 	struct si_screen *sscreen = (struct si_screen *)pscreen;
 	struct si_shader_part *parts[] = {
 		sscreen->vs_prologs,
 		sscreen->tcs_epilogs,
 		sscreen->gs_prologs,
 		sscreen->ps_prologs,
 		sscreen->ps_epilogs
 	};
 	unsigned i;
 
-	if (!sscreen->b.ws->unref(sscreen->b.ws))
+	if (!sscreen->ws->unref(sscreen->ws))
 		return;
 
 	util_queue_destroy(&sscreen->shader_compiler_queue);
 	util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
 
 	for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
 		if (sscreen->tm[i])
 			LLVMDisposeTargetMachine(sscreen->tm[i]);
 
 	for (i = 0; i < ARRAY_SIZE(sscreen->tm_low_priority); i++)
@@ -497,41 +497,41 @@ static void si_destroy_screen(struct pipe_screen* pscreen)
 			struct si_shader_part *part = parts[i];
 
 			parts[i] = part->next;
 			ac_shader_binary_clean(&part->binary);
 			FREE(part);
 		}
 	}
 	mtx_destroy(&sscreen->shader_parts_mutex);
 	si_destroy_shader_cache(sscreen);
 
-	si_perfcounters_destroy(&sscreen->b);
-	si_gpu_load_kill_thread(&sscreen->b);
+	si_perfcounters_destroy(sscreen);
+	si_gpu_load_kill_thread(sscreen);
 
-	mtx_destroy(&sscreen->b.gpu_load_mutex);
-	mtx_destroy(&sscreen->b.aux_context_lock);
-	sscreen->b.aux_context->destroy(sscreen->b.aux_context);
+	mtx_destroy(&sscreen->gpu_load_mutex);
+	mtx_destroy(&sscreen->aux_context_lock);
+	sscreen->aux_context->destroy(sscreen->aux_context);
 
-	slab_destroy_parent(&sscreen->b.pool_transfers);
+	slab_destroy_parent(&sscreen->pool_transfers);
 
-	disk_cache_destroy(sscreen->b.disk_shader_cache);
-	sscreen->b.ws->destroy(sscreen->b.ws);
+	disk_cache_destroy(sscreen->disk_shader_cache);
+	sscreen->ws->destroy(sscreen->ws);
 	FREE(sscreen);
 }
 
 static bool si_init_gs_info(struct si_screen *sscreen)
 {
 	/* gs_table_depth is not used by GFX9 */
-	if (sscreen->b.chip_class >= GFX9)
+	if (sscreen->info.chip_class >= GFX9)
 		return true;
 
-	switch (sscreen->b.family) {
+	switch (sscreen->info.family) {
 	case CHIP_OLAND:
 	case CHIP_HAINAN:
 	case CHIP_KAVERI:
 	case CHIP_KABINI:
 	case CHIP_MULLINS:
 	case CHIP_ICELAND:
 	case CHIP_CARRIZO:
 	case CHIP_STONEY:
 		sscreen->gs_table_depth = 16;
 		return true;
@@ -556,166 +556,164 @@ static void si_handle_env_var_force_family(struct si_screen *sscreen)
 {
 	const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
 	unsigned i;
 
 	if (!family)
 		return;
 
 	for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
 		if (!strcmp(family, ac_get_llvm_processor_name(i))) {
 			/* Override family and chip_class. */
-			sscreen->b.family = sscreen->b.info.family = i;
+			sscreen->info.family = i;
 
 			if (i >= CHIP_VEGA10)
-				sscreen->b.chip_class = sscreen->b.info.chip_class = GFX9;
+				sscreen->info.chip_class = GFX9;
 			else if (i >= CHIP_TONGA)
-				sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
+				sscreen->info.chip_class = VI;
 			else if (i >= CHIP_BONAIRE)
-				sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
+				sscreen->info.chip_class = CIK;
 			else
-				sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
+				sscreen->info.chip_class = SI;
 
 			/* Don't submit any IBs. */
 			setenv("RADEON_NOOP", "1", 1);
 			return;
 		}
 	}
 
 	fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
 	exit(1);
 }
 
 static void si_test_vmfault(struct si_screen *sscreen)
 {
-	struct pipe_context *ctx = sscreen->b.aux_context;
+	struct pipe_context *ctx = sscreen->aux_context;
 	struct si_context *sctx = (struct si_context *)ctx;
 	struct pipe_resource *buf =
-		pipe_buffer_create(&sscreen->b.b, 0, PIPE_USAGE_DEFAULT, 64);
+		pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
 
 	if (!buf) {
 		puts("Buffer allocation failed.");
 		exit(1);
 	}
 
 	r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
 
-	if (sscreen->b.debug_flags & DBG(TEST_VMFAULT_CP)) {
+	if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
 		si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
 		ctx->flush(ctx, NULL, 0);
 		puts("VM fault test: CP - done.");
 	}
-	if (sscreen->b.debug_flags & DBG(TEST_VMFAULT_SDMA)) {
+	if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
 		sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
 		ctx->flush(ctx, NULL, 0);
 		puts("VM fault test: SDMA - done.");
 	}
-	if (sscreen->b.debug_flags & DBG(TEST_VMFAULT_SHADER)) {
+	if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
 		util_test_constant_buffer(ctx, buf);
 		puts("VM fault test: Shader - done.");
 	}
 	exit(0);
 }
 
 static void si_disk_cache_create(struct si_screen *sscreen)
 {
 	/* Don't use the cache if shader dumping is enabled. */
-	if (sscreen->b.debug_flags & DBG_ALL_SHADERS)
+	if (sscreen->debug_flags & DBG_ALL_SHADERS)
 		return;
 
 	/* TODO: remove this once gallium supports a nir cache */
-	if (sscreen->b.debug_flags & DBG(NIR))
+	if (sscreen->debug_flags & DBG(NIR))
 		return;
 
 	uint32_t mesa_timestamp;
 	if (disk_cache_get_function_timestamp(si_disk_cache_create,
 					      &mesa_timestamp)) {
 		char *timestamp_str;
 		int res = -1;
 		uint32_t llvm_timestamp;
 
 		if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
 						      &llvm_timestamp)) {
 			res = asprintf(&timestamp_str, "%u_%u",
 				       mesa_timestamp, llvm_timestamp);
 		}
 
 		if (res != -1) {
 			/* These flags affect shader compilation. */
 			uint64_t shader_debug_flags =
-				sscreen->b.debug_flags &
+				sscreen->debug_flags &
 				(DBG(FS_CORRECT_DERIVS_AFTER_KILL) |
 				 DBG(SI_SCHED) |
 				 DBG(UNSAFE_MATH));
 
-			sscreen->b.disk_shader_cache =
+			sscreen->disk_shader_cache =
 				disk_cache_create(si_get_family_name(sscreen),
 						  timestamp_str,
 						  shader_debug_flags);
 			free(timestamp_str);
 		}
 	}
 }
 
 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
 					   const struct pipe_screen_config *config)
 {
 	struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 	unsigned num_threads, num_compiler_threads, num_compiler_threads_lowprio, i;
 
 	if (!sscreen) {
 		return NULL;
 	}
 
-	sscreen->b.ws = ws;
-	ws->query_info(ws, &sscreen->b.info);
+	sscreen->ws = ws;
+	ws->query_info(ws, &sscreen->info);
 
-	sscreen->b.family = sscreen->b.info.family;
-	sscreen->b.chip_class = sscreen->b.info.chip_class;
-	sscreen->b.debug_flags = debug_get_flags_option("R600_DEBUG",
+	sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
 							debug_options, 0);
 
 	/* Set functions first. */
-	sscreen->b.b.context_create = si_pipe_create_context;
-	sscreen->b.b.destroy = si_destroy_screen;
+	sscreen->b.context_create = si_pipe_create_context;
+	sscreen->b.destroy = si_destroy_screen;
 
 	si_init_screen_get_functions(sscreen);
 	si_init_screen_buffer_functions(sscreen);
 	si_init_screen_fence_functions(sscreen);
 	si_init_screen_state_functions(sscreen);
-	si_init_screen_texture_functions(&sscreen->b);
-	si_init_screen_query_functions(&sscreen->b);
+	si_init_screen_texture_functions(sscreen);
+	si_init_screen_query_functions(sscreen);
 
 	/* Set these flags in debug_flags early, so that the shader cache takes
 	 * them into account.
 	 */
 	if (driQueryOptionb(config->options,
 			    "glsl_correct_derivatives_after_discard"))
-		sscreen->b.debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
+		sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
 	if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
-		sscreen->b.debug_flags |= DBG(SI_SCHED);
+		sscreen->debug_flags |= DBG(SI_SCHED);
 
 
-	if (sscreen->b.debug_flags & DBG(INFO))
-		ac_print_gpu_info(&sscreen->b.info);
+	if (sscreen->debug_flags & DBG(INFO))
+		ac_print_gpu_info(&sscreen->info);
 
-	slab_create_parent(&sscreen->b.pool_transfers,
+	slab_create_parent(&sscreen->pool_transfers,
 			   sizeof(struct r600_transfer), 64);
 
-	sscreen->b.force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
-	if (sscreen->b.force_aniso >= 0) {
+	sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
+	if (sscreen->force_aniso >= 0) {
 		printf("radeonsi: Forcing anisotropy filter to %ix\n",
 		       /* round down to a power of two */
-		       1 << util_logbase2(sscreen->b.force_aniso));
+		       1 << util_logbase2(sscreen->force_aniso));
 	}
 
-	(void) mtx_init(&sscreen->b.aux_context_lock, mtx_plain);
-	(void) mtx_init(&sscreen->b.gpu_load_mutex, mtx_plain);
+	(void) mtx_init(&sscreen->aux_context_lock, mtx_plain);
+	(void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
 
 	if (!si_init_gs_info(sscreen) ||
 	    !si_init_shader_cache(sscreen)) {
 		FREE(sscreen);
 		return NULL;
 	}
 
 	si_disk_cache_create(sscreen);
 
 	/* Only enable as many threads as we have target machines, but at most
@@ -747,119 +745,119 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
 
 	si_handle_env_var_force_family(sscreen);
 
 	if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
 		si_init_perfcounters(sscreen);
 
 	/* Hawaii has a bug with offchip buffers > 256 that can be worked
 	 * around by setting 4K granularity.
 	 */
 	sscreen->tess_offchip_block_dw_size =
-		sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
+		sscreen->info.family == CHIP_HAWAII ? 4096 : 8192;
 
 	/* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
 	 * on SI. */
-	sscreen->has_clear_state = sscreen->b.chip_class >= CIK;
+	sscreen->has_clear_state = sscreen->info.chip_class >= CIK;
 
 	sscreen->has_distributed_tess =
-		sscreen->b.chip_class >= VI &&
-		sscreen->b.info.max_se >= 2;
+		sscreen->info.chip_class >= VI &&
+		sscreen->info.max_se >= 2;
 
 	sscreen->has_draw_indirect_multi =
-		(sscreen->b.family >= CHIP_POLARIS10) ||
-		(sscreen->b.chip_class == VI &&
-		 sscreen->b.info.pfp_fw_version >= 121 &&
-		 sscreen->b.info.me_fw_version >= 87) ||
-		(sscreen->b.chip_class == CIK &&
-		 sscreen->b.info.pfp_fw_version >= 211 &&
-		 sscreen->b.info.me_fw_version >= 173) ||
-		(sscreen->b.chip_class == SI &&
-		 sscreen->b.info.pfp_fw_version >= 79 &&
-		 sscreen->b.info.me_fw_version >= 142);
-
-	sscreen->has_out_of_order_rast = sscreen->b.chip_class >= VI &&
-					 sscreen->b.info.max_se >= 2 &&
-					 !(sscreen->b.debug_flags & DBG(NO_OUT_OF_ORDER));
+		(sscreen->info.family >= CHIP_POLARIS10) ||
+		(sscreen->info.chip_class == VI &&
+		 sscreen->info.pfp_fw_version >= 121 &&
+		 sscreen->info.me_fw_version >= 87) ||
+		(sscreen->info.chip_class == CIK &&
+		 sscreen->info.pfp_fw_version >= 211 &&
+		 sscreen->info.me_fw_version >= 173) ||
+		(sscreen->info.chip_class == SI &&
+		 sscreen->info.pfp_fw_version >= 79 &&
+		 sscreen->info.me_fw_version >= 142);
+
+	sscreen->has_out_of_order_rast = sscreen->info.chip_class >= VI &&
+					 sscreen->info.max_se >= 2 &&
+					 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
 	sscreen->assume_no_z_fights =
 		driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
 	sscreen->commutative_blend_add =
 		driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
 	sscreen->clear_db_cache_before_clear =
 		driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear");
-	sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
-					    sscreen->b.family <= CHIP_POLARIS12) ||
-					   sscreen->b.family == CHIP_VEGA10 ||
-					   sscreen->b.family == CHIP_RAVEN;
-	sscreen->has_ls_vgpr_init_bug = sscreen->b.family == CHIP_VEGA10 ||
-					sscreen->b.family == CHIP_RAVEN;
-
-	if (sscreen->b.debug_flags & DBG(DPBB)) {
+	sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
+					    sscreen->info.family <= CHIP_POLARIS12) ||
+					   sscreen->info.family == CHIP_VEGA10 ||
+					   sscreen->info.family == CHIP_RAVEN;
+	sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
+					sscreen->info.family == CHIP_RAVEN;
+
+	if (sscreen->debug_flags & DBG(DPBB)) {
 		sscreen->dpbb_allowed = true;
 	} else {
 		/* Only enable primitive binning on Raven by default. */
-		sscreen->dpbb_allowed = sscreen->b.family == CHIP_RAVEN &&
-					!(sscreen->b.debug_flags & DBG(NO_DPBB));
+		sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN &&
+					!(sscreen->debug_flags & DBG(NO_DPBB));
 	}
 
-	if (sscreen->b.debug_flags & DBG(DFSM)) {
+	if (sscreen->debug_flags & DBG(DFSM)) {
 		sscreen->dfsm_allowed = sscreen->dpbb_allowed;
 	} else {
 		sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
-					!(sscreen->b.debug_flags & DBG(NO_DFSM));
+					!(sscreen->debug_flags & DBG(NO_DFSM));
 	}
 
 	/* While it would be nice not to have this flag, we are constrained
 	 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
 	 * on GFX9.
 	 */
-	sscreen->llvm_has_working_vgpr_indexing = sscreen->b.chip_class <= VI;
+	sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= VI;
 
 	/* Some chips have RB+ registers, but don't support RB+. Those must
 	 * always disable it.
 	 */
-	if (sscreen->b.family == CHIP_STONEY ||
-	    sscreen->b.chip_class >= GFX9) {
-		sscreen->b.has_rbplus = true;
-
-		sscreen->b.rbplus_allowed =
-			!(sscreen->b.debug_flags & DBG(NO_RB_PLUS)) &&
-			(sscreen->b.family == CHIP_STONEY ||
-			 sscreen->b.family == CHIP_RAVEN);
+	if (sscreen->info.family == CHIP_STONEY ||
+	    sscreen->info.chip_class >= GFX9) {
+		sscreen->has_rbplus = true;
+
+		sscreen->rbplus_allowed =
+			!(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
+			(sscreen->info.family == CHIP_STONEY ||
+			 sscreen->info.family == CHIP_RAVEN);
 	}
 
-	sscreen->b.dcc_msaa_allowed =
-		!(sscreen->b.debug_flags & DBG(NO_DCC_MSAA)) &&
-		(sscreen->b.debug_flags & DBG(DCC_MSAA) ||
-		 sscreen->b.chip_class == VI);
+	sscreen->dcc_msaa_allowed =
+		!(sscreen->debug_flags & DBG(NO_DCC_MSAA)) &&
+		(sscreen->debug_flags & DBG(DCC_MSAA) ||
+		 sscreen->info.chip_class == VI);
 
 	(void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
 	sscreen->use_monolithic_shaders =
-		(sscreen->b.debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
+		(sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
 
-	sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
+	sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
 					    SI_CONTEXT_INV_VMEM_L1;
-	if (sscreen->b.chip_class <= VI) {
-		sscreen->b.barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
-		sscreen->b.barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
+	if (sscreen->info.chip_class <= VI) {
+		sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
+		sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
 	}
 
 	if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
-		sscreen->b.debug_flags |= DBG_ALL_SHADERS;
+		sscreen->debug_flags |= DBG_ALL_SHADERS;
 
 	for (i = 0; i < num_compiler_threads; i++)
 		sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
 	for (i = 0; i < num_compiler_threads_lowprio; i++)
 		sscreen->tm_low_priority[i] = si_create_llvm_target_machine(sscreen);
 
 	/* Create the auxiliary context. This must be done last. */
-	sscreen->b.aux_context = si_create_context(&sscreen->b.b, 0);
+	sscreen->aux_context = si_create_context(&sscreen->b, 0);
 
-	if (sscreen->b.debug_flags & DBG(TEST_DMA))
+	if (sscreen->debug_flags & DBG(TEST_DMA))
 		si_test_dma(sscreen);
 
-	if (sscreen->b.debug_flags & (DBG(TEST_VMFAULT_CP) |
+	if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
 				      DBG(TEST_VMFAULT_SDMA) |
 				      DBG(TEST_VMFAULT_SHADER)))
 		si_test_vmfault(sscreen);
 
-	return &sscreen->b.b;
+	return &sscreen->b;
 }
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 0c16cfb..7a09937 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -87,39 +87,105 @@
 
 #define SI_MAX_BORDER_COLORS	4096
 #define SI_MAX_VIEWPORTS        16
 #define SIX_BITS		0x3F
 
 struct si_compute;
 struct hash_table;
 struct u_suballocator;
 
 struct si_screen {
-	struct r600_common_screen	b;
+	struct pipe_screen		b;
+	struct radeon_winsys		*ws;
+	struct disk_cache		*disk_shader_cache;
+
+	struct radeon_info		info;
+	uint64_t			debug_flags;
+	char				renderer_string[100];
+
 	unsigned			gs_table_depth;
 	unsigned			tess_offchip_block_dw_size;
 	bool				has_clear_state;
 	bool				has_distributed_tess;
 	bool				has_draw_indirect_multi;
 	bool				has_out_of_order_rast;
 	bool				assume_no_z_fights;
 	bool				commutative_blend_add;
 	bool				clear_db_cache_before_clear;
 	bool				has_msaa_sample_loc_bug;
 	bool				has_ls_vgpr_init_bug;
 	bool				dpbb_allowed;
 	bool				dfsm_allowed;
 	bool				llvm_has_working_vgpr_indexing;
 
 	/* Whether shaders are monolithic (1-part) or separate (3-part). */
 	bool				use_monolithic_shaders;
 	bool				record_llvm_ir;
+	bool				has_rbplus;     /* if RB+ registers exist */
+	bool				rbplus_allowed; /* if RB+ is allowed */
+	bool				dcc_msaa_allowed;
+
+	struct slab_parent_pool		pool_transfers;
+
+	/* Texture filter settings. */
+	int				force_aniso; /* -1 = disabled */
+
+	/* Auxiliary context. Mainly used to initialize resources.
+	 * It must be locked prior to using and flushed before unlocking. */
+	struct pipe_context		*aux_context;
+	mtx_t				aux_context_lock;
+
+	/* This must be in the screen, because UE4 uses one context for
+	 * compilation and another one for rendering.
+	 */
+	unsigned			num_compilations;
+	/* Along with ST_DEBUG=precompile, this should show if applications
+	 * are loading shaders on demand. This is a monotonic counter.
+	 */
+	unsigned			num_shaders_created;
+	unsigned			num_shader_cache_hits;
+
+	/* GPU load thread. */
+	mtx_t				gpu_load_mutex;
+	thrd_t				gpu_load_thread;
+	union r600_mmio_counters	mmio_counters;
+	volatile unsigned		gpu_load_stop_thread; /* bool */
+
+	/* Performance counters. */
+	struct r600_perfcounters	*perfcounters;
+
+	/* If pipe_screen wants to recompute and re-emit the framebuffer,
+	 * sampler, and image states of all contexts, it should atomically
+	 * increment this.
+	 *
+	 * Each context will compare this with its own last known value of
+	 * the counter before drawing and re-emit the states accordingly.
+	 */
+	unsigned			dirty_tex_counter;
+
+	/* Atomically increment this counter when an existing texture's
+	 * metadata is enabled or disabled in a way that requires changing
+	 * contexts' compressed texture binding masks.
+	 */
+	unsigned			compressed_colortex_counter;
+
+	struct {
+		/* Context flags to set so that all writes from earlier jobs
+		 * in the CP are seen by L2 clients.
+		 */
+		unsigned cp_to_L2;
+
+		/* Context flags to set so that all writes from earlier jobs
+		 * that end in L2 are seen by CP.
+		 */
+		unsigned L2_to_cp;
+	} barrier_flags;
 
 	mtx_t			shader_parts_mutex;
 	struct si_shader_part		*vs_prologs;
 	struct si_shader_part		*tcs_epilogs;
 	struct si_shader_part		*gs_prologs;
 	struct si_shader_part		*ps_prologs;
 	struct si_shader_part		*ps_epilogs;
 
 	/* Shader cache in memory.
 	 *
@@ -746,48 +812,48 @@ static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 	if (sctx->gs_shader.cso)
 		return sctx->gs_shader.cso->gs_copy_shader;
 
 	struct si_shader_ctx_state *vs = si_get_vs(sctx);
 	return vs->current ? vs->current : NULL;
 }
 
 static inline bool si_can_dump_shader(struct si_screen *sscreen,
 				      unsigned processor)
 {
-	return sscreen->b.debug_flags & (1 << processor);
+	return sscreen->debug_flags & (1 << processor);
 }
 
 static inline bool si_extra_shader_checks(struct si_screen *sscreen,
 					  unsigned processor)
 {
-	return (sscreen->b.debug_flags & DBG(CHECK_IR)) ||
+	return (sscreen->debug_flags & DBG(CHECK_IR)) ||
 	       si_can_dump_shader(sscreen, processor);
 }
 
 static inline bool si_get_strmout_en(struct si_context *sctx)
 {
 	return sctx->streamout.streamout_enabled ||
 	       sctx->streamout.prims_gen_query_enabled;
 }
 
 static inline unsigned
 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 {
 	unsigned alignment, tcc_cache_line_size;
 
 	/* If the upload size is less than the cache line size (e.g. 16, 32),
 	 * the whole thing will fit into a cache line if we align it to its size.
 	 * The idea is that multiple small uploads can share a cache line.
 	 * If the upload size is greater, align it to the cache line size.
 	 */
 	alignment = util_next_power_of_two(upload_size);
-	tcc_cache_line_size = sctx->screen->b.info.tcc_cache_line_size;
+	tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
 	return MIN2(alignment, tcc_cache_line_size);
 }
 
 static inline void
 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
 {
 	if (pipe_reference(&(*dst)->reference, &src->reference))
 		si_destroy_saved_cs(*dst);
 
 	*dst = src;
diff --git a/src/gallium/drivers/radeonsi/si_pm4.c b/src/gallium/drivers/radeonsi/si_pm4.c
index 98aa94a..96e4e1d 100644
--- a/src/gallium/drivers/radeonsi/si_pm4.c
+++ b/src/gallium/drivers/radeonsi/si_pm4.c
@@ -166,21 +166,21 @@ void si_pm4_upload_indirect_buffer(struct si_context *sctx,
 	assert(aligned_ndw <= SI_PM4_MAX_DW);
 
 	r600_resource_reference(&state->indirect_buffer, NULL);
 	state->indirect_buffer = (struct r600_resource*)
 		pipe_buffer_create(screen, 0,
 				   PIPE_USAGE_DEFAULT, aligned_ndw * 4);
 	if (!state->indirect_buffer)
 		return;
 
 	/* Pad the IB to 8 DWs to meet CP fetch alignment requirements. */
-	if (sctx->screen->b.info.gfx_ib_pad_with_type2) {
+	if (sctx->screen->info.gfx_ib_pad_with_type2) {
 		for (int i = state->ndw; i < aligned_ndw; i++)
 			state->pm4[i] = 0x80000000; /* type2 nop packet */
 	} else {
 		for (int i = state->ndw; i < aligned_ndw; i++)
 			state->pm4[i] = 0xffff1000; /* type3 nop packet */
 	}
 
 	pipe_buffer_write(&sctx->b.b, &state->indirect_buffer->b.b,
 			  0, aligned_ndw *4, state->pm4);
 }
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index e942d34..d3e5e97 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -98,21 +98,21 @@ static void si_build_ps_epilog_function(struct si_shader_context *ctx,
  */
 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
 
 enum {
 	CONST_ADDR_SPACE = 2,
 	LOCAL_ADDR_SPACE = 3,
 };
 
 static bool is_merged_shader(struct si_shader *shader)
 {
-	if (shader->selector->screen->b.chip_class <= VI)
+	if (shader->selector->screen->info.chip_class <= VI)
 		return false;
 
 	return shader->key.as_ls ||
 	       shader->key.as_es ||
 	       shader->selector->type == PIPE_SHADER_TESS_CTRL ||
 	       shader->selector->type == PIPE_SHADER_GEOMETRY;
 }
 
 static void si_init_function_info(struct si_function_info *fninfo)
 {
@@ -400,21 +400,21 @@ static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
 {
 	unsigned stride;
 
 	switch (ctx->type) {
 	case PIPE_SHADER_VERTEX:
 		stride = util_last_bit64(ctx->shader->selector->outputs_written);
 		return LLVMConstInt(ctx->i32, stride * 4, 0);
 
 	case PIPE_SHADER_TESS_CTRL:
-		if (ctx->screen->b.chip_class >= GFX9 &&
+		if (ctx->screen->info.chip_class >= GFX9 &&
 		    ctx->shader->is_monolithic) {
 			stride = util_last_bit64(ctx->shader->key.part.tcs.ls->outputs_written);
 			return LLVMConstInt(ctx->i32, stride * 4, 0);
 		}
 		return unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
 
 	default:
 		assert(0);
 		return NULL;
 	}
@@ -1316,21 +1316,21 @@ static LLVMValueRef fetch_input_gs(
 
 	if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
 		return get_primitive_id(ctx, swizzle);
 
 	if (!reg->Register.Dimension)
 		return NULL;
 
 	param = si_shader_io_get_unique_index(semantic_name, semantic_index);
 
 	/* GFX9 has the ESGS ring in LDS. */
-	if (ctx->screen->b.chip_class >= GFX9) {
+	if (ctx->screen->info.chip_class >= GFX9) {
 		unsigned index = reg->Dimension.Index;
 
 		switch (index / 2) {
 		case 0:
 			vtx_offset = unpack_param(ctx, ctx->param_gs_vtx01_offset,
 						  index % 2 ? 16 : 0, 16);
 			break;
 		case 1:
 			vtx_offset = unpack_param(ctx, ctx->param_gs_vtx23_offset,
 						  index % 2 ? 16 : 0, 16);
@@ -2002,21 +2002,21 @@ static LLVMValueRef fetch_constant(
 		 *
 		 * Using s_buffer_load_dword (x1) seems to be the best option right now.
 		 *
 		 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
 		 * a descriptor and s_buffer_load_dword using it, so we can't expand
 		 * the pointer into a full descriptor like below. We have to use
 		 * s_load_dword instead. The only case when LLVM 5.0 would select
 		 * s_buffer_load_dword (that we have to prevent) is when we use use
 		 * a literal offset where we don't need bounds checking.
 		 */
-		if (ctx->screen->b.chip_class == SI &&
+		if (ctx->screen->info.chip_class == SI &&
                     HAVE_LLVM < 0x0600 &&
                     !reg->Register.Indirect) {
 			addr = LLVMBuildLShr(ctx->ac.builder, addr, LLVMConstInt(ctx->i32, 2, 0), "");
 			LLVMValueRef result = ac_build_load_invariant(&ctx->ac, ptr, addr);
 			return bitcast(bld_base, type, result);
 		}
 
 		/* Do the bounds checking with a descriptor, because
 		 * doing computation and manual bounds checking of 64-bit
 		 * addresses generates horrible VALU code with very high
@@ -2651,21 +2651,21 @@ static void si_llvm_export_vs(struct si_shader_context *ctx,
 							 edgeflag_value,
 							 ctx->i32, "");
 			edgeflag_value = ac_build_umin(&ctx->ac,
 						      edgeflag_value,
 						      ctx->i32_1);
 
 			/* The LLVM intrinsic expects a float. */
 			pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
 		}
 
-		if (ctx->screen->b.chip_class >= GFX9) {
+		if (ctx->screen->info.chip_class >= GFX9) {
 			/* GFX9 has the layer in out.z[10:0] and the viewport
 			 * index in out.z[19:16].
 			 */
 			if (shader->selector->info.writes_layer)
 				pos_args[1].out[2] = layer_value;
 
 			if (shader->selector->info.writes_viewport_index) {
 				LLVMValueRef v = viewport_index_value;
 
 				v = ac_to_integer(&ctx->ac, v);
@@ -2863,21 +2863,21 @@ static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
 			       ctx->param_tcs_factor_offset);
 	byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
 				  LLVMConstInt(ctx->i32, 4 * stride, 0), "");
 
 	lp_build_if(&inner_if_ctx, &ctx->gallivm,
 		    LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
 				  rel_patch_id, ctx->i32_0, ""));
 
 	/* Store the dynamic HS control word. */
 	offset = 0;
-	if (ctx->screen->b.chip_class <= VI) {
+	if (ctx->screen->info.chip_class <= VI) {
 		ac_build_buffer_store_dword(&ctx->ac, buffer,
 					    LLVMConstInt(ctx->i32, 0x80000000, 0),
 					    1, ctx->i32_0, tf_base,
 					    offset, 1, 0, true, false);
 		offset += 4;
 	}
 
 	lp_build_endif(&inner_if_ctx);
 
 	/* Store the tessellation factors. */
@@ -2970,21 +2970,21 @@ static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
 	struct si_shader_context *ctx = si_shader_context(bld_base);
 	LLVMBuilderRef builder = ctx->ac.builder;
 	LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
 
 	si_copy_tcs_inputs(bld_base);
 
 	rel_patch_id = get_rel_patch_id(ctx);
 	invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
 	tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
 
-	if (ctx->screen->b.chip_class >= GFX9) {
+	if (ctx->screen->info.chip_class >= GFX9) {
 		LLVMBasicBlockRef blocks[2] = {
 			LLVMGetInsertBlock(builder),
 			ctx->merged_wrap_if_state.entry_block
 		};
 		LLVMValueRef values[2];
 
 		lp_build_endif(&ctx->merged_wrap_if_state);
 
 		values[0] = rel_patch_id;
 		values[1] = LLVMGetUndef(ctx->i32);
@@ -2996,21 +2996,21 @@ static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
 
 		values[0] = invocation_id;
 		values[1] = ctx->i32_1; /* cause the epilog to skip threads */
 		invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
 	}
 
 	/* Return epilog parameters from this function. */
 	LLVMValueRef ret = ctx->return_value;
 	unsigned vgpr;
 
-	if (ctx->screen->b.chip_class >= GFX9) {
+	if (ctx->screen->info.chip_class >= GFX9) {
 		ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
 					  8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
 		ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
 					  8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
 		ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
 					  8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
 		/* Tess offchip and tess factor offsets are at the beginning. */
 		ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
 		ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
 		vgpr = 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K + 1;
@@ -3173,36 +3173,36 @@ static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
 
 		for (chan = 0; chan < 4; chan++) {
 			if (!(info->output_usagemask[i] & (1 << chan)))
 				continue;
 
 			lds_store(bld_base, chan, dw_addr,
 				  LLVMBuildLoad(ctx->ac.builder, out_ptr[chan], ""));
 		}
 	}
 
-	if (ctx->screen->b.chip_class >= GFX9)
+	if (ctx->screen->info.chip_class >= GFX9)
 		si_set_ls_return_value_for_tcs(ctx);
 }
 
 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
 {
 	struct si_shader_context *ctx = si_shader_context(bld_base);
 	struct si_shader *es = ctx->shader;
 	struct tgsi_shader_info *info = &es->selector->info;
 	LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
 					    ctx->param_es2gs_offset);
 	LLVMValueRef lds_base = NULL;
 	unsigned chan;
 	int i;
 
-	if (ctx->screen->b.chip_class >= GFX9 && info->num_outputs) {
+	if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
 		unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
 		LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
 		LLVMValueRef wave_idx = unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
 		vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
 					 LLVMBuildMul(ctx->ac.builder, wave_idx,
 						      LLVMConstInt(ctx->i32, 64, false), ""), "");
 		lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
 					LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
 	}
 
@@ -3215,53 +3215,53 @@ static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
 			continue;
 
 		param = si_shader_io_get_unique_index(info->output_semantic_name[i],
 						      info->output_semantic_index[i]);
 
 		for (chan = 0; chan < 4; chan++) {
 			LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[chan], "");
 			out_val = ac_to_integer(&ctx->ac, out_val);
 
 			/* GFX9 has the ESGS ring in LDS. */
-			if (ctx->screen->b.chip_class >= GFX9) {
+			if (ctx->screen->info.chip_class >= GFX9) {
 				lds_store(bld_base, param * 4 + chan, lds_base, out_val);
 				continue;
 			}
 
 			ac_build_buffer_store_dword(&ctx->ac,
 						    ctx->esgs_ring,
 						    out_val, 1, NULL, soffset,
 						    (4 * param + chan) * 4,
 						    1, 1, true, true);
 		}
 	}
 
-	if (ctx->screen->b.chip_class >= GFX9)
+	if (ctx->screen->info.chip_class >= GFX9)
 		si_set_es_return_value_for_gs(ctx);
 }
 
 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
 {
-	if (ctx->screen->b.chip_class >= GFX9)
+	if (ctx->screen->info.chip_class >= GFX9)
 		return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
 	else
 		return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
 }
 
 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
 {
 	struct si_shader_context *ctx = si_shader_context(bld_base);
 
 	ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
 			 si_get_gs_wave_id(ctx));
 
-	if (ctx->screen->b.chip_class >= GFX9)
+	if (ctx->screen->info.chip_class >= GFX9)
 		lp_build_endif(&ctx->merged_wrap_if_state);
 }
 
 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
 				     unsigned max_outputs,
 				     LLVMValueRef *addrs)
 {
 	struct si_shader_context *ctx = si_shader_context_from_abi(abi);
 	struct tgsi_shader_info *info = &ctx->shader->selector->info;
 	struct si_shader_output_values *outputs = NULL;
@@ -3429,23 +3429,23 @@ static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
 			mask |= 0x2;
 		}
 		if (samplemask) {
 			args.out[2] = samplemask;
 			mask |= 0x4;
 		}
 	}
 
 	/* SI (except OLAND and HAINAN) has a bug that it only looks
 	 * at the X writemask component. */
-	if (ctx->screen->b.chip_class == SI &&
-	    ctx->screen->b.family != CHIP_OLAND &&
-	    ctx->screen->b.family != CHIP_HAINAN)
+	if (ctx->screen->info.chip_class == SI &&
+	    ctx->screen->info.family != CHIP_OLAND &&
+	    ctx->screen->info.family != CHIP_HAINAN)
 		mask |= 0x1;
 
 	/* Specify which components to enable */
 	args.enabled_channels = mask;
 
 	memcpy(&exp->args[exp->num++], &args, sizeof(args));
 }
 
 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
 				LLVMValueRef *color, unsigned index,
@@ -4145,21 +4145,21 @@ static void si_llvm_emit_primitive(
 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
 				 struct lp_build_tgsi_context *bld_base,
 				 struct lp_build_emit_data *emit_data)
 {
 	struct si_shader_context *ctx = si_shader_context(bld_base);
 
 	/* SI only (thanks to a hw bug workaround):
 	 * The real barrier instruction isn’t needed, because an entire patch
 	 * always fits into a single wave.
 	 */
-	if (ctx->screen->b.chip_class == SI &&
+	if (ctx->screen->info.chip_class == SI &&
 	    ctx->type == PIPE_SHADER_TESS_CTRL) {
 		si_emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
 		return;
 	}
 
 	lp_build_intrinsic(ctx->ac.builder,
 			   "llvm.amdgcn.s.barrier",
 			   ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
 }
 
@@ -4204,21 +4204,21 @@ static void si_create_function(struct si_shader_context *ctx,
 	}
 
 	if (max_workgroup_size) {
 		si_llvm_add_attribute(ctx->main_fn, "amdgpu-max-work-group-size",
 				      max_workgroup_size);
 	}
 	LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
 					   "no-signed-zeros-fp-math",
 					   "true");
 
-	if (ctx->screen->b.debug_flags & DBG(UNSAFE_MATH)) {
+	if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
 		/* These were copied from some LLVM test. */
 		LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
 						   "less-precise-fpmad",
 						   "true");
 		LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
 						   "no-infs-fp-math",
 						   "true");
 		LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
 						   "no-nans-fp-math",
 						   "true");
@@ -4251,24 +4251,24 @@ static void declare_streamout_params(struct si_shader_context *ctx,
 		ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
 	}
 }
 
 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
 {
 	switch (shader->selector->type) {
 	case PIPE_SHADER_TESS_CTRL:
 		/* Return this so that LLVM doesn't remove s_barrier
 		 * instructions on chips where we use s_barrier. */
-		return shader->selector->screen->b.chip_class >= CIK ? 128 : 64;
+		return shader->selector->screen->info.chip_class >= CIK ? 128 : 64;
 
 	case PIPE_SHADER_GEOMETRY:
-		return shader->selector->screen->b.chip_class >= GFX9 ? 128 : 64;
+		return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
 
 	case PIPE_SHADER_COMPUTE:
 		break; /* see below */
 
 	default:
 		return 0;
 	}
 
 	const unsigned *properties = shader->selector->info.properties;
 	unsigned max_work_group_size =
@@ -4380,21 +4380,21 @@ static void create_function(struct si_shader_context *ctx)
 	unsigned i, num_return_sgprs;
 	unsigned num_returns = 0;
 	unsigned num_prolog_vgprs = 0;
 	unsigned type = ctx->type;
 	unsigned vs_blit_property =
 		shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
 
 	si_init_function_info(&fninfo);
 
 	/* Set MERGED shaders. */
-	if (ctx->screen->b.chip_class >= GFX9) {
+	if (ctx->screen->info.chip_class >= GFX9) {
 		if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
 			type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
 		else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
 			type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
 	}
 
 	LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
 
 	switch (type) {
 	case PIPE_SHADER_VERTEX:
@@ -4747,21 +4747,21 @@ static void create_function(struct si_shader_context *ctx)
  * Load ESGS and GSVS ring buffer resource descriptors and save the variables
  * for later use.
  */
 static void preload_ring_buffers(struct si_shader_context *ctx)
 {
 	LLVMBuilderRef builder = ctx->ac.builder;
 
 	LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
 					    ctx->param_rw_buffers);
 
-	if (ctx->screen->b.chip_class <= VI &&
+	if (ctx->screen->info.chip_class <= VI &&
 	    (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
 		unsigned ring =
 			ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
 							     : SI_ES_RING_ESGS;
 		LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
 
 		ctx->esgs_ring =
 			ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
 	}
 
@@ -5010,28 +5010,28 @@ int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
 
 	assert(!prolog || !prolog->rodata_size);
 	assert(!previous_stage || !previous_stage->rodata_size);
 	assert(!prolog2 || !prolog2->rodata_size);
 	assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
 	       !mainb->rodata_size);
 	assert(!epilog || !epilog->rodata_size);
 
 	r600_resource_reference(&shader->bo, NULL);
 	shader->bo = (struct r600_resource*)
-		     pipe_buffer_create(&sscreen->b.b, 0,
+		     pipe_buffer_create(&sscreen->b, 0,
 					PIPE_USAGE_IMMUTABLE,
 					align(bo_size, SI_CPDMA_ALIGNMENT));
 	if (!shader->bo)
 		return -ENOMEM;
 
 	/* Upload. */
-	ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
+	ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
 					PIPE_TRANSFER_READ_WRITE |
 					PIPE_TRANSFER_UNSYNCHRONIZED);
 
 	/* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
 	 * endian-independent. */
 	if (prolog) {
 		memcpy(ptr, prolog->code, prolog->code_size);
 		ptr += prolog->code_size;
 	}
 	if (previous_stage) {
@@ -5044,21 +5044,21 @@ int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
 	}
 
 	memcpy(ptr, mainb->code, mainb->code_size);
 	ptr += mainb->code_size;
 
 	if (epilog)
 		memcpy(ptr, epilog->code, epilog->code_size);
 	else if (mainb->rodata_size > 0)
 		memcpy(ptr, mainb->rodata, mainb->rodata_size);
 
-	sscreen->b.ws->buffer_unmap(shader->bo->buf);
+	sscreen->ws->buffer_unmap(shader->bo->buf);
 	return 0;
 }
 
 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
 				       struct pipe_debug_callback *debug,
 				       const char *name, FILE *file)
 {
 	char *line, *p;
 	unsigned i, count;
 
@@ -5106,25 +5106,25 @@ static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
 static void si_shader_dump_stats(struct si_screen *sscreen,
 				 const struct si_shader *shader,
 			         struct pipe_debug_callback *debug,
 			         unsigned processor,
 				 FILE *file,
 				 bool check_debug_option)
 {
 	const struct si_shader_config *conf = &shader->config;
 	unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
 	unsigned code_size = si_get_shader_binary_size(shader);
-	unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
+	unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256;
 	unsigned lds_per_wave = 0;
 	unsigned max_simd_waves;
 
-	switch (sscreen->b.family) {
+	switch (sscreen->info.family) {
 	/* These always have 8 waves: */
 	case CHIP_POLARIS10:
 	case CHIP_POLARIS11:
 	case CHIP_POLARIS12:
 		max_simd_waves = 8;
 		break;
 	default:
 		max_simd_waves = 10;
 	}
 
@@ -5149,21 +5149,21 @@ static void si_shader_dump_stats(struct si_screen *sscreen,
 			unsigned max_workgroup_size =
 				si_get_max_workgroup_size(shader);
 			lds_per_wave = (conf->lds_size * lds_increment) /
 				       DIV_ROUND_UP(max_workgroup_size, 64);
 		}
 		break;
 	}
 
 	/* Compute the per-SIMD wave counts. */
 	if (conf->num_sgprs) {
-		if (sscreen->b.chip_class >= VI)
+		if (sscreen->info.chip_class >= VI)
 			max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
 		else
 			max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
 	}
 
 	if (conf->num_vgprs)
 		max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
 
 	/* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
 	 * 16KB makes some SIMDs unoccupied). */
@@ -5254,21 +5254,21 @@ void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
 			fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
 		}
 
 		fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
 			si_get_shader_name(shader, processor));
 		fprintf(file, "%s\n", shader->binary.llvm_ir_string);
 	}
 
 	if (!check_debug_option ||
 	    (si_can_dump_shader(sscreen, processor) &&
-	     !(sscreen->b.debug_flags & DBG(NO_ASM)))) {
+	     !(sscreen->debug_flags & DBG(NO_ASM)))) {
 		fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
 
 		if (shader->prolog)
 			si_shader_dump_disassembly(&shader->prolog->binary,
 						   debug, "prolog", file);
 		if (shader->previous_stage)
 			si_shader_dump_disassembly(&shader->previous_stage->binary,
 						   debug, "previous stage", file);
 		if (shader->prolog2)
 			si_shader_dump_disassembly(&shader->prolog2->binary,
@@ -5289,26 +5289,26 @@ void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
 static int si_compile_llvm(struct si_screen *sscreen,
 			   struct ac_shader_binary *binary,
 			   struct si_shader_config *conf,
 			   LLVMTargetMachineRef tm,
 			   LLVMModuleRef mod,
 			   struct pipe_debug_callback *debug,
 			   unsigned processor,
 			   const char *name)
 {
 	int r = 0;
-	unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
+	unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
 
 	if (si_can_dump_shader(sscreen, processor)) {
 		fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
 
-		if (!(sscreen->b.debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
+		if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
 			fprintf(stderr, "%s LLVM IR:\n\n", name);
 			ac_dump_module(mod);
 			fprintf(stderr, "\n");
 		}
 	}
 
 	if (sscreen->record_llvm_ir) {
 		char *ir = LLVMPrintModuleToString(mod);
 		binary->llvm_ir_string = strdup(ir);
 		LLVMDisposeMessage(ir);
@@ -5544,39 +5544,39 @@ static void si_dump_shader_key(unsigned processor, const struct si_shader *shade
 	case PIPE_SHADER_VERTEX:
 		si_dump_shader_key_vs(key, &key->part.vs.prolog,
 				      "part.vs.prolog", f);
 		fprintf(f, "  as_es = %u\n", key->as_es);
 		fprintf(f, "  as_ls = %u\n", key->as_ls);
 		fprintf(f, "  mono.u.vs_export_prim_id = %u\n",
 			key->mono.u.vs_export_prim_id);
 		break;
 
 	case PIPE_SHADER_TESS_CTRL:
-		if (shader->selector->screen->b.chip_class >= GFX9) {
+		if (shader->selector->screen->info.chip_class >= GFX9) {
 			si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
 					      "part.tcs.ls_prolog", f);
 		}
 		fprintf(f, "  part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
 		fprintf(f, "  mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
 		break;
 
 	case PIPE_SHADER_TESS_EVAL:
 		fprintf(f, "  as_es = %u\n", key->as_es);
 		fprintf(f, "  mono.u.vs_export_prim_id = %u\n",
 			key->mono.u.vs_export_prim_id);
 		break;
 
 	case PIPE_SHADER_GEOMETRY:
 		if (shader->is_gs_copy_shader)
 			break;
 
-		if (shader->selector->screen->b.chip_class >= GFX9 &&
+		if (shader->selector->screen->info.chip_class >= GFX9 &&
 		    key->part.gs.es->type == PIPE_SHADER_VERTEX) {
 			si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
 					      "part.gs.vs_prolog", f);
 		}
 		fprintf(f, "  part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
 		break;
 
 	case PIPE_SHADER_COMPUTE:
 		break;
 
@@ -5787,21 +5787,21 @@ static bool si_compile_tgsi_main(struct si_shader_context *ctx,
 	 *   EXEC there instead.
 	 * - Add a barrier before the second shader.
 	 * - In the second shader, reset EXEC to ~0 and wrap the main part in
 	 *   an if-statement. This is required for correctness in geometry
 	 *   shaders, to ensure that empty GS waves do not send GS_EMIT and
 	 *   GS_CUT messages.
 	 *
 	 * For monolithic merged shaders, the first shader is wrapped in an
 	 * if-block together with its prolog in si_build_wrapper_function.
 	 */
-	if (ctx->screen->b.chip_class >= GFX9) {
+	if (ctx->screen->info.chip_class >= GFX9) {
 		if (!is_monolithic &&
 		    sel->info.num_instructions > 1 && /* not empty shader */
 		    (shader->key.as_es || shader->key.as_ls) &&
 		    (ctx->type == PIPE_SHADER_TESS_EVAL ||
 		     (ctx->type == PIPE_SHADER_VERTEX &&
 		      !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
 			si_init_exec_from_input(ctx,
 						ctx->param_merged_wave_info, 0);
 		} else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
 			   ctx->type == PIPE_SHADER_GEOMETRY) {
@@ -6061,21 +6061,21 @@ static void si_build_gs_prolog_function(struct si_shader_context *ctx,
 					union si_shader_part_key *key)
 {
 	unsigned num_sgprs, num_vgprs;
 	struct si_function_info fninfo;
 	LLVMBuilderRef builder = ctx->ac.builder;
 	LLVMTypeRef returns[48];
 	LLVMValueRef func, ret;
 
 	si_init_function_info(&fninfo);
 
-	if (ctx->screen->b.chip_class >= GFX9) {
+	if (ctx->screen->info.chip_class >= GFX9) {
 		num_sgprs = 8 + GFX9_GS_NUM_USER_SGPR;
 		num_vgprs = 5; /* ES inputs are not needed by GS */
 	} else {
 		num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
 		num_vgprs = 8;
 	}
 
 	for (unsigned i = 0; i < num_sgprs; ++i) {
 		add_arg(&fninfo, ARG_SGPR, ctx->i32);
 		returns[i] = ctx->i32;
@@ -6088,21 +6088,21 @@ static void si_build_gs_prolog_function(struct si_shader_context *ctx,
 
 	/* Create the function. */
 	si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
 			   &fninfo, 0);
 	func = ctx->main_fn;
 
 	/* Set the full EXEC mask for the prolog, because we are only fiddling
 	 * with registers here. The main shader part will set the correct EXEC
 	 * mask.
 	 */
-	if (ctx->screen->b.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
+	if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
 		si_init_exec_full_mask(ctx);
 
 	/* Copy inputs to outputs. This should be no-op, as the registers match,
 	 * but it will prevent the compiler from overwriting them unintentionally.
 	 */
 	ret = ctx->return_value;
 	for (unsigned i = 0; i < num_sgprs; i++) {
 		LLVMValueRef p = LLVMGetParam(func, i);
 		ret = LLVMBuildInsertValue(builder, ret, p, i, "");
 	}
@@ -6123,41 +6123,41 @@ static void si_build_gs_prolog_function(struct si_shader_context *ctx,
 			num_sgprs + 6
 		};
 		const unsigned gfx9_vtx_params[3] = {
 			num_sgprs,
 			num_sgprs + 1,
 			num_sgprs + 4,
 		};
 		LLVMValueRef vtx_in[6], vtx_out[6];
 		LLVMValueRef prim_id, rotate;
 
-		if (ctx->screen->b.chip_class >= GFX9) {
+		if (ctx->screen->info.chip_class >= GFX9) {
 			for (unsigned i = 0; i < 3; i++) {
 				vtx_in[i*2] = unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
 				vtx_in[i*2+1] = unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
 			}
 		} else {
 			for (unsigned i = 0; i < 6; i++)
 				vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
 		}
 
 		prim_id = LLVMGetParam(func, num_sgprs + 2);
 		rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
 
 		for (unsigned i = 0; i < 6; ++i) {
 			LLVMValueRef base, rotated;
 			base = vtx_in[i];
 			rotated = vtx_in[(i + 4) % 6];
 			vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
 		}
 
-		if (ctx->screen->b.chip_class >= GFX9) {
+		if (ctx->screen->info.chip_class >= GFX9) {
 			for (unsigned i = 0; i < 3; i++) {
 				LLVMValueRef hi, out;
 
 				hi = LLVMBuildShl(builder, vtx_out[i*2+1],
 						  LLVMConstInt(ctx->i32, 16, 0), "");
 				out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
 				out = ac_to_float(&ctx->ac, out);
 				ret = LLVMBuildInsertValue(builder, ret, out,
 							   gfx9_vtx_params[i], "");
 			}
@@ -6410,21 +6410,21 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
 			   bool is_monolithic,
 			   struct pipe_debug_callback *debug)
 {
 	struct si_shader_selector *sel = shader->selector;
 	struct si_shader_context ctx;
 	int r = -1;
 
 	/* Dump TGSI code before doing TGSI->LLVM conversion in case the
 	 * conversion fails. */
 	if (si_can_dump_shader(sscreen, sel->info.processor) &&
-	    !(sscreen->b.debug_flags & DBG(NO_TGSI))) {
+	    !(sscreen->debug_flags & DBG(NO_TGSI))) {
 		if (sel->tokens)
 			tgsi_dump(sel->tokens, 0);
 		else
 			nir_print_shader(sel->nir, stderr);
 		si_dump_streamout(&sel->so);
 	}
 
 	si_init_shader_ctx(&ctx, sscreen, tm);
 	si_llvm_context_set_tgsi(&ctx, shader);
 	ctx.separate_prolog = !is_monolithic;
@@ -6451,21 +6451,21 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
 					     shader->info.num_input_sgprs,
 					     &shader->key.part.vs.prolog,
 					     shader, &prolog_key);
 			si_build_vs_prolog_function(&ctx, &prolog_key);
 			parts[0] = ctx.main_fn;
 		}
 
 		si_build_wrapper_function(&ctx, parts + !need_prolog,
 					  1 + need_prolog, need_prolog, 0);
 	} else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
-		if (sscreen->b.chip_class >= GFX9) {
+		if (sscreen->info.chip_class >= GFX9) {
 			struct si_shader_selector *ls = shader->key.part.tcs.ls;
 			LLVMValueRef parts[4];
 			bool vs_needs_prolog =
 				si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
 
 			/* TCS main part */
 			parts[2] = ctx.main_fn;
 
 			/* TCS epilog */
 			union si_shader_part_key tcs_epilog_key;
@@ -6516,21 +6516,21 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
 			parts[0] = ctx.main_fn;
 
 			memset(&epilog_key, 0, sizeof(epilog_key));
 			epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
 			si_build_tcs_epilog_function(&ctx, &epilog_key);
 			parts[1] = ctx.main_fn;
 
 			si_build_wrapper_function(&ctx, parts, 2, 0, 0);
 		}
 	} else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
-		if (ctx.screen->b.chip_class >= GFX9) {
+		if (ctx.screen->info.chip_class >= GFX9) {
 			struct si_shader_selector *es = shader->key.part.gs.es;
 			LLVMValueRef es_prolog = NULL;
 			LLVMValueRef es_main = NULL;
 			LLVMValueRef gs_prolog = NULL;
 			LLVMValueRef gs_main = ctx.main_fn;
 
 			/* GS prolog */
 			union si_shader_part_key gs_prolog_key;
 			memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
 			gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
@@ -6636,21 +6636,21 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
 		fprintf(stderr, "LLVM failed to compile shader\n");
 		return r;
 	}
 
 	/* Validate SGPR and VGPR usage for compute to detect compiler bugs.
 	 * LLVM 3.9svn has this bug.
 	 */
 	if (sel->type == PIPE_SHADER_COMPUTE) {
 		unsigned wave_size = 64;
 		unsigned max_vgprs = 256;
-		unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
+		unsigned max_sgprs = sscreen->info.chip_class >= VI ? 800 : 512;
 		unsigned max_sgprs_per_wave = 128;
 		unsigned max_block_threads = si_get_max_workgroup_size(shader);
 		unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
 		unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
 
 		max_vgprs = max_vgprs / min_waves_per_simd;
 		max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
 
 		if (shader->config.num_sgprs > max_sgprs ||
 		    shader->config.num_vgprs > max_vgprs) {
@@ -6807,21 +6807,21 @@ si_get_shader_part(struct si_screen *sscreen,
 out:
 	si_llvm_dispose(&ctx);
 	mtx_unlock(&sscreen->shader_parts_mutex);
 	return result;
 }
 
 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
 {
 	LLVMValueRef ptr[2], list;
 	bool is_merged_shader =
-		ctx->screen->b.chip_class >= GFX9 &&
+		ctx->screen->info.chip_class >= GFX9 &&
 		(ctx->type == PIPE_SHADER_TESS_CTRL ||
 		 ctx->type == PIPE_SHADER_GEOMETRY ||
 		 ctx->shader->key.as_ls || ctx->shader->key.as_es);
 
 	/* Get the pointer to rw buffers. */
 	ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
 	ptr[1] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS_HI);
 	list = lp_build_gather_values(&ctx->gallivm, ptr, 2);
 	list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
 	list = LLVMBuildIntToPtr(ctx->ac.builder, list,
@@ -7019,21 +7019,21 @@ static bool si_shader_select_vs_parts(struct si_screen *sscreen,
  */
 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
 					 union si_shader_part_key *key)
 {
 	struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
 	struct si_function_info fninfo;
 	LLVMValueRef func;
 
 	si_init_function_info(&fninfo);
 
-	if (ctx->screen->b.chip_class >= GFX9) {
+	if (ctx->screen->info.chip_class >= GFX9) {
 		add_arg(&fninfo, ARG_SGPR, ctx->i64);
 		ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
 		add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
 		ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
 		add_arg(&fninfo, ARG_SGPR, ctx->i32);
 		add_arg(&fninfo, ARG_SGPR, ctx->i32);
 		add_arg(&fninfo, ARG_SGPR, ctx->i32);
 		add_arg(&fninfo, ARG_SGPR, ctx->i64);
 		add_arg(&fninfo, ARG_SGPR, ctx->i64);
 		add_arg(&fninfo, ARG_SGPR, ctx->i64);
@@ -7068,21 +7068,21 @@ static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
 	unsigned tess_factors_idx =
 		add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
 	add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
 	add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
 
 	for (unsigned i = 0; i < 6; i++)
 		add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
 
 	/* Create the function. */
 	si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
-			   ctx->screen->b.chip_class >= CIK ? 128 : 64);
+			   ctx->screen->info.chip_class >= CIK ? 128 : 64);
 	ac_declare_lds_as_pointer(&ctx->ac);
 	func = ctx->main_fn;
 
 	LLVMValueRef invoc0_tess_factors[6];
 	for (unsigned i = 0; i < 6; i++)
 		invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
 
 	si_write_tess_factors(bld_base,
 			      LLVMGetParam(func, tess_factors_idx),
 			      LLVMGetParam(func, tess_factors_idx + 1),
@@ -7093,21 +7093,21 @@ static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
 }
 
 /**
  * Select and compile (or reuse) TCS parts (epilog).
  */
 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
 				       LLVMTargetMachineRef tm,
 				       struct si_shader *shader,
 				       struct pipe_debug_callback *debug)
 {
-	if (sscreen->b.chip_class >= GFX9) {
+	if (sscreen->info.chip_class >= GFX9) {
 		struct si_shader *ls_main_part =
 			shader->key.part.tcs.ls->main_shader_part_ls;
 
 		if (!si_get_vs_prolog(sscreen, tm, shader, debug, ls_main_part,
 				      &shader->key.part.tcs.ls_prolog))
 			return false;
 
 		shader->previous_stage = ls_main_part;
 	}
 
@@ -7125,21 +7125,21 @@ static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
 }
 
 /**
  * Select and compile (or reuse) GS parts (prolog).
  */
 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
 				      LLVMTargetMachineRef tm,
 				      struct si_shader *shader,
 				      struct pipe_debug_callback *debug)
 {
-	if (sscreen->b.chip_class >= GFX9) {
+	if (sscreen->info.chip_class >= GFX9) {
 		struct si_shader *es_main_part =
 			shader->key.part.gs.es->main_shader_part_es;
 
 		if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
 		    !si_get_vs_prolog(sscreen, tm, shader, debug, es_main_part,
 				      &shader->key.part.gs.vs_prolog))
 			return false;
 
 		shader->previous_stage = es_main_part;
 	}
@@ -7640,23 +7640,23 @@ static bool si_shader_select_ps_parts(struct si_screen *sscreen,
 	return true;
 }
 
 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
 				      unsigned *lds_size)
 {
 	/* SPI barrier management bug:
 	 *   Make sure we have at least 4k of LDS in use to avoid the bug.
 	 *   It applies to workgroup sizes of more than one wavefront.
 	 */
-	if (sscreen->b.family == CHIP_BONAIRE ||
-	    sscreen->b.family == CHIP_KABINI ||
-	    sscreen->b.family == CHIP_MULLINS)
+	if (sscreen->info.family == CHIP_BONAIRE ||
+	    sscreen->info.family == CHIP_KABINI ||
+	    sscreen->info.family == CHIP_MULLINS)
 		*lds_size = MAX2(*lds_size, 8);
 }
 
 static void si_fix_resource_usage(struct si_screen *sscreen,
 				  struct si_shader *shader)
 {
 	unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
 
 	shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
 
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
index 5552cc8..35ada5f 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
@@ -44,21 +44,21 @@ static const struct lp_build_tgsi_action tex_action;
 static LLVMValueRef get_buffer_size(
 	struct lp_build_tgsi_context *bld_base,
 	LLVMValueRef descriptor)
 {
 	struct si_shader_context *ctx = si_shader_context(bld_base);
 	LLVMBuilderRef builder = ctx->ac.builder;
 	LLVMValueRef size =
 		LLVMBuildExtractElement(builder, descriptor,
 					LLVMConstInt(ctx->i32, 2, 0), "");
 
-	if (ctx->screen->b.chip_class == VI) {
+	if (ctx->screen->info.chip_class == VI) {
 		/* On VI, the descriptor contains the size in bytes,
 		 * but TXQ must return the size in elements.
 		 * The stride is always non-zero for resources using TXQ.
 		 */
 		LLVMValueRef stride =
 			LLVMBuildExtractElement(builder, descriptor,
 						ctx->i32_1, "");
 		stride = LLVMBuildLShr(builder, stride,
 				       LLVMConstInt(ctx->i32, 16, 0), "");
 		stride = LLVMBuildAnd(builder, stride,
@@ -107,21 +107,21 @@ static bool tgsi_is_array_image(unsigned target)
  * non-trivial can eventually lead to lockups. This can occur when an
  * application binds an image as read-only but then uses a shader that writes
  * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
  * program termination) in this case, but it doesn't cost much to be a bit
  * nicer: disabling DCC in the shader still leads to undefined results but
  * avoids the lockup.
  */
 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
 				  LLVMValueRef rsrc)
 {
-	if (ctx->screen->b.chip_class <= CIK) {
+	if (ctx->screen->info.chip_class <= CIK) {
 		return rsrc;
 	} else {
 		LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
 		LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
 		LLVMValueRef tmp;
 
 		tmp = LLVMBuildExtractElement(ctx->ac.builder, rsrc, i32_6, "");
 		tmp = LLVMBuildAnd(ctx->ac.builder, tmp, i32_C, "");
 		return LLVMBuildInsertElement(ctx->ac.builder, rsrc, tmp, i32_6, "");
 	}
@@ -228,21 +228,21 @@ static LLVMValueRef image_fetch_coords(
 	LLVMValueRef coords[4];
 	LLVMValueRef tmp;
 	int chan;
 
 	for (chan = 0; chan < num_coords; ++chan) {
 		tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
 		tmp = ac_to_integer(&ctx->ac, tmp);
 		coords[chan] = tmp;
 	}
 
-	if (ctx->screen->b.chip_class >= GFX9) {
+	if (ctx->screen->info.chip_class >= GFX9) {
 		/* 1D textures are allocated and used as 2D on GFX9. */
 		if (target == TGSI_TEXTURE_1D) {
 			coords[1] = ctx->i32_0;
 			num_coords++;
 		} else if (target == TGSI_TEXTURE_1D_ARRAY) {
 			coords[2] = coords[1];
 			coords[1] = ctx->i32_0;
 			num_coords++;
 		} else if (target == TGSI_TEXTURE_2D) {
 			/* The hw can't bind a slice of a 3D image as a 2D
@@ -640,21 +640,21 @@ static void store_fetch_args(
 		   tgsi_is_bindless_image_file(inst->Dst[0].Register.File)) {
 		unsigned target = inst->Memory.Texture;
 		LLVMValueRef coords;
 
 		/* 8bit/16bit TC L1 write corruption bug on SI.
 		 * All store opcodes not aligned to a dword are affected.
 		 *
 		 * The only way to get unaligned stores in radeonsi is through
 		 * shader images.
 		 */
-		bool force_glc = ctx->screen->b.chip_class == SI;
+		bool force_glc = ctx->screen->info.chip_class == SI;
 
 		image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
 		coords = image_fetch_coords(bld_base, inst, 0, rsrc);
 
 		if (target == TGSI_TEXTURE_BUFFER) {
 			buffer_append_args(ctx, emit_data, rsrc, coords,
 					   ctx->i32_0, false, force_glc);
 		} else {
 			emit_data->args[1] = coords;
 			emit_data->args[2] = rsrc;
@@ -1007,21 +1007,21 @@ static void set_tex_fetch_args(struct si_shader_context *ctx,
 	STATIC_ASSERT(sizeof(args) <= sizeof(emit_data->args));
 	memcpy(emit_data->args, &args, sizeof(args));
 }
 
 static LLVMValueRef fix_resinfo(struct si_shader_context *ctx,
 				unsigned target, LLVMValueRef out)
 {
 	LLVMBuilderRef builder = ctx->ac.builder;
 
 	/* 1D textures are allocated and used as 2D on GFX9. */
-        if (ctx->screen->b.chip_class >= GFX9 &&
+        if (ctx->screen->info.chip_class >= GFX9 &&
 	    (target == TGSI_TEXTURE_1D_ARRAY ||
 	     target == TGSI_TEXTURE_SHADOW1D_ARRAY)) {
 		LLVMValueRef layers =
 			LLVMBuildExtractElement(builder, out,
 						LLVMConstInt(ctx->i32, 2, 0), "");
 		out = LLVMBuildInsertElement(builder, out, layers,
 					     ctx->i32_1, "");
 	}
 
 	/* Divide the number of layers by 6 to get the number of cubes. */
@@ -1146,21 +1146,21 @@ LLVMValueRef si_load_sampler_desc(struct si_shader_context *ctx,
  *     s_and_b32 samp0, samp0, img7
  *
  * VI:
  *   The ANISO_OVERRIDE sampler field enables this fix in TA.
  */
 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
 					   LLVMValueRef res, LLVMValueRef samp)
 {
 	LLVMValueRef img7, samp0;
 
-	if (ctx->screen->b.chip_class >= VI)
+	if (ctx->screen->info.chip_class >= VI)
 		return samp;
 
 	img7 = LLVMBuildExtractElement(ctx->ac.builder, res,
 				       LLVMConstInt(ctx->i32, 7, 0), "");
 	samp0 = LLVMBuildExtractElement(ctx->ac.builder, samp,
 					ctx->i32_0, "");
 	samp0 = LLVMBuildAnd(ctx->ac.builder, samp0, img7, "");
 	return LLVMBuildInsertElement(ctx->ac.builder, samp, samp0,
 				      ctx->i32_0, "");
 }
@@ -1367,21 +1367,21 @@ static void tex_fetch_args(
 		 * OpenGL 4.5 spec says:
 		 *
 		 *    "If the texture’s internal format indicates a fixed-point
 		 *     depth texture, then D_t and D_ref are clamped to the
 		 *     range [0, 1]; otherwise no clamping is performed."
 		 *
 		 * TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
 		 * so the depth comparison value isn't clamped for Z16 and
 		 * Z24 anymore. Do it manually here.
 		 */
-		if (ctx->screen->b.chip_class >= VI) {
+		if (ctx->screen->info.chip_class >= VI) {
 			LLVMValueRef upgraded;
 			LLVMValueRef clamped;
 			upgraded = LLVMBuildExtractElement(ctx->ac.builder, samp_ptr,
 							   LLVMConstInt(ctx->i32, 3, false), "");
 			upgraded = LLVMBuildLShr(ctx->ac.builder, upgraded,
 						 LLVMConstInt(ctx->i32, 29, false), "");
 			upgraded = LLVMBuildTrunc(ctx->ac.builder, upgraded, ctx->i1, "");
 			clamped = ac_build_clamp(&ctx->ac, z);
 			z = LLVMBuildSelect(ctx->ac.builder, upgraded, clamped, z, "");
 		}
@@ -1418,21 +1418,21 @@ static void tex_fetch_args(
 			num_dst_deriv_channels = 3;
 			num_deriv_channels = 2;
 			break;
 		case TGSI_TEXTURE_1D:
 		case TGSI_TEXTURE_SHADOW1D:
 		case TGSI_TEXTURE_1D_ARRAY:
 		case TGSI_TEXTURE_SHADOW1D_ARRAY:
 			num_src_deriv_channels = 1;
 
 			/* 1D textures are allocated and used as 2D on GFX9. */
-			if (ctx->screen->b.chip_class >= GFX9) {
+			if (ctx->screen->info.chip_class >= GFX9) {
 				num_dst_deriv_channels = 2;
 				num_deriv_channels = 2;
 			} else {
 				num_dst_deriv_channels = 1;
 				num_deriv_channels = 1;
 			}
 			break;
 		default:
 			unreachable("invalid target");
 		}
@@ -1456,40 +1456,40 @@ static void tex_fetch_args(
 	    target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
 		ac_prepare_cube_coords(&ctx->ac,
 				       opcode == TGSI_OPCODE_TXD,
 				       target == TGSI_TEXTURE_CUBE_ARRAY ||
 				       target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
 				       opcode == TGSI_OPCODE_LODQ,
 				       coords, derivs);
 	} else if (tgsi_is_array_sampler(target) &&
 		   opcode != TGSI_OPCODE_TXF &&
 		   opcode != TGSI_OPCODE_TXF_LZ &&
-		   ctx->screen->b.chip_class <= VI) {
+		   ctx->screen->info.chip_class <= VI) {
 		unsigned array_coord = target == TGSI_TEXTURE_1D_ARRAY ? 1 : 2;
 		coords[array_coord] =
 			ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32,
 					   &coords[array_coord], 1, 0);
 	}
 
 	if (opcode == TGSI_OPCODE_TXD)
 		for (int i = 0; i < num_deriv_channels * 2; i++)
 			address[count++] = derivs[i];
 
 	/* Pack texture coordinates */
 	address[count++] = coords[0];
 	if (num_coords > 1)
 		address[count++] = coords[1];
 	if (num_coords > 2)
 		address[count++] = coords[2];
 
 	/* 1D textures are allocated and used as 2D on GFX9. */
-	if (ctx->screen->b.chip_class >= GFX9) {
+	if (ctx->screen->info.chip_class >= GFX9) {
 		LLVMValueRef filler;
 
 		/* Use 0.5, so that we don't sample the border color. */
 		if (opcode == TGSI_OPCODE_TXF ||
 		    opcode == TGSI_OPCODE_TXF_LZ)
 			filler = ctx->i32_0;
 		else
 			filler = LLVMConstReal(ctx->f32, 0.5);
 
 		if (target == TGSI_TEXTURE_1D ||
@@ -1893,21 +1893,21 @@ static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
 		args.level_zero = true;
 		break;
 	default:
 		assert(0);
 		return;
 	}
 
 	/* The hardware needs special lowering for Gather4 with integer formats. */
 	LLVMValueRef gather4_int_result_workaround = NULL;
 
-	if (ctx->screen->b.chip_class <= VI &&
+	if (ctx->screen->info.chip_class <= VI &&
 	    opcode == TGSI_OPCODE_TG4) {
 		assert(inst->Texture.ReturnType != TGSI_RETURN_TYPE_UNKNOWN);
 
 		if (inst->Texture.ReturnType == TGSI_RETURN_TYPE_SINT ||
 		    inst->Texture.ReturnType == TGSI_RETURN_TYPE_UINT) {
 			gather4_int_result_workaround =
 				si_lower_gather4_integer(ctx, &args, target,
 							 inst->Texture.ReturnType);
 		}
 	}
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
index 9c1ea91..e965fa7 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
@@ -1149,29 +1149,29 @@ void si_llvm_context_init(struct si_shader_context *ctx,
 	ctx->gallivm.module = LLVMModuleCreateWithNameInContext("tgsi",
 						ctx->gallivm.context);
 	LLVMSetTarget(ctx->gallivm.module, "amdgcn--");
 
 	LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
 	char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
 	LLVMSetDataLayout(ctx->gallivm.module, data_layout_str);
 	LLVMDisposeTargetData(data_layout);
 	LLVMDisposeMessage(data_layout_str);
 
-	bool unsafe_fpmath = (sscreen->b.debug_flags & DBG(UNSAFE_MATH)) != 0;
+	bool unsafe_fpmath = (sscreen->debug_flags & DBG(UNSAFE_MATH)) != 0;
 	enum lp_float_mode float_mode =
 		unsafe_fpmath ? LP_FLOAT_MODE_UNSAFE_FP_MATH :
 				LP_FLOAT_MODE_NO_SIGNED_ZEROS_FP_MATH;
 
 	ctx->gallivm.builder = lp_create_builder(ctx->gallivm.context,
 						 float_mode);
 
-	ac_llvm_context_init(&ctx->ac, ctx->gallivm.context, sscreen->b.chip_class);
+	ac_llvm_context_init(&ctx->ac, ctx->gallivm.context, sscreen->info.chip_class);
 	ctx->ac.module = ctx->gallivm.module;
 	ctx->ac.builder = ctx->gallivm.builder;
 
 	struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
 
 	type.floating = true;
 	type.fixed = false;
 	type.sign = true;
 	type.norm = false;
 	type.width = 32;
@@ -1312,21 +1312,21 @@ void si_llvm_create_func(struct si_shader_context *ctx,
 	ctx->return_type = ret_type;
 	main_fn_type = LLVMFunctionType(ret_type, ParamTypes, ParamCount, 0);
 	ctx->main_fn = LLVMAddFunction(ctx->gallivm.module, name, main_fn_type);
 	main_fn_body = LLVMAppendBasicBlockInContext(ctx->ac.context,
 			ctx->main_fn, "main_body");
 	LLVMPositionBuilderAtEnd(ctx->ac.builder, main_fn_body);
 
 	real_shader_type = ctx->type;
 
 	/* LS is merged into HS (TCS), and ES is merged into GS. */
-	if (ctx->screen->b.chip_class >= GFX9) {
+	if (ctx->screen->info.chip_class >= GFX9) {
 		if (ctx->shader->key.as_ls)
 			real_shader_type = PIPE_SHADER_TESS_CTRL;
 		else if (ctx->shader->key.as_es)
 			real_shader_type = PIPE_SHADER_GEOMETRY;
 	}
 
 	switch (real_shader_type) {
 	case PIPE_SHADER_VERTEX:
 	case PIPE_SHADER_TESS_EVAL:
 		call_conv = RADEON_LLVM_AMDGPU_VS;
@@ -1351,21 +1351,21 @@ void si_llvm_create_func(struct si_shader_context *ctx,
 	LLVMSetFunctionCallConv(ctx->main_fn, call_conv);
 }
 
 void si_llvm_optimize_module(struct si_shader_context *ctx)
 {
 	struct gallivm_state *gallivm = &ctx->gallivm;
 	const char *triple = LLVMGetTarget(gallivm->module);
 	LLVMTargetLibraryInfoRef target_library_info;
 
 	/* Dump LLVM IR before any optimization passes */
-	if (ctx->screen->b.debug_flags & DBG(PREOPT_IR) &&
+	if (ctx->screen->debug_flags & DBG(PREOPT_IR) &&
 	    si_can_dump_shader(ctx->screen, ctx->type))
 		LLVMDumpModule(ctx->gallivm.module);
 
 	/* Create the pass manager */
 	gallivm->passmgr = LLVMCreatePassManager();
 
 	target_library_info = gallivm_create_target_library_info(triple);
 	LLVMAddTargetLibraryInfo(target_library_info, gallivm->passmgr);
 
 	if (si_extra_shader_checks(ctx->screen, ctx->type))
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index b68dea9..5c4c383 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -131,21 +131,21 @@ static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *a
 				  blend->blend_enable_4bit & cb_target_mask &&
 				  sctx->framebuffer.nr_samples >= 2;
 
 		radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
 				       S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
 				       S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
 				       S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
 	}
 
 	/* RB+ register settings. */
-	if (sctx->screen->b.rbplus_allowed) {
+	if (sctx->screen->rbplus_allowed) {
 		unsigned spi_shader_col_format =
 			sctx->ps_shader.cso ?
 			sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
 		unsigned sx_ps_downconvert = 0;
 		unsigned sx_blend_opt_epsilon = 0;
 		unsigned sx_blend_opt_control = 0;
 
 		for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
 			struct r600_surface *surf =
 				(struct r600_surface*)sctx->framebuffer.state.cbufs[i];
@@ -259,21 +259,21 @@ static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *a
 					sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
 				}
 				break;
 			}
 		}
 
 		radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
 		radeon_emit(cs, sx_ps_downconvert);	/* R_028754_SX_PS_DOWNCONVERT */
 		radeon_emit(cs, sx_blend_opt_epsilon);	/* R_028758_SX_BLEND_OPT_EPSILON */
 		radeon_emit(cs, sx_blend_opt_control);	/* R_02875C_SX_BLEND_OPT_CONTROL */
-	} else if (sctx->screen->b.has_rbplus) {
+	} else if (sctx->screen->has_rbplus) {
 		radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
 		radeon_emit(cs, 0);	/* R_028754_SX_PS_DOWNCONVERT */
 		radeon_emit(cs, 0);	/* R_028758_SX_BLEND_OPT_EPSILON */
 		radeon_emit(cs, 0);	/* R_02875C_SX_BLEND_OPT_CONTROL */
 	}
 }
 
 /*
  * Blender functions
  */
@@ -622,21 +622,21 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx,
 		    dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
 			blend->need_src_alpha_4bit |= 0xfu << (i * 4);
 	}
 
 	if (blend->cb_target_mask) {
 		color_control |= S_028808_MODE(mode);
 	} else {
 		color_control |= S_028808_MODE(V_028808_CB_DISABLE);
 	}
 
-	if (sctx->screen->b.has_rbplus) {
+	if (sctx->screen->has_rbplus) {
 		/* Disable RB+ blend optimizations for dual source blending.
 		 * Vulkan does this.
 		 */
 		if (blend->dual_src_blend) {
 			for (int i = 0; i < 8; i++) {
 				sx_mrt_blend_opt[i] =
 					S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
 					S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
 			}
 		}
@@ -670,21 +670,21 @@ static void si_bind_blend_state(struct pipe_context *ctx, void *state)
 	if (!state)
 		return;
 
 	si_pm4_bind_state(sctx, blend, state);
 
 	if (!old_blend ||
 	    old_blend->cb_target_mask != blend->cb_target_mask ||
 	    old_blend->dual_src_blend != blend->dual_src_blend ||
 	    (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
 	     sctx->framebuffer.nr_samples >= 2 &&
-	     sctx->screen->b.dcc_msaa_allowed))
+	     sctx->screen->dcc_msaa_allowed))
 		si_mark_atom_dirty(sctx, &sctx->cb_render_state);
 
 	if (!old_blend ||
 	    old_blend->cb_target_mask != blend->cb_target_mask ||
 	    old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
 	    old_blend->alpha_to_one != blend->alpha_to_one ||
 	    old_blend->dual_src_blend != blend->dual_src_blend ||
 	    old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
 	    old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
 		sctx->do_update_shaders = true;
@@ -923,21 +923,21 @@ static void *si_create_rs_state(struct pipe_context *ctx,
 			S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
 
 	si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
 		       S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
 	si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
 		       S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
 		       S_028A48_MSAA_ENABLE(state->multisample ||
 					    state->poly_smooth ||
 					    state->line_smooth) |
 		       S_028A48_VPORT_SCISSOR_ENABLE(1) |
-		       S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->b.chip_class >= GFX9));
+		       S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
 
 	si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
 		       S_028BE4_PIX_CENTER(state->half_pixel_center) |
 		       S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
 
 	si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
 	si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
 		S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
 		S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
 		S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
@@ -1434,22 +1434,22 @@ static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *s
 	/* Bug workaround for smoothing (overrasterization) on SI. */
 	if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
 		db_shader_control &= C_02880C_Z_ORDER;
 		db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
 	}
 
 	/* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
 	if (!rs || !rs->multisample_enable)
 		db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
 
-	if (sctx->screen->b.has_rbplus &&
-	    !sctx->screen->b.rbplus_allowed)
+	if (sctx->screen->has_rbplus &&
+	    !sctx->screen->rbplus_allowed)
 		db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
 
 	radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
 			       db_shader_control);
 }
 
 /*
  * format translation
  */
 static uint32_t si_translate_colorformat(enum pipe_format format)
@@ -1596,23 +1596,23 @@ static uint32_t si_translate_dbformat(enum pipe_format format)
 /*
  * Texture translation
  */
 
 static uint32_t si_translate_texformat(struct pipe_screen *screen,
 				       enum pipe_format format,
 				       const struct util_format_description *desc,
 				       int first_non_void)
 {
 	struct si_screen *sscreen = (struct si_screen*)screen;
-	bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
-					  sscreen->b.info.drm_minor >= 31) ||
-					 sscreen->b.info.drm_major == 3;
+	bool enable_compressed_formats = (sscreen->info.drm_major == 2 &&
+					  sscreen->info.drm_minor >= 31) ||
+					 sscreen->info.drm_major == 3;
 	bool uniform = true;
 	int i;
 
 	/* Colorspace (return non-RGB formats directly). */
 	switch (desc->colorspace) {
 	/* Depth stencil formats */
 	case UTIL_FORMAT_COLORSPACE_ZS:
 		switch (format) {
 		case PIPE_FORMAT_Z16_UNORM:
 			return V_008F14_IMG_DATA_FORMAT_16;
@@ -1667,22 +1667,22 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen,
 		case PIPE_FORMAT_LATC2_SNORM:
 		case PIPE_FORMAT_RGTC2_UNORM:
 		case PIPE_FORMAT_LATC2_UNORM:
 			return V_008F14_IMG_DATA_FORMAT_BC5;
 		default:
 			goto out_unknown;
 		}
 	}
 
 	if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
-	    (sscreen->b.family == CHIP_STONEY ||
-	     sscreen->b.chip_class >= GFX9)) {
+	    (sscreen->info.family == CHIP_STONEY ||
+	     sscreen->info.chip_class >= GFX9)) {
 		switch (format) {
 		case PIPE_FORMAT_ETC1_RGB8:
 		case PIPE_FORMAT_ETC2_RGB8:
 		case PIPE_FORMAT_ETC2_SRGB8:
 			return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
 		case PIPE_FORMAT_ETC2_RGB8A1:
 		case PIPE_FORMAT_ETC2_SRGB8A1:
 			return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
 		case PIPE_FORMAT_ETC2_RGBA8:
 		case PIPE_FORMAT_ETC2_SRGBA8:
@@ -1923,21 +1923,21 @@ static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
 	    view_target == PIPE_TEXTURE_CUBE_ARRAY)
 		res_target = view_target;
 	/* If interpreting cubemaps as something else, set 2D_ARRAY. */
 	else if (res_target == PIPE_TEXTURE_CUBE ||
 		 res_target == PIPE_TEXTURE_CUBE_ARRAY)
 		res_target = PIPE_TEXTURE_2D_ARRAY;
 
 	/* GFX9 allocates 1D textures as 2D. */
 	if ((res_target == PIPE_TEXTURE_1D ||
 	     res_target == PIPE_TEXTURE_1D_ARRAY) &&
-	    sscreen->b.chip_class >= GFX9 &&
+	    sscreen->info.chip_class >= GFX9 &&
 	    rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
 		if (res_target == PIPE_TEXTURE_1D)
 			res_target = PIPE_TEXTURE_2D;
 		else
 			res_target = PIPE_TEXTURE_2D_ARRAY;
 	}
 
 	switch (res_target) {
 	default:
 	case PIPE_TEXTURE_1D:
@@ -2573,21 +2573,21 @@ static void si_init_depth_surface(struct si_context *sctx,
 				       rtex->surface.u.legacy.level[level].offset) >> 8;
 		surf->db_stencil_base = (rtex->resource.gpu_address +
 					 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
 
 		z_info = S_028040_FORMAT(format) |
 			 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
 		s_info = S_028044_FORMAT(stencil_format);
 		surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
 
 		if (sctx->b.chip_class >= CIK) {
-			struct radeon_info *info = &sctx->screen->b.info;
+			struct radeon_info *info = &sctx->screen->info;
 			unsigned index = rtex->surface.u.legacy.tiling_index[level];
 			unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
 			unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
 			unsigned tile_mode = info->si_tile_mode_array[index];
 			unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
 			unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
 
 			surf->db_depth_info |=
 				S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
 				S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
@@ -3303,21 +3303,21 @@ static bool si_out_of_order_rasterization(struct si_context *sctx)
 		if (!dsa_order_invariant.pass_last)
 			return false;
 	}
 
 	return true;
 }
 
 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
 {
 	struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
-	unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
+	unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
 	/* 33% faster rendering to linear color buffers */
 	bool dst_is_linear = sctx->framebuffer.any_dst_linear;
 	bool out_of_order_rast = si_out_of_order_rasterization(sctx);
 	unsigned sc_mode_cntl_1 =
 		S_028A4C_WALK_SIZE(dst_is_linear) |
 		S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
 		S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
 		S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
 		S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
 		/* always 1: */
@@ -3430,22 +3430,22 @@ si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
 {
 	const struct util_format_description *desc;
 	int first_non_void;
 	unsigned stride;
 	unsigned num_records;
 	unsigned num_format, data_format;
 
 	desc = util_format_description(format);
 	first_non_void = util_format_get_first_non_void_channel(format);
 	stride = desc->block.bits / 8;
-	num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
-	data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
+	num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
+	data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
 
 	num_records = size / stride;
 	num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
 
 	/* The NUM_RECORDS field has a different meaning depending on the chip,
 	 * instruction type, STRIDE, and SWIZZLE_ENABLE.
 	 *
 	 * SI-CIK:
 	 * - If STRIDE == 0, it's in byte units.
 	 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
@@ -3459,31 +3459,31 @@ si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
 	 *       ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
 	 *       using SMEM. This can be done in the shader by clearing STRIDE with s_and.
 	 *       That way the same descriptor can be used by both SMEM and VMEM.
 	 *
 	 * GFX9:
 	 * - For SMEM and STRIDE == 0, it's in byte units.
 	 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
 	 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
 	 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
 	 */
-	if (screen->b.chip_class >= GFX9)
+	if (screen->info.chip_class >= GFX9)
 		/* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
 		 * from STRIDE to bytes. This works around it by setting
 		 * NUM_RECORDS to at least the size of one element, so that
 		 * the first element is readable when IDXEN == 0.
 		 *
 		 * TODO: Fix this in LLVM, but do we need a new intrinsic where
 		 *       IDXEN is enforced?
 		 */
 		num_records = num_records ? MAX2(num_records, stride) : 0;
-	else if (screen->b.chip_class == VI)
+	else if (screen->info.chip_class == VI)
 		num_records *= stride;
 
 	state[4] = 0;
 	state[5] = S_008F04_STRIDE(stride);
 	state[6] = num_records;
 	state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
 		   S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
 		   S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
 		   S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
 		   S_008F0C_NUM_FORMAT(num_format) |
@@ -3631,35 +3631,35 @@ si_make_texture_descriptor(struct si_screen *screen,
 				if (desc->channel[first_non_void].normalized)
 					num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
 				else if (desc->channel[first_non_void].pure_integer)
 					num_format = V_008F14_IMG_NUM_FORMAT_UINT;
 				else
 					num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
 			}
 		}
 	}
 
-	data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
+	data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
 	if (data_format == ~0) {
 		data_format = 0;
 	}
 
 	/* S8 with Z32 HTILE needs a special format. */
-	if (screen->b.chip_class >= GFX9 &&
+	if (screen->info.chip_class >= GFX9 &&
 	    pipe_format == PIPE_FORMAT_S8_UINT &&
 	    tex->tc_compatible_htile)
 		data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
 
 	if (!sampler &&
 	    (res->target == PIPE_TEXTURE_CUBE ||
 	     res->target == PIPE_TEXTURE_CUBE_ARRAY ||
-	     (screen->b.chip_class <= VI &&
+	     (screen->info.chip_class <= VI &&
 	      res->target == PIPE_TEXTURE_3D))) {
 		/* For the purpose of shader images, treat cube maps and 3D
 		 * textures as 2D arrays. For 3D textures, the address
 		 * calculations for mipmaps are different, so we rely on the
 		 * caller to effectively disable mipmaps.
 		 */
 		type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
 
 		assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
 	} else {
@@ -3690,21 +3690,21 @@ si_make_texture_descriptor(struct si_screen *screen,
 					0 : first_level) |
 		    S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
 					util_logbase2(res->nr_samples) :
 					last_level) |
 		    S_008F1C_TYPE(type));
 	state[4] = 0;
 	state[5] = S_008F24_BASE_ARRAY(first_layer);
 	state[6] = 0;
 	state[7] = 0;
 
-	if (screen->b.chip_class >= GFX9) {
+	if (screen->info.chip_class >= GFX9) {
 		unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
 
 		/* Depth is the the last accessible layer on Gfx9.
 		 * The hw doesn't need to know the total number of layers.
 		 */
 		if (type == V_008F1C_SQ_RSRC_IMG_3D)
 			state[4] |= S_008F20_DEPTH(depth - 1);
 		else
 			state[4] |= S_008F20_DEPTH(last_layer);
 
@@ -3719,35 +3719,35 @@ si_make_texture_descriptor(struct si_screen *screen,
 	}
 
 	if (tex->dcc_offset) {
 		unsigned swap = si_translate_colorswap(pipe_format, false);
 
 		state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
 	} else {
 		/* The last dword is unused by hw. The shader uses it to clear
 		 * bits in the first dword of sampler state.
 		 */
-		if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
+		if (screen->info.chip_class <= CIK && res->nr_samples <= 1) {
 			if (first_level == last_level)
 				state[7] = C_008F30_MAX_ANISO_RATIO;
 			else
 				state[7] = 0xffffffff;
 		}
 	}
 
 	/* Initialize the sampler view for FMASK. */
 	if (tex->fmask.size) {
 		uint32_t data_format, num_format;
 
 		va = tex->resource.gpu_address + tex->fmask.offset;
 
-		if (screen->b.chip_class >= GFX9) {
+		if (screen->info.chip_class >= GFX9) {
 			data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
 			switch (res->nr_samples) {
 			case 2:
 				num_format = V_008F14_IMG_FMASK_8_2_2;
 				break;
 			case 4:
 				num_format = V_008F14_IMG_FMASK_8_4_4;
 				break;
 			case 8:
 				num_format = V_008F14_IMG_FMASK_32_8_8;
@@ -3781,21 +3781,21 @@ si_make_texture_descriptor(struct si_screen *screen,
 		fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
 				 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
 				 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
 				 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
 				 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
 		fmask_state[4] = 0;
 		fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
 		fmask_state[6] = 0;
 		fmask_state[7] = 0;
 
-		if (screen->b.chip_class >= GFX9) {
+		if (screen->info.chip_class >= GFX9) {
 			fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
 			fmask_state[4] |= S_008F20_DEPTH(last_layer) |
 					  S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
 			fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
 					  S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
 		} else {
 			fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
 			fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
 					  S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
 			fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
@@ -4078,23 +4078,23 @@ static inline unsigned si_tex_aniso_filter(unsigned filter)
 		return 2;
 	if (filter < 16)
 		return 3;
 	return 4;
 }
 
 static void *si_create_sampler_state(struct pipe_context *ctx,
 				     const struct pipe_sampler_state *state)
 {
 	struct si_context *sctx = (struct si_context *)ctx;
-	struct r600_common_screen *rscreen = sctx->b.screen;
+	struct si_screen *sscreen = sctx->screen;
 	struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
-	unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
+	unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
 						       : state->max_anisotropy;
 	unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
 	union pipe_color_union clamped_border_color;
 
 	if (!rstate) {
 		return NULL;
 	}
 
 #ifdef DEBUG
 	rstate->magic = SI_SAMPLER_STATE_MAGIC;
@@ -4241,22 +4241,22 @@ static void *si_create_vertex_elements(struct pipe_context *ctx,
 
 		v->format_size[i] = desc->block.bits / 8;
 		v->src_offset[i] = elements[i].src_offset;
 		v->vertex_buffer_index[i] = vbo_index;
 
 		/* The hardware always treats the 2-bit alpha channel as
 		 * unsigned, so a shader workaround is needed. The affected
 		 * chips are VI and older except Stoney (GFX8.1).
 		 */
 		if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
-		    sscreen->b.chip_class <= VI &&
-		    sscreen->b.family != CHIP_STONEY) {
+		    sscreen->info.chip_class <= VI &&
+		    sscreen->info.family != CHIP_STONEY) {
 			if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
 				v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
 			} else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
 				v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
 			} else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
 				/* This isn't actually used in OpenGL. */
 				v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
 			}
 		} else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
 			if (desc->swizzle[3] == PIPE_SWIZZLE_1)
@@ -4468,38 +4468,38 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
 		/* As far as I can tell, L1 contents are written back to L2
 		 * automatically at end of shader, but the contents of other
 		 * L1 caches might still be stale. */
 		sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
 	}
 
 	if (flags & PIPE_BARRIER_INDEX_BUFFER) {
 		/* Indices are read through TC L2 since VI.
 		 * L1 isn't used.
 		 */
-		if (sctx->screen->b.chip_class <= CIK)
+		if (sctx->screen->info.chip_class <= CIK)
 			sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
 	}
 
 	/* MSAA color, any depth and any stencil are flushed in
 	 * si_decompress_textures when needed.
 	 */
 	if (flags & PIPE_BARRIER_FRAMEBUFFER &&
 	    sctx->framebuffer.nr_samples <= 1 &&
 	    sctx->framebuffer.state.nr_cbufs) {
 		sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
 
 		if (sctx->b.chip_class <= VI)
 			sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
 	}
 
 	/* Indirect buffers use TC L2 on GFX9, but not older hw. */
-	if (sctx->screen->b.chip_class <= VI &&
+	if (sctx->screen->info.chip_class <= VI &&
 	    flags & PIPE_BARRIER_INDIRECT_BUFFER)
 		sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
 }
 
 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
 {
 	struct pipe_blend_state blend;
 
 	memset(&blend, 0, sizeof(blend));
 	blend.independent_blend_enable = true;
@@ -4582,52 +4582,52 @@ void si_init_state_functions(struct si_context *sctx)
 	sctx->b.save_qbo_state = si_save_qbo_state;
 	sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
 
 	sctx->b.b.draw_vbo = si_draw_vbo;
 
 	si_init_config(sctx);
 }
 
 void si_init_screen_state_functions(struct si_screen *sscreen)
 {
-	sscreen->b.b.is_format_supported = si_is_format_supported;
+	sscreen->b.is_format_supported = si_is_format_supported;
 }
 
 static void si_set_grbm_gfx_index(struct si_context *sctx,
 				  struct si_pm4_state *pm4,  unsigned value)
 {
 	unsigned reg = sctx->b.chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
 						   R_00802C_GRBM_GFX_INDEX;
 	si_pm4_set_reg(pm4, reg, value);
 }
 
 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
 				     struct si_pm4_state *pm4, unsigned se)
 {
-	assert(se == ~0 || se < sctx->screen->b.info.max_se);
+	assert(se == ~0 || se < sctx->screen->info.max_se);
 	si_set_grbm_gfx_index(sctx, pm4,
 			      (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
 					  S_030800_SE_INDEX(se)) |
 			      S_030800_SH_BROADCAST_WRITES(1) |
 			      S_030800_INSTANCE_BROADCAST_WRITES(1));
 }
 
 static void
 si_write_harvested_raster_configs(struct si_context *sctx,
 				  struct si_pm4_state *pm4,
 				  unsigned raster_config,
 				  unsigned raster_config_1)
 {
-	unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
-	unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
-	unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
-	unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
+	unsigned sh_per_se = MAX2(sctx->screen->info.max_sh_per_se, 1);
+	unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
+	unsigned rb_mask = sctx->screen->info.enabled_rb_mask;
+	unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16);
 	unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
 	unsigned rb_per_se = num_rb / num_se;
 	unsigned se_mask[4];
 	unsigned se;
 
 	se_mask[0] = ((1 << rb_per_se) - 1);
 	se_mask[1] = (se_mask[0] << rb_per_se);
 	se_mask[2] = (se_mask[1] << rb_per_se);
 	se_mask[3] = (se_mask[2] << rb_per_se);
 
@@ -4732,22 +4732,22 @@ si_write_harvested_raster_configs(struct si_context *sctx,
 			}
 		}
 
 		si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
 	}
 }
 
 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
 {
 	struct si_screen *sscreen = sctx->screen;
-	unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
-	unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
+	unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16);
+	unsigned rb_mask = sctx->screen->info.enabled_rb_mask;
 	unsigned raster_config, raster_config_1;
 
 	switch (sctx->b.family) {
 	case CHIP_TAHITI:
 	case CHIP_PITCAIRN:
 		raster_config = 0x2a00126a;
 		raster_config_1 = 0x00000000;
 		break;
 	case CHIP_VERDE:
 		raster_config = 0x0000124a;
@@ -4763,21 +4763,21 @@ static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *p
 		break;
 	case CHIP_BONAIRE:
 		raster_config = 0x16000012;
 		raster_config_1 = 0x00000000;
 		break;
 	case CHIP_HAWAII:
 		raster_config = 0x3a00161a;
 		raster_config_1 = 0x0000002e;
 		break;
 	case CHIP_FIJI:
-		if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
+		if (sscreen->info.cik_macrotile_mode_array[0] == 0x000000e8) {
 			/* old kernels with old tiling config */
 			raster_config = 0x16000012;
 			raster_config_1 = 0x0000002a;
 		} else {
 			raster_config = 0x3a00161a;
 			raster_config_1 = 0x0000002e;
 		}
 		break;
 	case CHIP_POLARIS10:
 		raster_config = 0x16000012;
@@ -4836,21 +4836,21 @@ static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *p
 }
 
 static void si_init_config(struct si_context *sctx)
 {
 	struct si_screen *sscreen = sctx->screen;
 	uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
 	bool has_clear_state = sscreen->has_clear_state;
 	struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
 
 	/* Only SI can disable CLEAR_STATE for now. */
-	assert(has_clear_state || sscreen->b.chip_class == SI);
+	assert(has_clear_state || sscreen->info.chip_class == SI);
 
 	if (!pm4)
 		return;
 
 	si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
 	si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
 	si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
 	si_pm4_cmd_end(pm4, false);
 
 	if (has_clear_state) {
@@ -4956,23 +4956,23 @@ static void si_init_config(struct si_context *sctx)
 			 * but we don't use on-chip GS.
 			 */
 			si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
 				       S_028A44_ES_VERTS_PER_SUBGRP(64) |
 				       S_028A44_GS_PRIMS_PER_SUBGRP(4));
 		}
 		si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
 			       S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
 
 		/* Compute LATE_ALLOC_VS.LIMIT. */
-		unsigned num_cu_per_sh = sscreen->b.info.num_good_compute_units /
-					 (sscreen->b.info.max_se *
-					  sscreen->b.info.max_sh_per_se);
+		unsigned num_cu_per_sh = sscreen->info.num_good_compute_units /
+					 (sscreen->info.max_se *
+					  sscreen->info.max_sh_per_se);
 		unsigned late_alloc_limit; /* The limit is per SH. */
 
 		if (sctx->b.family == CHIP_KABINI) {
 			late_alloc_limit = 0; /* Potential hang on Kabini. */
 		} else if (num_cu_per_sh <= 4) {
 			/* Too few available compute units per SH. Disallowing
 			 * VS to run on one CU could hurt us more than late VS
 			 * allocation would help.
 			 *
 			 * 2 is the highest safe number that allows us to keep
@@ -5022,21 +5022,21 @@ static void si_init_config(struct si_context *sctx)
 		si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
 	}
 
 	si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
 	if (sctx->b.chip_class >= CIK)
 		si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
 	si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
 		      RADEON_PRIO_BORDER_COLORS);
 
 	if (sctx->b.chip_class >= GFX9) {
-		unsigned num_se = sscreen->b.info.max_se;
+		unsigned num_se = sscreen->info.max_se;
 		unsigned pc_lines = 0;
 
 		switch (sctx->b.family) {
 		case CHIP_VEGA10:
 			pc_lines = 4096;
 			break;
 		case CHIP_RAVEN:
 			pc_lines = 1024;
 			break;
 		default:
diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c
index 8d98d6d..686701d 100644
--- a/src/gallium/drivers/radeonsi/si_state_binning.c
+++ b/src/gallium/drivers/radeonsi/si_state_binning.c
@@ -39,23 +39,23 @@ struct si_bin_size_map {
 };
 
 typedef struct si_bin_size_map si_bin_size_subtable[3][9];
 
 /* Find the bin size where sum is >= table[i].start and < table[i + 1].start. */
 static struct uvec2 si_find_bin_size(struct si_screen *sscreen,
 				     const si_bin_size_subtable table[],
 				     unsigned sum)
 {
 	unsigned log_num_rb_per_se =
-		util_logbase2_ceil(sscreen->b.info.num_render_backends /
-				   sscreen->b.info.max_se);
-	unsigned log_num_se = util_logbase2_ceil(sscreen->b.info.max_se);
+		util_logbase2_ceil(sscreen->info.num_render_backends /
+				   sscreen->info.max_se);
+	unsigned log_num_se = util_logbase2_ceil(sscreen->info.max_se);
 	unsigned i;
 
 	/* Get the chip-specific subtable. */
 	const struct si_bin_size_map *subtable =
 		&table[log_num_rb_per_se][log_num_se][0];
 
 	for (i = 0; subtable[i].start != UINT_MAX; i++) {
 		if (sum >= subtable[i].start && sum < subtable[i + 1].start)
 			break;
 	}
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 7330bf4..06ef84d 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -334,124 +334,124 @@ si_get_init_multi_vgt_param(struct si_screen *sscreen,
 	bool ia_switch_on_eoi = false;
 	bool partial_vs_wave = false;
 	bool partial_es_wave = false;
 
 	if (key->u.uses_tess) {
 		/* SWITCH_ON_EOI must be set if PrimID is used. */
 		if (key->u.tess_uses_prim_id)
 			ia_switch_on_eoi = true;
 
 		/* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
-		if ((sscreen->b.family == CHIP_TAHITI ||
-		     sscreen->b.family == CHIP_PITCAIRN ||
-		     sscreen->b.family == CHIP_BONAIRE) &&
+		if ((sscreen->info.family == CHIP_TAHITI ||
+		     sscreen->info.family == CHIP_PITCAIRN ||
+		     sscreen->info.family == CHIP_BONAIRE) &&
 		    key->u.uses_gs)
 			partial_vs_wave = true;
 
 		/* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
 		if (sscreen->has_distributed_tess) {
 			if (key->u.uses_gs) {
-				if (sscreen->b.chip_class <= VI)
+				if (sscreen->info.chip_class <= VI)
 					partial_es_wave = true;
 
 				/* GPU hang workaround. */
-				if (sscreen->b.family == CHIP_TONGA ||
-				    sscreen->b.family == CHIP_FIJI ||
-				    sscreen->b.family == CHIP_POLARIS10 ||
-				    sscreen->b.family == CHIP_POLARIS11 ||
-				    sscreen->b.family == CHIP_POLARIS12)
+				if (sscreen->info.family == CHIP_TONGA ||
+				    sscreen->info.family == CHIP_FIJI ||
+				    sscreen->info.family == CHIP_POLARIS10 ||
+				    sscreen->info.family == CHIP_POLARIS11 ||
+				    sscreen->info.family == CHIP_POLARIS12)
 					partial_vs_wave = true;
 			} else {
 				partial_vs_wave = true;
 			}
 		}
 	}
 
 	/* This is a hardware requirement. */
 	if (key->u.line_stipple_enabled ||
-	    (sscreen->b.debug_flags & DBG(SWITCH_ON_EOP))) {
+	    (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
 		ia_switch_on_eop = true;
 		wd_switch_on_eop = true;
 	}
 
-	if (sscreen->b.chip_class >= CIK) {
+	if (sscreen->info.chip_class >= CIK) {
 		/* WD_SWITCH_ON_EOP has no effect on GPUs with less than
 		 * 4 shader engines. Set 1 to pass the assertion below.
 		 * The other cases are hardware requirements.
 		 *
 		 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
 		 * for points, line strips, and tri strips.
 		 */
-		if (sscreen->b.info.max_se < 4 ||
+		if (sscreen->info.max_se < 4 ||
 		    key->u.prim == PIPE_PRIM_POLYGON ||
 		    key->u.prim == PIPE_PRIM_LINE_LOOP ||
 		    key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
 		    key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
 		    (key->u.primitive_restart &&
-		     (sscreen->b.family < CHIP_POLARIS10 ||
+		     (sscreen->info.family < CHIP_POLARIS10 ||
 		      (key->u.prim != PIPE_PRIM_POINTS &&
 		       key->u.prim != PIPE_PRIM_LINE_STRIP &&
 		       key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
 		    key->u.count_from_stream_output)
 			wd_switch_on_eop = true;
 
 		/* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
 		 * We don't know that for indirect drawing, so treat it as
 		 * always problematic. */
-		if (sscreen->b.family == CHIP_HAWAII &&
+		if (sscreen->info.family == CHIP_HAWAII &&
 		    key->u.uses_instancing)
 			wd_switch_on_eop = true;
 
 		/* Performance recommendation for 4 SE Gfx7-8 parts if
 		 * instances are smaller than a primgroup.
 		 * Assume indirect draws always use small instances.
 		 * This is needed for good VS wave utilization.
 		 */
-		if (sscreen->b.chip_class <= VI &&
-		    sscreen->b.info.max_se == 4 &&
+		if (sscreen->info.chip_class <= VI &&
+		    sscreen->info.max_se == 4 &&
 		    key->u.multi_instances_smaller_than_primgroup)
 			wd_switch_on_eop = true;
 
 		/* Required on CIK and later. */
-		if (sscreen->b.info.max_se > 2 && !wd_switch_on_eop)
+		if (sscreen->info.max_se > 2 && !wd_switch_on_eop)
 			ia_switch_on_eoi = true;
 
 		/* Required by Hawaii and, for some special cases, by VI. */
 		if (ia_switch_on_eoi &&
-		    (sscreen->b.family == CHIP_HAWAII ||
-		     (sscreen->b.chip_class == VI &&
+		    (sscreen->info.family == CHIP_HAWAII ||
+		     (sscreen->info.chip_class == VI &&
 		      (key->u.uses_gs || max_primgroup_in_wave != 2))))
 			partial_vs_wave = true;
 
 		/* Instancing bug on Bonaire. */
-		if (sscreen->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
+		if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
 		    key->u.uses_instancing)
 			partial_vs_wave = true;
 
 		/* If the WD switch is false, the IA switch must be false too. */
 		assert(wd_switch_on_eop || !ia_switch_on_eop);
 	}
 
 	/* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
-	if (sscreen->b.chip_class <= VI && ia_switch_on_eoi)
+	if (sscreen->info.chip_class <= VI && ia_switch_on_eoi)
 		partial_es_wave = true;
 
 	return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
 		S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
 		S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
 		S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
-		S_028AA8_WD_SWITCH_ON_EOP(sscreen->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
+		S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= CIK ? wd_switch_on_eop : 0) |
 		/* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
-		S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->b.chip_class == VI ?
+		S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == VI ?
 					     max_primgroup_in_wave : 0) |
-		S_030960_EN_INST_OPT_BASIC(sscreen->b.chip_class >= GFX9) |
-		S_030960_EN_INST_OPT_ADV(sscreen->b.chip_class >= GFX9);
+		S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
+		S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
 }
 
 void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
 {
 	for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
 	for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
 	for (int multi_instances = 0; multi_instances < 2; multi_instances++)
 	for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
 	for (int count_from_so = 0; count_from_so < 2; count_from_so++)
 	for (int line_stipple = 0; line_stipple < 2; line_stipple++)
@@ -1354,21 +1354,21 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 			index_size = 2;
 		} else if (info->has_user_indices) {
 			unsigned start_offset;
 
 			assert(!info->indirect);
 			start_offset = info->start * index_size;
 
 			indexbuf = NULL;
 			u_upload_data(ctx->stream_uploader, start_offset,
 				      info->count * index_size,
-				      sctx->screen->b.info.tcc_cache_line_size,
+				      sctx->screen->info.tcc_cache_line_size,
 				      (char*)info->index.user + start_offset,
 				      &index_offset, &indexbuf);
 			if (!indexbuf)
 				return;
 
 			/* info->start will be added by the drawing code */
 			index_offset -= start_offset;
 		} else if (sctx->b.chip_class <= CIK &&
 			   r600_resource(indexbuf)->TC_L2_dirty) {
 			/* VI reads index buffers through TC L2, so it doesn't
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 5395530..461760f 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -199,61 +199,61 @@ static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
 	hw_binary = si_get_shader_binary(shader);
 	if (!hw_binary)
 		return false;
 
 	if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
 				    hw_binary) == NULL) {
 		FREE(hw_binary);
 		return false;
 	}
 
-	if (sscreen->b.disk_shader_cache && insert_into_disk_cache) {
-		disk_cache_compute_key(sscreen->b.disk_shader_cache, tgsi_binary,
+	if (sscreen->disk_shader_cache && insert_into_disk_cache) {
+		disk_cache_compute_key(sscreen->disk_shader_cache, tgsi_binary,
 				       *((uint32_t *)tgsi_binary), key);
-		disk_cache_put(sscreen->b.disk_shader_cache, key, hw_binary,
+		disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
 			       *((uint32_t *) hw_binary), NULL);
 	}
 
 	return true;
 }
 
 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
 					void *tgsi_binary,
 				        struct si_shader *shader)
 {
 	struct hash_entry *entry =
 		_mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
 	if (!entry) {
-		if (sscreen->b.disk_shader_cache) {
+		if (sscreen->disk_shader_cache) {
 			unsigned char sha1[CACHE_KEY_SIZE];
 			size_t tg_size = *((uint32_t *) tgsi_binary);
 
-			disk_cache_compute_key(sscreen->b.disk_shader_cache,
+			disk_cache_compute_key(sscreen->disk_shader_cache,
 					       tgsi_binary, tg_size, sha1);
 
 			size_t binary_size;
 			uint8_t *buffer =
-				disk_cache_get(sscreen->b.disk_shader_cache,
+				disk_cache_get(sscreen->disk_shader_cache,
 					       sha1, &binary_size);
 			if (!buffer)
 				return false;
 
 			if (binary_size < sizeof(uint32_t) ||
 			    *((uint32_t*)buffer) != binary_size) {
 				 /* Something has gone wrong discard the item
 				  * from the cache and rebuild/link from
 				  * source.
 				  */
 				assert(!"Invalid radeonsi shader disk cache "
 				       "item!");
 
-				disk_cache_remove(sscreen->b.disk_shader_cache,
+				disk_cache_remove(sscreen->disk_shader_cache,
 						  sha1);
 				free(buffer);
 
 				return false;
 			}
 
 			if (!si_load_shader_binary(shader, buffer)) {
 				free(buffer);
 				return false;
 			}
@@ -264,21 +264,21 @@ static bool si_shader_cache_load_shader(struct si_screen *sscreen,
 				FREE(tgsi_binary);
 		} else {
 			return false;
 		}
 	} else {
 		if (si_load_shader_binary(shader, entry->data))
 			FREE(tgsi_binary);
 		else
 			return false;
 	}
-	p_atomic_inc(&sscreen->b.num_shader_cache_hits);
+	p_atomic_inc(&sscreen->num_shader_cache_hits);
 	return true;
 }
 
 static uint32_t si_shader_cache_key_hash(const void *key)
 {
 	/* The first dword is the key size. */
 	return util_hash_crc32(key, *(uint32_t*)key);
 }
 
 static bool si_shader_cache_key_equals(const void *a, const void *b)
@@ -365,22 +365,22 @@ static void si_set_tesseval_regs(struct si_screen *sscreen,
 		topology = V_028B6C_OUTPUT_POINT;
 	else if (tes_prim_mode == PIPE_PRIM_LINES)
 		topology = V_028B6C_OUTPUT_LINE;
 	else if (tes_vertex_order_cw)
 		/* for some reason, this must be the other way around */
 		topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
 	else
 		topology = V_028B6C_OUTPUT_TRIANGLE_CW;
 
 	if (sscreen->has_distributed_tess) {
-		if (sscreen->b.family == CHIP_FIJI ||
-		    sscreen->b.family >= CHIP_POLARIS10)
+		if (sscreen->info.family == CHIP_FIJI ||
+		    sscreen->info.family >= CHIP_POLARIS10)
 			distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
 		else
 			distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
 	} else
 		distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
 
 	si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
 		       S_028B6C_TYPE(type) |
 		       S_028B6C_PARTITIONING(partitioning) |
 		       S_028B6C_TOPOLOGY(topology) |
@@ -401,21 +401,21 @@ static void si_set_tesseval_regs(struct si_screen *sscreen,
  *
  * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
  */
 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
 					 struct si_shader_selector *sel,
 					 struct si_shader *shader,
 					 struct si_pm4_state *pm4)
 {
 	unsigned type = sel->type;
 
-	if (sscreen->b.family < CHIP_POLARIS10)
+	if (sscreen->info.family < CHIP_POLARIS10)
 		return;
 
 	/* VS as VS, or VS as ES: */
 	if ((type == PIPE_SHADER_VERTEX &&
 	     (!shader ||
 	      (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
 	    /* TES as VS, or TES as ES: */
 	    type == PIPE_SHADER_TESS_EVAL) {
 		unsigned vtx_reuse_depth = 30;
 
@@ -438,21 +438,21 @@ static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
 
 	return shader->pm4;
 }
 
 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
 {
 	struct si_pm4_state *pm4;
 	unsigned vgpr_comp_cnt;
 	uint64_t va;
 
-	assert(sscreen->b.chip_class <= VI);
+	assert(sscreen->info.chip_class <= VI);
 
 	pm4 = si_get_shader_pm4_state(shader);
 	if (!pm4)
 		return;
 
 	va = shader->bo->gpu_address;
 	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
 
 	/* We need at least 2 components for LS.
 	 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
@@ -478,21 +478,21 @@ static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
 	uint64_t va;
 	unsigned ls_vgpr_comp_cnt = 0;
 
 	pm4 = si_get_shader_pm4_state(shader);
 	if (!pm4)
 		return;
 
 	va = shader->bo->gpu_address;
 	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
 
-	if (sscreen->b.chip_class >= GFX9) {
+	if (sscreen->info.chip_class >= GFX9) {
 		si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
 		si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, va >> 40);
 
 		/* We need at least 2 components for LS.
 		 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
 		 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
 		 */
 		ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
 
 		shader->config.rsrc2 =
@@ -509,35 +509,35 @@ static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
 			S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
 	}
 
 	si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
 		       S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
 		       S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
 		       S_00B428_DX10_CLAMP(1) |
 		       S_00B428_FLOAT_MODE(shader->config.float_mode) |
 		       S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
 
-	if (sscreen->b.chip_class <= VI) {
+	if (sscreen->info.chip_class <= VI) {
 		si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
 			       shader->config.rsrc2);
 	}
 }
 
 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
 {
 	struct si_pm4_state *pm4;
 	unsigned num_user_sgprs;
 	unsigned vgpr_comp_cnt;
 	uint64_t va;
 	unsigned oc_lds_en;
 
-	assert(sscreen->b.chip_class <= VI);
+	assert(sscreen->info.chip_class <= VI);
 
 	pm4 = si_get_shader_pm4_state(shader);
 	if (!pm4)
 		return;
 
 	va = shader->bo->gpu_address;
 	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
 
 	if (shader->selector->type == PIPE_SHADER_VERTEX) {
 		/* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
@@ -571,21 +571,21 @@ static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
 
 	polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
 }
 
 /**
  * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
  * geometry shader.
  */
 static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
 {
-	enum chip_class chip_class = sel->screen->b.chip_class;
+	enum chip_class chip_class = sel->screen->info.chip_class;
 	unsigned gs_max_vert_out = sel->gs_max_out_vertices;
 	unsigned cut_mode;
 
 	if (gs_max_vert_out <= 128) {
 		cut_mode = V_028A40_GS_CUT_128;
 	} else if (gs_max_vert_out <= 256) {
 		cut_mode = V_028A40_GS_CUT_256;
 	} else if (gs_max_vert_out <= 512) {
 		cut_mode = V_028A40_GS_CUT_512;
 	} else {
@@ -744,21 +744,21 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
 	si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
 	si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
 
 	si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
 		       S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
 		       S_028B90_ENABLE(gs_num_invocations > 0));
 
 	va = shader->bo->gpu_address;
 	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
 
-	if (sscreen->b.chip_class >= GFX9) {
+	if (sscreen->info.chip_class >= GFX9) {
 		unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
 		unsigned es_type = shader->key.part.gs.es->type;
 		unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
 		struct gfx9_gs_info gs_info;
 
 		if (es_type == PIPE_SHADER_VERTEX)
 			/* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
 			es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
 		else if (es_type == PIPE_SHADER_TESS_EVAL)
 			es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
@@ -863,21 +863,21 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
 		if (enable_prim_id)
 			mode = V_028A40_GS_SCENARIO_A;
 
 		si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, S_028A40_MODE(mode));
 		si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
 	} else {
 		si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
 		si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
 	}
 
-	if (sscreen->b.chip_class <= VI) {
+	if (sscreen->info.chip_class <= VI) {
 		/* Reuse needs to be set off if we write oViewport. */
 		si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF,
 			       S_028AB4_REUSE_OFF(info->writes_viewport_index));
 	}
 
 	va = shader->bo->gpu_address;
 	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
 
 	if (gs) {
 		vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
@@ -1473,21 +1473,21 @@ static inline void si_shader_selector_key(struct pipe_context *ctx,
 			}
 		}
 
 		key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
 		break;
 	}
 	default:
 		assert(0);
 	}
 
-	if (unlikely(sctx->screen->b.debug_flags & DBG(NO_OPT_VARIANT)))
+	if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
 		memset(&key->opt, 0, sizeof(key->opt));
 }
 
 static void si_build_shader_variant(struct si_shader *shader,
 				    int thread_index,
 				    bool low_priority)
 {
 	struct si_shader_selector *sel = shader->selector;
 	struct si_screen *sscreen = sel->screen;
 	LLVMTargetMachineRef tm;
@@ -1653,21 +1653,21 @@ current_not_ready:
 		return -ENOMEM;
 	}
 
 	util_queue_fence_init(&shader->ready);
 
 	shader->selector = sel;
 	shader->key = *key;
 	shader->compiler_ctx_state = *compiler_state;
 
 	/* If this is a merged shader, get the first shader's selector. */
-	if (sscreen->b.chip_class >= GFX9) {
+	if (sscreen->info.chip_class >= GFX9) {
 		if (sel->type == PIPE_SHADER_TESS_CTRL)
 			previous_stage_sel = key->part.tcs.ls;
 		else if (sel->type == PIPE_SHADER_GEOMETRY)
 			previous_stage_sel = key->part.gs.es;
 
 		/* We need to wait for the previous shader. */
 		if (previous_stage_sel && thread_index < 0)
 			util_queue_fence_wait(&previous_stage_sel->ready);
 	}
 
@@ -1936,35 +1936,35 @@ static void si_init_shader_selector_async(void *job, int thread_index)
 				case TGSI_SEMANTIC_PSIZE:
 				case TGSI_SEMANTIC_CLIPVERTEX:
 				case TGSI_SEMANTIC_EDGEFLAG:
 					break;
 				}
 			}
 		}
 	}
 
 	/* Pre-compilation. */
-	if (sscreen->b.debug_flags & DBG(PRECOMPILE) &&
+	if (sscreen->debug_flags & DBG(PRECOMPILE) &&
 	    /* GFX9 needs LS or ES for compilation, which we don't have here. */
-	    (sscreen->b.chip_class <= VI ||
+	    (sscreen->info.chip_class <= VI ||
 	     (sel->type != PIPE_SHADER_TESS_CTRL &&
 	      sel->type != PIPE_SHADER_GEOMETRY))) {
 		struct si_shader_ctx_state state = {sel};
 		struct si_shader_key key;
 
 		memset(&key, 0, sizeof(key));
 		si_parse_next_shader_property(&sel->info,
 					      sel->so.num_outputs != 0,
 					      &key);
 
 		/* GFX9 doesn't have LS and ES. */
-		if (sscreen->b.chip_class >= GFX9) {
+		if (sscreen->info.chip_class >= GFX9) {
 			key.as_ls = 0;
 			key.as_es = 0;
 		}
 
 		/* Set reasonable defaults, so that the shader key doesn't
 		 * cause any code to be eliminated.
 		 */
 		switch (sel->type) {
 		case PIPE_SHADER_TESS_CTRL:
 			key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
@@ -2057,42 +2057,42 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
 		assert(state->type == PIPE_SHADER_IR_NIR);
 
 		sel->nir = state->ir.nir;
 
 		si_nir_scan_shader(sel->nir, &sel->info);
 
 		si_lower_nir(sel);
 	}
 
 	sel->type = sel->info.processor;
-	p_atomic_inc(&sscreen->b.num_shaders_created);
+	p_atomic_inc(&sscreen->num_shaders_created);
 	si_get_active_slot_masks(&sel->info,
 				 &sel->active_const_and_shader_buffers,
 				 &sel->active_samplers_and_images);
 
 	/* Record which streamout buffers are enabled. */
 	for (i = 0; i < sel->so.num_outputs; i++) {
 		sel->enabled_streamout_buffer_mask |=
 			(1 << sel->so.output[i].output_buffer) <<
 			(sel->so.output[i].stream * 4);
 	}
 
 	/* The prolog is a no-op if there are no inputs. */
 	sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
 			       sel->info.num_inputs &&
 			       !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
 
 	sel->force_correct_derivs_after_kill =
 		sel->type == PIPE_SHADER_FRAGMENT &&
 		sel->info.uses_derivatives &&
 		sel->info.uses_kill &&
-		sctx->screen->b.debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
+		sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
 
 	/* Set which opcode uses which (i,j) pair. */
 	if (sel->info.uses_persp_opcode_interp_centroid)
 		sel->info.uses_persp_centroid = true;
 
 	if (sel->info.uses_linear_opcode_interp_centroid)
 		sel->info.uses_linear_centroid = true;
 
 	if (sel->info.uses_persp_opcode_interp_offset ||
 	    sel->info.uses_persp_opcode_interp_sample)
@@ -2714,21 +2714,21 @@ static void si_init_config_add_vgt_flush(struct si_context *sctx)
 
 /* Initialize state related to ESGS / GSVS ring buffers */
 static bool si_update_gs_ring_buffers(struct si_context *sctx)
 {
 	struct si_shader_selector *es =
 		sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
 	struct si_shader_selector *gs = sctx->gs_shader.cso;
 	struct si_pm4_state *pm4;
 
 	/* Chip constants. */
-	unsigned num_se = sctx->screen->b.info.max_se;
+	unsigned num_se = sctx->screen->info.max_se;
 	unsigned wave_size = 64;
 	unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
 	/* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
 	 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
 	 */
 	unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se;
 	unsigned alignment = 256 * num_se;
 	/* The maximum size is 63.999 MB per SE. */
 	unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
 
@@ -3014,21 +3014,21 @@ static bool si_update_spi_tmpring_size(struct si_context *sctx)
 	unsigned scratch_needed_size = scratch_bytes_per_wave *
 		sctx->scratch_waves;
 	unsigned spi_tmpring_size;
 
 	if (scratch_needed_size > 0) {
 		if (scratch_needed_size > current_scratch_buffer_size) {
 			/* Create a bigger scratch buffer */
 			r600_resource_reference(&sctx->scratch_buffer, NULL);
 
 			sctx->scratch_buffer = (struct r600_resource*)
-				si_aligned_buffer_create(&sctx->screen->b.b,
+				si_aligned_buffer_create(&sctx->screen->b,
 							   R600_RESOURCE_FLAG_UNMAPPABLE,
 							   PIPE_USAGE_DEFAULT,
 							   scratch_needed_size, 256);
 			if (!sctx->scratch_buffer)
 				return false;
 
 			si_mark_atom_dirty(sctx, &sctx->scratch_state);
 			si_context_add_resource_size(&sctx->b.b,
 						     &sctx->scratch_buffer->b.b);
 		}
@@ -3053,21 +3053,21 @@ static bool si_update_spi_tmpring_size(struct si_context *sctx)
 static void si_init_tess_factor_ring(struct si_context *sctx)
 {
 	bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
 				      sctx->b.family != CHIP_CARRIZO &&
 				      sctx->b.family != CHIP_STONEY;
 	/* This must be one less than the maximum number due to a hw limitation.
 	 * Various hardware bugs in SI, CIK, and GFX9 need this.
 	 */
 	unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
 	unsigned max_offchip_buffers = max_offchip_buffers_per_se *
-				       sctx->screen->b.info.max_se;
+				       sctx->screen->info.max_se;
 	unsigned offchip_granularity;
 
 	switch (sctx->screen->tess_offchip_block_dw_size) {
 	default:
 		assert(0);
 		/* fall through */
 	case 8192:
 		offchip_granularity = V_03093C_X_8K_DWORDS;
 		break;
 	case 4096:
@@ -3075,21 +3075,21 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
 		break;
 	}
 
 	assert(!sctx->tf_ring);
 	/* Use 64K alignment for both rings, so that we can pass the address
 	 * to shaders as one SGPR containing bits [16:47].
 	 */
 	sctx->tf_ring = si_aligned_buffer_create(sctx->b.b.screen,
 						   R600_RESOURCE_FLAG_UNMAPPABLE,
 						   PIPE_USAGE_DEFAULT,
-						   32768 * sctx->screen->b.info.max_se,
+						   32768 * sctx->screen->info.max_se,
 						   64 * 1024);
 	if (!sctx->tf_ring)
 		return;
 
 	assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
 
 	sctx->tess_offchip_ring =
 		si_aligned_buffer_create(sctx->b.b.screen,
 					   R600_RESOURCE_FLAG_UNMAPPABLE,
 					   PIPE_USAGE_DEFAULT,
@@ -3359,21 +3359,21 @@ bool si_update_shaders(struct si_context *sctx)
 			S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
 
 		if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
 		    sctx->sprite_coord_enable != rs->sprite_coord_enable ||
 		    sctx->flatshade != rs->flatshade) {
 			sctx->sprite_coord_enable = rs->sprite_coord_enable;
 			sctx->flatshade = rs->flatshade;
 			si_mark_atom_dirty(sctx, &sctx->spi_map);
 		}
 
-		if (sctx->screen->b.rbplus_allowed &&
+		if (sctx->screen->rbplus_allowed &&
 		    si_pm4_state_changed(sctx, ps) &&
 		    (!old_ps ||
 		     old_spi_shader_col_format !=
 		     sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
 			si_mark_atom_dirty(sctx, &sctx->cb_render_state);
 
 		if (sctx->ps_db_shader_control != db_shader_control) {
 			sctx->ps_db_shader_control = db_shader_control;
 			si_mark_atom_dirty(sctx, &sctx->db_render_state);
 			if (sctx->screen->dpbb_allowed)
diff --git a/src/gallium/drivers/radeonsi/si_test_dma.c b/src/gallium/drivers/radeonsi/si_test_dma.c
index de88469..779572e 100644
--- a/src/gallium/drivers/radeonsi/si_test_dma.c
+++ b/src/gallium/drivers/radeonsi/si_test_dma.c
@@ -131,21 +131,21 @@ static enum pipe_format get_format_from_bpp(int bpp)
 		return PIPE_FORMAT_R32G32B32A32_UINT;
 	default:
 		assert(0);
 		return PIPE_FORMAT_NONE;
 	}
 }
 
 static const char *array_mode_to_string(struct si_screen *sscreen,
 					struct radeon_surf *surf)
 {
-	if (sscreen->b.chip_class >= GFX9) {
+	if (sscreen->info.chip_class >= GFX9) {
 		/* TODO */
 		return "       UNKNOWN";
 	} else {
 		switch (surf->u.legacy.level[0].mode) {
 		case RADEON_SURF_MODE_LINEAR_ALIGNED:
 			return "LINEAR_ALIGNED";
 		case RADEON_SURF_MODE_1D:
 			return "1D_TILED_THIN1";
 		case RADEON_SURF_MODE_2D:
 			return "2D_TILED_THIN1";
@@ -166,21 +166,21 @@ static unsigned generate_max_tex_side(unsigned max_tex_side)
 		/* Try to hit 1D tiling in 1/4 of the cases. */
 		return 128;
 	default:
 		/* Try to hit common sizes in 2/4 of the cases. */
 		return 2048;
 	}
 }
 
 void si_test_dma(struct si_screen *sscreen)
 {
-	struct pipe_screen *screen = &sscreen->b.b;
+	struct pipe_screen *screen = &sscreen->b;
 	struct pipe_context *ctx = screen->context_create(screen, NULL, 0);
 	struct si_context *sctx = (struct si_context*)ctx;
 	uint64_t max_alloc_size;
 	unsigned i, iterations, num_partial_copies, max_levels, max_tex_side;
 	unsigned num_pass = 0, num_fail = 0;
 
 	max_levels = screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS);
 	max_tex_side = 1 << (max_levels - 1);
 
 	/* Max 128 MB allowed for both textures. */
diff --git a/src/gallium/drivers/radeonsi/si_uvd.c b/src/gallium/drivers/radeonsi/si_uvd.c
index 09fdb23..64f2f8e 100644
--- a/src/gallium/drivers/radeonsi/si_uvd.c
+++ b/src/gallium/drivers/radeonsi/si_uvd.c
@@ -105,21 +105,21 @@ error:
 
 	return NULL;
 }
 
 /* set the decoding target buffer offsets */
 static struct pb_buffer* si_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_buffer *buf)
 {
 	struct si_screen *sscreen = (struct si_screen*)buf->base.context->screen;
 	struct r600_texture *luma = (struct r600_texture *)buf->resources[0];
 	struct r600_texture *chroma = (struct r600_texture *)buf->resources[1];
-	enum ruvd_surface_type type =  (sscreen->b.chip_class >= GFX9) ?
+	enum ruvd_surface_type type =  (sscreen->info.chip_class >= GFX9) ?
 					RUVD_SURFACE_TYPE_GFX9 :
 					RUVD_SURFACE_TYPE_LEGACY;
 
 	msg->body.decode.dt_field_mode = buf->base.interlaced;
 
 	si_uvd_set_dt_surfaces(msg, &luma->surface, (chroma) ? &chroma->surface : NULL, type);
 
 	return luma->resource.buf;
 }
 
-- 
2.7.4



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