[Mesa-dev] [PATCH 3/4] i965/gen10: Enable float blend optimization

[Anuj Phogat]

This optimization is enabled for previous generations too.
See Mesa commit c17e214a6b
On CNL this bit is moved to 3DSTATE_3D_MODE.

Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
---
 src/mesa/drivers/dri/i965/brw_defines.h      | 3 +++
 src/mesa/drivers/dri/i965/brw_state_upload.c | 8 ++++++++
 2 files changed, 11 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 270cdf29db..743b9d0a0d 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1333,6 +1333,9 @@ enum brw_pixel_shader_coverage_mask_mode {
 /* DW2: start address */
 /* DW3: end address. */
 
+#define _3DSTATE_3D_MODE                     0x791E
+# define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 9)
+
 #define CMD_MI_FLUSH                  0x0200
 
 # define BLT_X_SHIFT					0
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 7b31aad170..a1bf54dc72 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -85,6 +85,14 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
       }
    }
 
+   if (devinfo->gen == 10) {
+      BEGIN_BATCH(2);
+      OUT_BATCH(_3DSTATE_3D_MODE  << 16 | (2 - 2));
+      OUT_BATCH(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE << 16 |
+                GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE);
+      ADVANCE_BATCH();
+   }
+
    if (devinfo->gen >= 8) {
       gen8_emit_3dstate_sample_pattern(brw);
 
-- 
2.13.5