[Mesa-dev] [PATCH 5/5] radeonsi: inline struct si_sampler_views
Nicolai Hähnle
nhaehnle at gmail.com
Thu Oct 5 15:18:19 UTC 2017
For the series:
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
On 03.10.2017 19:30, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> ---
> src/gallium/drivers/radeonsi/si_blit.c | 12 +++----
> src/gallium/drivers/radeonsi/si_debug.c | 2 +-
> src/gallium/drivers/radeonsi/si_descriptors.c | 51 +++++++++++++--------------
> src/gallium/drivers/radeonsi/si_pipe.h | 6 +++-
> src/gallium/drivers/radeonsi/si_state.h | 8 -----
> 5 files changed, 37 insertions(+), 42 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
> index 957254b..67972a2 100644
> --- a/src/gallium/drivers/radeonsi/si_blit.c
> +++ b/src/gallium/drivers/radeonsi/si_blit.c
> @@ -73,24 +73,24 @@ static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
> util_blitter_save_viewport(sctx->blitter, &sctx->viewports.states[0]);
> util_blitter_save_scissor(sctx->blitter, &sctx->scissors.states[0]);
> }
>
> if (op & SI_SAVE_FRAMEBUFFER)
> util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
>
> if (op & SI_SAVE_TEXTURES) {
> util_blitter_save_fragment_sampler_states(
> sctx->blitter, 2,
> - (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
> + (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].sampler_states);
>
> util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
> - sctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
> + sctx->samplers[PIPE_SHADER_FRAGMENT].views);
> }
>
> if (op & SI_DISABLE_RENDER_COND)
> sctx->b.render_cond_force_off = true;
> }
>
> static void si_blitter_end(struct pipe_context *ctx)
> {
> struct si_context *sctx = (struct si_context *)ctx;
>
> @@ -426,21 +426,21 @@ si_decompress_sampler_depth_textures(struct si_context *sctx,
> unsigned i;
> unsigned mask = textures->needs_depth_decompress_mask;
>
> while (mask) {
> struct pipe_sampler_view *view;
> struct si_sampler_view *sview;
> struct r600_texture *tex;
>
> i = u_bit_scan(&mask);
>
> - view = textures->views.views[i];
> + view = textures->views[i];
> assert(view);
> sview = (struct si_sampler_view*)view;
>
> tex = (struct r600_texture *)view->texture;
> assert(tex->db_compatible);
>
> si_decompress_depth(sctx, tex,
> sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
> view->u.tex.first_level, view->u.tex.last_level,
> 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
> @@ -552,21 +552,21 @@ si_decompress_sampler_color_textures(struct si_context *sctx,
> {
> unsigned i;
> unsigned mask = textures->needs_color_decompress_mask;
>
> while (mask) {
> struct pipe_sampler_view *view;
> struct r600_texture *tex;
>
> i = u_bit_scan(&mask);
>
> - view = textures->views.views[i];
> + view = textures->views[i];
> assert(view);
>
> tex = (struct r600_texture *)view->texture;
>
> si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
> view->u.tex.last_level);
> }
> }
>
> static void
> @@ -622,29 +622,29 @@ static void si_check_render_feedback_texture(struct si_context *sctx,
> }
> }
>
> if (render_feedback)
> si_texture_disable_dcc(&sctx->b, tex);
> }
>
> static void si_check_render_feedback_textures(struct si_context *sctx,
> struct si_samplers *textures)
> {
> - uint32_t mask = textures->views.enabled_mask;
> + uint32_t mask = textures->enabled_mask;
>
> while (mask) {
> const struct pipe_sampler_view *view;
> struct r600_texture *tex;
>
> unsigned i = u_bit_scan(&mask);
>
> - view = textures->views.views[i];
> + view = textures->views[i];
> if(view->texture->target == PIPE_BUFFER)
> continue;
>
> tex = (struct r600_texture *)view->texture;
>
> si_check_render_feedback_texture(sctx, tex,
> view->u.tex.first_level,
> view->u.tex.last_level,
> view->u.tex.first_layer,
> view->u.tex.last_layer);
> diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c
> index 5075ccd..ddf65d6 100644
> --- a/src/gallium/drivers/radeonsi/si_debug.c
> +++ b/src/gallium/drivers/radeonsi/si_debug.c
> @@ -729,21 +729,21 @@ static void si_dump_descriptors(struct si_context *sctx,
> enabled_shaderbuf = info->shader_buffers_declared;
> enabled_samplers = info->samplers_declared;
> enabled_images = info->images_declared;
> } else {
> enabled_constbuf = sctx->const_and_shader_buffers[processor].enabled_mask >>
> SI_NUM_SHADER_BUFFERS;
> enabled_shaderbuf = sctx->const_and_shader_buffers[processor].enabled_mask &
> u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
> enabled_shaderbuf = util_bitreverse(enabled_shaderbuf) >>
> (32 - SI_NUM_SHADER_BUFFERS);
> - enabled_samplers = sctx->samplers[processor].views.enabled_mask;
> + enabled_samplers = sctx->samplers[processor].enabled_mask;
> enabled_images = sctx->images[processor].enabled_mask;
> }
>
> if (processor == PIPE_SHADER_VERTEX) {
> assert(info); /* only CS may not have an info struct */
>
> si_dump_descriptor_list(sctx->screen, &sctx->vertex_buffers, name,
> " - Vertex buffer", 4, info->num_inputs,
> si_identity, log);
> }
> diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
> index 788e7c3..dee8e71 100644
> --- a/src/gallium/drivers/radeonsi/si_descriptors.c
> +++ b/src/gallium/drivers/radeonsi/si_descriptors.c
> @@ -187,26 +187,26 @@ si_sampler_and_image_descriptors_idx(unsigned shader)
> return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
> SI_SHADER_DESCS_SAMPLERS_AND_IMAGES;
> }
>
> static struct si_descriptors *
> si_sampler_and_image_descriptors(struct si_context *sctx, unsigned shader)
> {
> return &sctx->descriptors[si_sampler_and_image_descriptors_idx(shader)];
> }
>
> -static void si_release_sampler_views(struct si_sampler_views *views)
> +static void si_release_sampler_views(struct si_samplers *samplers)
> {
> int i;
>
> - for (i = 0; i < ARRAY_SIZE(views->views); i++) {
> - pipe_sampler_view_reference(&views->views[i], NULL);
> + for (i = 0; i < ARRAY_SIZE(samplers->views); i++) {
> + pipe_sampler_view_reference(&samplers->views[i], NULL);
> }
> }
>
> static void si_sampler_view_add_buffer(struct si_context *sctx,
> struct pipe_resource *resource,
> enum radeon_bo_usage usage,
> bool is_stencil_sampler,
> bool check_mem)
> {
> struct r600_resource *rres;
> @@ -236,28 +236,28 @@ static void si_sampler_view_add_buffer(struct si_context *sctx,
> /* Now add separate DCC or HTILE. */
> rtex = (struct r600_texture*)resource;
> if (rtex->dcc_separate_buffer) {
> radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
> rtex->dcc_separate_buffer, usage,
> RADEON_PRIO_DCC, check_mem);
> }
> }
>
> static void si_sampler_views_begin_new_cs(struct si_context *sctx,
> - struct si_sampler_views *views)
> + struct si_samplers *samplers)
> {
> - unsigned mask = views->enabled_mask;
> + unsigned mask = samplers->enabled_mask;
>
> /* Add buffers to the CS. */
> while (mask) {
> int i = u_bit_scan(&mask);
> - struct si_sampler_view *sview = (struct si_sampler_view *)views->views[i];
> + struct si_sampler_view *sview = (struct si_sampler_view *)samplers->views[i];
>
> si_sampler_view_add_buffer(sctx, sview->base.texture,
> RADEON_USAGE_READ,
> sview->is_stencil_sampler, false);
> }
> }
>
> /* Set buffer descriptor fields that can be changed by reallocations. */
> static void si_set_buf_desc_address(struct r600_resource *buf,
> uint64_t offset, uint32_t *state)
> @@ -459,34 +459,33 @@ static bool depth_needs_decompression(struct r600_texture *rtex)
> */
> return rtex->db_compatible;
> }
>
> static void si_set_sampler_view(struct si_context *sctx,
> unsigned shader,
> unsigned slot, struct pipe_sampler_view *view,
> bool disallow_early_out)
> {
> struct si_samplers *samplers = &sctx->samplers[shader];
> - struct si_sampler_views *views = &samplers->views;
> struct si_sampler_view *rview = (struct si_sampler_view*)view;
> struct si_descriptors *descs = si_sampler_and_image_descriptors(sctx, shader);
> unsigned desc_slot = si_get_sampler_slot(slot);
> uint32_t *desc = descs->list + desc_slot * 16;
>
> - if (views->views[slot] == view && !disallow_early_out)
> + if (samplers->views[slot] == view && !disallow_early_out)
> return;
>
> if (view) {
> struct r600_texture *rtex = (struct r600_texture *)view->texture;
>
> si_set_sampler_view_desc(sctx, rview,
> - views->sampler_states[slot], desc);
> + samplers->sampler_states[slot], desc);
>
> if (rtex->resource.b.b.target == PIPE_BUFFER) {
> rtex->resource.bind_history |= PIPE_BIND_SAMPLER_VIEW;
> samplers->needs_depth_decompress_mask &= ~(1u << slot);
> samplers->needs_color_decompress_mask &= ~(1u << slot);
> } else {
> if (depth_needs_decompression(rtex)) {
> samplers->needs_depth_decompress_mask |= 1u << slot;
> } else {
> samplers->needs_depth_decompress_mask &= ~(1u << slot);
> @@ -495,39 +494,39 @@ static void si_set_sampler_view(struct si_context *sctx,
> samplers->needs_color_decompress_mask |= 1u << slot;
> } else {
> samplers->needs_color_decompress_mask &= ~(1u << slot);
> }
>
> if (rtex->dcc_offset &&
> p_atomic_read(&rtex->framebuffers_bound))
> sctx->need_check_render_feedback = true;
> }
>
> - pipe_sampler_view_reference(&views->views[slot], view);
> - views->enabled_mask |= 1u << slot;
> + pipe_sampler_view_reference(&samplers->views[slot], view);
> + samplers->enabled_mask |= 1u << slot;
>
> /* Since this can flush, it must be done after enabled_mask is
> * updated. */
> si_sampler_view_add_buffer(sctx, view->texture,
> RADEON_USAGE_READ,
> rview->is_stencil_sampler, true);
> } else {
> - pipe_sampler_view_reference(&views->views[slot], NULL);
> + pipe_sampler_view_reference(&samplers->views[slot], NULL);
> memcpy(desc, null_texture_descriptor, 8*4);
> /* Only clear the lower dwords of FMASK. */
> memcpy(desc + 8, null_texture_descriptor, 4*4);
> /* Re-set the sampler state if we are transitioning from FMASK. */
> - if (views->sampler_states[slot])
> - si_set_sampler_state_desc(views->sampler_states[slot], NULL, NULL,
> + if (samplers->sampler_states[slot])
> + si_set_sampler_state_desc(samplers->sampler_states[slot], NULL, NULL,
> desc + 12);
>
> - views->enabled_mask &= ~(1u << slot);
> + samplers->enabled_mask &= ~(1u << slot);
> samplers->needs_depth_decompress_mask &= ~(1u << slot);
> samplers->needs_color_decompress_mask &= ~(1u << slot);
> }
>
> sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
> }
>
> static void si_update_shader_needs_decompress_mask(struct si_context *sctx,
> unsigned shader)
> {
> @@ -560,25 +559,25 @@ static void si_set_sampler_views(struct pipe_context *ctx,
> for (i = 0; i < count; i++)
> si_set_sampler_view(sctx, shader, start + i, NULL, false);
> }
>
> si_update_shader_needs_decompress_mask(sctx, shader);
> }
>
> static void
> si_samplers_update_needs_color_decompress_mask(struct si_samplers *samplers)
> {
> - unsigned mask = samplers->views.enabled_mask;
> + unsigned mask = samplers->enabled_mask;
>
> while (mask) {
> int i = u_bit_scan(&mask);
> - struct pipe_resource *res = samplers->views.views[i]->texture;
> + struct pipe_resource *res = samplers->views[i]->texture;
>
> if (res && res->target != PIPE_BUFFER) {
> struct r600_texture *rtex = (struct r600_texture *)res;
>
> if (color_needs_decompression(rtex)) {
> samplers->needs_color_decompress_mask |= 1u << i;
> } else {
> samplers->needs_color_decompress_mask &= ~(1u << i);
> }
> }
> @@ -835,33 +834,33 @@ static void si_bind_sampler_states(struct pipe_context *ctx,
> int i;
>
> if (!count || shader >= SI_NUM_SHADERS)
> return;
>
> for (i = 0; i < count; i++) {
> unsigned slot = start + i;
> unsigned desc_slot = si_get_sampler_slot(slot);
>
> if (!sstates[i] ||
> - sstates[i] == samplers->views.sampler_states[slot])
> + sstates[i] == samplers->sampler_states[slot])
> continue;
>
> #ifdef DEBUG
> assert(sstates[i]->magic == SI_SAMPLER_STATE_MAGIC);
> #endif
> - samplers->views.sampler_states[slot] = sstates[i];
> + samplers->sampler_states[slot] = sstates[i];
>
> /* If FMASK is bound, don't overwrite it.
> * The sampler state will be set after FMASK is unbound.
> */
> struct si_sampler_view *sview =
> - (struct si_sampler_view *)samplers->views.views[slot];
> + (struct si_sampler_view *)samplers->views[slot];
>
> struct r600_texture *tex = NULL;
>
> if (sview && sview->base.texture &&
> sview->base.texture->target != PIPE_BUFFER)
> tex = (struct r600_texture *)sview->base.texture;
>
> if (tex && tex->fmask.size)
> continue;
>
> @@ -1676,28 +1675,28 @@ static void si_rebind_buffer(struct pipe_context *ctx, struct pipe_resource *buf
> si_const_and_shader_buffer_descriptors_idx(shader),
> u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS),
> buf, old_va,
> sctx->const_and_shader_buffers[shader].shader_usage,
> sctx->const_and_shader_buffers[shader].priority);
> }
>
> if (rbuffer->bind_history & PIPE_BIND_SAMPLER_VIEW) {
> /* Texture buffers - update bindings. */
> for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
> - struct si_sampler_views *views = &sctx->samplers[shader].views;
> + struct si_samplers *samplers = &sctx->samplers[shader];
> struct si_descriptors *descs =
> si_sampler_and_image_descriptors(sctx, shader);
> - unsigned mask = views->enabled_mask;
> + unsigned mask = samplers->enabled_mask;
>
> while (mask) {
> unsigned i = u_bit_scan(&mask);
> - if (views->views[i]->texture == buf) {
> + if (samplers->views[i]->texture == buf) {
> unsigned desc_slot = si_get_sampler_slot(i);
>
> si_desc_reset_buffer_offset(ctx,
> descs->list +
> desc_slot * 16 + 4,
> old_va, buf);
> sctx->descriptors_dirty |=
> 1u << si_sampler_and_image_descriptors_idx(shader);
>
> radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
> @@ -1941,21 +1940,21 @@ static void si_update_all_resident_texture_descriptors(struct si_context *sctx)
>
> si_upload_bindless_descriptors(sctx);
> }
>
> /* Update mutable image descriptor fields of all bound textures. */
> void si_update_all_texture_descriptors(struct si_context *sctx)
> {
> unsigned shader;
>
> for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
> - struct si_sampler_views *samplers = &sctx->samplers[shader].views;
> + struct si_samplers *samplers = &sctx->samplers[shader];
> struct si_images *images = &sctx->images[shader];
> unsigned mask;
>
> /* Images. */
> mask = images->enabled_mask;
> while (mask) {
> unsigned i = u_bit_scan(&mask);
> struct pipe_image_view *view = &images->views[i];
>
> if (!view->resource ||
> @@ -2764,21 +2763,21 @@ bool si_upload_compute_shader_descriptors(struct si_context *sctx)
> return si_upload_shader_descriptors(sctx, mask);
> }
>
> void si_release_all_descriptors(struct si_context *sctx)
> {
> int i;
>
> for (i = 0; i < SI_NUM_SHADERS; i++) {
> si_release_buffer_resources(&sctx->const_and_shader_buffers[i],
> si_const_and_shader_buffer_descriptors(sctx, i));
> - si_release_sampler_views(&sctx->samplers[i].views);
> + si_release_sampler_views(&sctx->samplers[i]);
> si_release_image_views(&sctx->images[i]);
> }
> si_release_buffer_resources(&sctx->rw_buffers,
> &sctx->descriptors[SI_DESCS_RW_BUFFERS]);
> for (i = 0; i < SI_NUM_VERTEX_BUFFERS; i++)
> pipe_vertex_buffer_unreference(&sctx->vertex_buffer[i]);
>
> for (i = 0; i < SI_NUM_DESCS; ++i)
> si_release_descriptors(&sctx->descriptors[i]);
>
> @@ -2786,21 +2785,21 @@ void si_release_all_descriptors(struct si_context *sctx)
> si_release_descriptors(&sctx->vertex_buffers);
> si_release_bindless_descriptors(sctx);
> }
>
> void si_all_descriptors_begin_new_cs(struct si_context *sctx)
> {
> int i;
>
> for (i = 0; i < SI_NUM_SHADERS; i++) {
> si_buffer_resources_begin_new_cs(sctx, &sctx->const_and_shader_buffers[i]);
> - si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i].views);
> + si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i]);
> si_image_views_begin_new_cs(sctx, &sctx->images[i]);
> }
> si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
> si_vertex_buffers_begin_new_cs(sctx);
>
> for (i = 0; i < SI_NUM_DESCS; ++i)
> si_descriptors_begin_new_cs(sctx, &sctx->descriptors[i]);
> si_descriptors_begin_new_cs(sctx, &sctx->bindless_descriptors);
>
> si_shader_pointers_begin_new_cs(sctx);
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
> index 212d163..b96bf9d 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.h
> +++ b/src/gallium/drivers/radeonsi/si_pipe.h
> @@ -175,21 +175,25 @@ struct si_sampler_state {
>
> struct si_cs_shader_state {
> struct si_compute *program;
> struct si_compute *emitted_program;
> unsigned offset;
> bool initialized;
> bool uses_scratch;
> };
>
> struct si_samplers {
> - struct si_sampler_views views;
> + struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
> + struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
> +
> + /* The i-th bit is set if that element is enabled (non-NULL resource). */
> + unsigned enabled_mask;
> uint32_t needs_depth_decompress_mask;
> uint32_t needs_color_decompress_mask;
> };
>
> struct si_images {
> struct pipe_image_view views[SI_NUM_IMAGES];
> uint32_t needs_color_decompress_mask;
> unsigned enabled_mask;
> };
>
> diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
> index 8e414a0..3277926 100644
> --- a/src/gallium/drivers/radeonsi/si_state.h
> +++ b/src/gallium/drivers/radeonsi/si_state.h
> @@ -269,28 +269,20 @@ struct si_descriptors {
> * It determines which slots are uploaded.
> */
> uint32_t first_active_slot;
> uint32_t num_active_slots;
>
> /* The SGPR index where the 64-bit pointer to the descriptor array will
> * be stored. */
> ubyte shader_userdata_offset;
> };
>
> -struct si_sampler_views {
> - struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
> - struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
> -
> - /* The i-th bit is set if that element is enabled (non-NULL resource). */
> - unsigned enabled_mask;
> -};
> -
> struct si_buffer_resources {
> struct pipe_resource **buffers; /* this has num_buffers elements */
>
> enum radeon_bo_usage shader_usage:4; /* READ, WRITE, or READWRITE */
> enum radeon_bo_usage shader_usage_constbuf:4;
> enum radeon_bo_priority priority:6;
> enum radeon_bo_priority priority_constbuf:6;
>
> /* The i-th bit is set if that element is enabled (non-NULL resource). */
> unsigned enabled_mask;
>
--
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