[Mesa-dev] [PATCH] radeonsi: disable primitive binning on Vega10

Marek Olšák maraeo at gmail.com
Fri Oct 6 13:49:27 UTC 2017


From: Marek Olšák <marek.olsak at amd.com>

Our driver implementation is known to decrease performance for some tests,
but we don't know if any apps and benchmarks (especially those tested by
Phoronix) are affected. This disables the feature just to be safe.

The debug flags are inverted for Vega10. To enable it, set:
    R600_DEBUG=nodpbb,nodfsm
Partial support that might be better for Vega10 can be enabled with:
    R600_DEBUG=nodpbb
---
 src/gallium/drivers/radeonsi/si_pipe.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 5e20a0b..cf4e357 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1054,20 +1054,24 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
 	sscreen->assume_no_z_fights =
 		driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
 	sscreen->commutative_blend_add =
 		driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
 	sscreen->clear_db_meta_before_clear =
 		driQueryOptionb(config->options, "radeonsi_clear_db_meta_before_clear");
 	sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
 					    sscreen->b.family <= CHIP_POLARIS12) ||
 					   sscreen->b.family == CHIP_VEGA10 ||
 					   sscreen->b.family == CHIP_RAVEN;
+	/* Invert the DPBB flags for Vega10. Default is disabled.
+	 * nodpbb and nodfsm enable the features. */
+	if (sscreen->b.family == CHIP_VEGA10)
+		sscreen->b.debug_flags ^= (DBG_NO_DPBB | DBG_NO_DFSM);
 	sscreen->dpbb_allowed = sscreen->b.chip_class >= GFX9 &&
 				!(sscreen->b.debug_flags & DBG_NO_DPBB);
 	sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
 				!(sscreen->b.debug_flags & DBG_NO_DFSM);
 
 	/* While it would be nice not to have this flag, we are constrained
 	 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
 	 * on GFX9.
 	 */
 	sscreen->llvm_has_working_vgpr_indexing = sscreen->b.chip_class <= VI;
-- 
2.7.4



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