[Mesa-dev] [PATCH 11/12] radeonsi: set correct PA_SC_VPORT_ZMIN/ZMAX when viewport is disabled

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeonsi/si_state_viewport.c | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c b/src/gallium/drivers/radeonsi/si_state_viewport.c
index 0d280f6..0d6b7a8 100644
--- a/src/gallium/drivers/radeonsi/si_state_viewport.c
+++ b/src/gallium/drivers/radeonsi/si_state_viewport.c
@@ -328,54 +328,69 @@ static void si_emit_viewports(struct si_context *ctx)
 		u_bit_scan_consecutive_range(&mask, &start, &count);
 
 		radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
 					       start * 4 * 6, count * 6);
 		for (i = start; i < start+count; i++)
 			si_emit_one_viewport(ctx, &states[i]);
 	}
 	ctx->viewports.dirty_mask = 0;
 }
 
+static inline void
+si_viewport_zmin_zmax(const struct pipe_viewport_state *vp, bool halfz,
+		      bool window_space_position, float *zmin, float *zmax)
+{
+	if (window_space_position) {
+		*zmin = 0;
+		*zmax = 1;
+		return;
+	}
+	util_viewport_zmin_zmax(vp, halfz, zmin, zmax);
+}
+
 static void si_emit_depth_ranges(struct si_context *ctx)
 {
 	struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
 	struct pipe_viewport_state *states = ctx->viewports.states;
 	unsigned mask = ctx->viewports.depth_range_dirty_mask;
 	bool clip_halfz = false;
+	bool window_space = ctx->vs_disables_clipping_viewport;
 	float zmin, zmax;
 
 	if (ctx->queued.named.rasterizer)
 		clip_halfz = ctx->queued.named.rasterizer->clip_halfz;
 
 	/* The simple case: Only 1 viewport is active. */
 	if (!ctx->vs_writes_viewport_index) {
 		if (!(mask & 1))
 			return;
 
-		util_viewport_zmin_zmax(&states[0], clip_halfz, &zmin, &zmax);
+		si_viewport_zmin_zmax(&states[0], clip_halfz, window_space,
+				      &zmin, &zmax);
 
 		radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
 		radeon_emit(cs, fui(zmin));
 		radeon_emit(cs, fui(zmax));
 		ctx->viewports.depth_range_dirty_mask &= ~1; /* clear one bit */
 		return;
 	}
 
 	while (mask) {
 		int start, count, i;
 
 		u_bit_scan_consecutive_range(&mask, &start, &count);
 
 		radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
 					   start * 4 * 2, count * 2);
 		for (i = start; i < start+count; i++) {
-			util_viewport_zmin_zmax(&states[i], clip_halfz, &zmin, &zmax);
+			si_viewport_zmin_zmax(&states[i], clip_halfz, window_space,
+					      &zmin, &zmax);
 			radeon_emit(cs, fui(zmin));
 			radeon_emit(cs, fui(zmax));
 		}
 	}
 	ctx->viewports.depth_range_dirty_mask = 0;
 }
 
 static void si_emit_viewport_states(struct r600_common_context *rctx,
 				    struct r600_atom *atom)
 {
@@ -402,21 +417,23 @@ void si_update_vs_viewport_state(struct si_context *ctx)
 	if (!info)
 		return;
 
 	/* When the VS disables clipping and viewport transformation. */
 	vs_window_space =
 		info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
 
 	if (ctx->vs_disables_clipping_viewport != vs_window_space) {
 		ctx->vs_disables_clipping_viewport = vs_window_space;
 		ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
+		ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 		si_mark_atom_dirty(ctx, &ctx->scissors.atom);
+		si_mark_atom_dirty(ctx, &ctx->viewports.atom);
 	}
 
 	/* Viewport index handling. */
 	ctx->vs_writes_viewport_index = info->writes_viewport_index;
 	if (!ctx->vs_writes_viewport_index)
 		return;
 
 	if (ctx->scissors.dirty_mask)
 	    si_mark_atom_dirty(ctx, &ctx->scissors.atom);
 
-- 
2.7.4