[Mesa-dev] [PATCH 1/4] i965/fs: some TXF don't provide LOD

[Lionel Landwerlin]

On 06/10/17 16:31, Samuel Iglesias Gonsálvez wrote:
> On Fri, 2017-10-06 at 08:28 -0700, Jason Ekstrand wrote:
>> On Fri, Oct 6, 2017 at 6:36 AM, Samuel Iglesias Gonsálvez 
>> <siglesias at igalia.com <mailto:siglesias at igalia.com>> wrote:
>>> On Fri, 2017-10-06 at 14:23 +0100, Lionel Landwerlin wrote:
>>>> I fixed a similar bug in the vec4 backend a couple of days ago.
>>>> Can we maybe put this logic somewhere that could reused across 
>>>> backends?
>>>> Or maybe a nir pass to add the missing parameters?
>>>>
>>>> Thanks,
>>>>
>>>> -
>>>> Lionel
>>>>
>>>
>>> Right. I think it should be reused across the backends, as it is the 
>>> sampling
>>> instruction the one who needs it; but I'm OK with either option.
>>>
>>
>> I don't care much where it goes.  I guess we could always add it to 
>> nir_lower_tex with a default_lod_0 option.  Or we can just fix it up 
>> in both back-ends.  Or we could fix it up here.  The nir_lower_tex 
>> option may be the most reliable.
>
> OK, as I need to send a v2 for this patch series, I will write patch 
> with the nir_lower_tex solution.
>
> Sam

Thanks !

>
>>> Sam
>>>
>>>> On 06/10/17 14:07, Jason Ekstrand wrote:
>>>>> Is there a test case for this?
>>>>>
>>>>> Reviewed-by: Jason Ekstrand <jason at jlekstrand.net 
>>>>> <mailto:jason at jlekstrand.net>>
>>>>>
>>>>> On Fri, Oct 6, 2017 at 2:36 AM, Samuel Iglesias Gonsálvez 
>>>>> <siglesias at igalia.com <mailto:siglesias at igalia.com>> wrote:
>>>>>> SpvOpImageFetch doesn't provide it, so set it to zero.
>>>>>>
>>>>>> Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com 
>>>>>> <mailto:siglesias at igalia.com>>
>>>>>> ---
>>>>>>  src/intel/compiler/brw_fs_nir.cpp | 9 +++++----
>>>>>>  1 file changed, 5 insertions(+), 4 deletions(-)
>>>>>>
>>>>>> diff --git a/src/intel/compiler/brw_fs_nir.cpp 
>>>>>> b/src/intel/compiler/brw_fs_nir.cpp
>>>>>> index 5b8ccd50bff..25488303c29 100644
>>>>>> --- a/src/intel/compiler/brw_fs_nir.cpp
>>>>>> +++ b/src/intel/compiler/brw_fs_nir.cpp
>>>>>> @@ -4518,11 +4518,12 @@ fs_visitor::nir_emit_texture(const 
>>>>>> fs_builder &bld, nir_tex_instr *instr)
>>>>>>        unreachable("unknown texture opcode");
>>>>>>     }
>>>>>>
>>>>>> -   /* TXS and TXL require a LOD but not everything we implement 
>>>>>> using those
>>>>>> -    * two opcodes provides one. Provide a default LOD of 0.
>>>>>> +   /* TXF, TXS and TXL require a LOD but not everything we 
>>>>>> implement using those
>>>>>> +    * three opcodes provides one. Provide a default LOD of 0.
>>>>>>      */
>>>>>> -   if ((opcode == SHADER_OPCODE_TXS_LOGICAL ||
>>>>>> -        opcode == SHADER_OPCODE_TXL_LOGICAL) &&
>>>>>> +   if ((opcode == SHADER_OPCODE_TXF_LOGICAL ||
>>>>>> +         opcode == SHADER_OPCODE_TXS_LOGICAL ||
>>>>>> +         opcode == SHADER_OPCODE_TXL_LOGICAL) &&
>>>>>>         srcs[TEX_LOGICAL_SRC_LOD].file == BAD_FILE) {
>>>>>>        srcs[TEX_LOGICAL_SRC_LOD] = brw_imm_ud(0u);
>>>>>>     }
>>>>>> --
>>>>>> 2.13.6
>>>>>>
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>>>>>>
>>>>>
>>>>>
>>>>>
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>>>>
>>>>
>>

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