[Mesa-dev] [PATCH 2/3] gallium/radeon: remove r600_atom::num_dw
Nicolai Hähnle
nhaehnle at gmail.com
Sat Oct 7 08:58:06 UTC 2017
Okay, so my comment on patch #1 is irrelevant, makes sense. For the series:
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
On 06.10.2017 15:49, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> ---
> src/gallium/drivers/radeon/r600_pipe_common.h | 2 --
> src/gallium/drivers/radeon/r600_query.c | 15 ---------------
> src/gallium/drivers/radeon/r600_streamout.c | 21 ++-------------------
> src/gallium/drivers/radeonsi/si_state_viewport.c | 3 ---
> 4 files changed, 2 insertions(+), 39 deletions(-)
>
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
> index 074b321..8530798 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.h
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.h
> @@ -473,39 +473,37 @@ struct r600_common_screen {
>
> void (*apply_opaque_metadata)(struct r600_common_screen *rscreen,
> struct r600_texture *rtex,
> struct radeon_bo_metadata *md);
> };
>
> /* This encapsulates a state or an operation which can emitted into the GPU
> * command stream. */
> struct r600_atom {
> void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
> - unsigned num_dw;
> unsigned short id;
> };
>
> struct r600_so_target {
> struct pipe_stream_output_target b;
>
> /* The buffer where BUFFER_FILLED_SIZE is stored. */
> struct r600_resource *buf_filled_size;
> unsigned buf_filled_size_offset;
> bool buf_filled_size_valid;
>
> unsigned stride_in_dw;
> };
>
> struct r600_streamout {
> struct r600_atom begin_atom;
> bool begin_emitted;
> - unsigned num_dw_for_end;
>
> unsigned enabled_mask;
> unsigned num_targets;
> struct r600_so_target *targets[PIPE_MAX_SO_BUFFERS];
>
> unsigned append_bitmask;
> bool suspended;
>
> /* External state which comes from the vertex shader,
> * it must be set explicitly when binding a shader. */
> diff --git a/src/gallium/drivers/radeon/r600_query.c b/src/gallium/drivers/radeon/r600_query.c
> index f41cd8e..adf3522 100644
> --- a/src/gallium/drivers/radeon/r600_query.c
> +++ b/src/gallium/drivers/radeon/r600_query.c
> @@ -1770,25 +1770,22 @@ static void r600_query_hw_get_result_resource(struct r600_common_context *rctx,
> pipe_resource_reference(&tmp_buffer, NULL);
> }
>
> static void r600_render_condition(struct pipe_context *ctx,
> struct pipe_query *query,
> boolean condition,
> enum pipe_render_cond_flag mode)
> {
> struct r600_common_context *rctx = (struct r600_common_context *)ctx;
> struct r600_query_hw *rquery = (struct r600_query_hw *)query;
> - struct r600_query_buffer *qbuf;
> struct r600_atom *atom = &rctx->render_cond_atom;
>
> - /* Compute the size of SET_PREDICATION packets. */
> - atom->num_dw = 0;
> if (query) {
> bool needs_workaround = false;
>
> /* There was a firmware regression in VI which causes successive
> * SET_PREDICATION packets to give the wrong answer for
> * non-inverted stream overflow predication.
> */
> if (((rctx->chip_class == VI && rctx->screen->info.pfp_fw_feature < 49) ||
> (rctx->chip_class == GFX9 && rctx->screen->info.pfp_fw_feature < 38)) &&
> !condition &&
> @@ -1817,30 +1814,20 @@ static void r600_render_condition(struct pipe_context *ctx,
> ctx, query, true, PIPE_QUERY_TYPE_U64, 0,
> &rquery->workaround_buf->b.b, rquery->workaround_offset);
>
> /* Settings this in the render cond atom is too late,
> * so set it here. */
> rctx->flags |= rctx->screen->barrier_flags.L2_to_cp |
> R600_CONTEXT_FLUSH_FOR_RENDER_COND;
>
> rctx->render_cond_force_off = old_force_off;
> }
> -
> - if (needs_workaround) {
> - atom->num_dw = 5;
> - } else {
> - for (qbuf = &rquery->buffer; qbuf; qbuf = qbuf->previous)
> - atom->num_dw += (qbuf->results_end / rquery->result_size) * 5;
> -
> - if (rquery->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE)
> - atom->num_dw *= R600_MAX_STREAMS;
> - }
> }
>
> rctx->render_cond = query;
> rctx->render_cond_invert = condition;
> rctx->render_cond_mode = mode;
>
> rctx->set_atom_dirty(rctx, atom, query != NULL);
> }
>
> void si_suspend_queries(struct r600_common_context *ctx)
> @@ -1863,22 +1850,20 @@ static unsigned r600_queries_num_cs_dw_for_resuming(struct r600_common_context *
> /* begin + end */
> num_dw += query->num_cs_dw_begin + query->num_cs_dw_end;
>
> /* Workaround for the fact that
> * num_cs_dw_nontimer_queries_suspend is incremented for every
> * resumed query, which raises the bar in need_cs_space for
> * queries about to be resumed.
> */
> num_dw += query->num_cs_dw_end;
> }
> - /* primitives generated query */
> - num_dw += ctx->streamout.enable_atom.num_dw;
> /* guess for ZPASS enable or PERFECT_ZPASS_COUNT enable updates */
> num_dw += 13;
>
> return num_dw;
> }
>
> void si_resume_queries(struct r600_common_context *ctx)
> {
> struct r600_query_hw *query;
> unsigned num_cs_dw = r600_queries_num_cs_dw_for_resuming(ctx, &ctx->active_queries);
> diff --git a/src/gallium/drivers/radeon/r600_streamout.c b/src/gallium/drivers/radeon/r600_streamout.c
> index 84f6035..5c14b1b 100644
> --- a/src/gallium/drivers/radeon/r600_streamout.c
> +++ b/src/gallium/drivers/radeon/r600_streamout.c
> @@ -69,40 +69,24 @@ static void r600_so_target_destroy(struct pipe_context *ctx,
> struct pipe_stream_output_target *target)
> {
> struct r600_so_target *t = (struct r600_so_target*)target;
> pipe_resource_reference(&t->b.buffer, NULL);
> r600_resource_reference(&t->buf_filled_size, NULL);
> FREE(t);
> }
>
> void si_streamout_buffers_dirty(struct r600_common_context *rctx)
> {
> - struct r600_atom *begin = &rctx->streamout.begin_atom;
> - unsigned num_bufs = util_bitcount(rctx->streamout.enabled_mask);
> - unsigned num_bufs_appended = util_bitcount(rctx->streamout.enabled_mask &
> - rctx->streamout.append_bitmask);
> -
> - if (!num_bufs)
> + if (!rctx->streamout.enabled_mask)
> return;
>
> - rctx->streamout.num_dw_for_end =
> - 12 + /* flush_vgt_streamout */
> - num_bufs * 11; /* STRMOUT_BUFFER_UPDATE, BUFFER_SIZE */
> -
> - begin->num_dw = 12; /* flush_vgt_streamout */
> - begin->num_dw += num_bufs * 4; /* SET_CONTEXT_REG */
> - begin->num_dw +=
> - num_bufs_appended * 8 + /* STRMOUT_BUFFER_UPDATE */
> - (num_bufs - num_bufs_appended); + /* STRMOUT_BUFFER_UPDATE */
> -
> - rctx->set_atom_dirty(rctx, begin, true);
> -
> + rctx->set_atom_dirty(rctx, &rctx->streamout.begin_atom, true);
> r600_set_streamout_enable(rctx, true);
> }
>
> void si_common_set_streamout_targets(struct pipe_context *ctx,
> unsigned num_targets,
> struct pipe_stream_output_target **targets,
> const unsigned *offsets)
> {
> struct r600_common_context *rctx = (struct r600_common_context *)ctx;
> unsigned i;
> @@ -316,12 +300,11 @@ void si_update_prims_generated_query_state(struct r600_common_context *rctx,
> }
> }
> }
>
> void si_streamout_init(struct r600_common_context *rctx)
> {
> rctx->b.create_stream_output_target = r600_create_so_target;
> rctx->b.stream_output_target_destroy = r600_so_target_destroy;
> rctx->streamout.begin_atom.emit = r600_emit_streamout_begin;
> rctx->streamout.enable_atom.emit = r600_emit_streamout_enable;
> - rctx->streamout.enable_atom.num_dw = 6;
> }
> diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c b/src/gallium/drivers/radeonsi/si_state_viewport.c
> index a96eb8a..84f8cd8 100644
> --- a/src/gallium/drivers/radeonsi/si_state_viewport.c
> +++ b/src/gallium/drivers/radeonsi/si_state_viewport.c
> @@ -419,16 +419,13 @@ void si_update_vs_writes_viewport_index(struct si_context *ctx)
> if (ctx->viewports.dirty_mask ||
> ctx->viewports.depth_range_dirty_mask)
> si_mark_atom_dirty(ctx, &ctx->viewports.atom);
> }
>
> void si_init_viewport_functions(struct si_context *ctx)
> {
> ctx->scissors.atom.emit = si_emit_scissors;
> ctx->viewports.atom.emit = si_emit_viewport_states;
>
> - ctx->scissors.atom.num_dw = (2 + 16 * 2) + 6;
> - ctx->viewports.atom.num_dw = 2 + 16 * 6;
> -
> ctx->b.b.set_scissor_states = si_set_scissor_states;
> ctx->b.b.set_viewport_states = si_set_viewport_states;
> }
>
--
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.
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