[Mesa-dev] [PATCH 2/2] radeonsi: disable primitive binning on Vega10 (v2)

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

Our driver implementation is known to decrease performance for some tests,
but we don't know if any apps and benchmarks (e.g. those tested by Phoronix)
are affected. This disables the feature just to be safe.

Set this to enable partial primitive binning:
    R600_DEBUG=dpbb
Set this to enable full primitive binning:
    R600_DEBUG=dfsm

v2: add new debug options
---
 src/gallium/drivers/radeon/r600_pipe_common.c |  2 ++
 src/gallium/drivers/radeon/r600_pipe_common.h |  2 ++
 src/gallium/drivers/radeonsi/si_pipe.c        | 19 +++++++++++++++----
 3 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index 1fbf39c..76cca47 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -861,20 +861,22 @@ static const struct debug_named_value common_debug_options[] = {
 	{ "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
 	{ "nodcc", DBG(NO_DCC), "Disable DCC." },
 	{ "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
 	{ "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
 	{ "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
 	{ "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
 	{ "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" },
 	{ "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
 	{ "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
 	{ "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
+	{ "dpbb", DBG(DPBB), "Enable DPBB." },
+	{ "dfsm", DBG(DFSM), "Enable DFSM." },
 	{ "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
 
 	DEBUG_NAMED_VALUE_END /* must be last */
 };
 
 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 {
 	return "X.Org";
 }
 
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index 8c08eda..5a9e7fb 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -106,20 +106,22 @@ enum {
 	DBG_NO_ASYNC_DMA,
 	DBG_NO_DISCARD_RANGE,
 	DBG_NO_WC,
 	DBG_CHECK_VM,
 
 	/* 3D engine options: */
 	DBG_SWITCH_ON_EOP,
 	DBG_NO_OUT_OF_ORDER,
 	DBG_NO_DPBB,
 	DBG_NO_DFSM,
+	DBG_DPBB,
+	DBG_DFSM,
 	DBG_NO_HYPERZ,
 	DBG_NO_RB_PLUS,
 	DBG_NO_2D_TILING,
 	DBG_NO_TILING,
 	DBG_NO_DCC,
 	DBG_NO_DCC_CLEAR,
 	DBG_NO_DCC_FB,
 
 	/* Tests: */
 	DBG_TEST_DMA,
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index da5a97b..be37c25 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1054,24 +1054,35 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
 	sscreen->assume_no_z_fights =
 		driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
 	sscreen->commutative_blend_add =
 		driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
 	sscreen->clear_db_meta_before_clear =
 		driQueryOptionb(config->options, "radeonsi_clear_db_meta_before_clear");
 	sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
 					    sscreen->b.family <= CHIP_POLARIS12) ||
 					   sscreen->b.family == CHIP_VEGA10 ||
 					   sscreen->b.family == CHIP_RAVEN;
-	sscreen->dpbb_allowed = sscreen->b.chip_class >= GFX9 &&
-				!(sscreen->b.debug_flags & DBG(NO_DPBB));
-	sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
-				!(sscreen->b.debug_flags & DBG(NO_DFSM));
+
+	if (sscreen->b.debug_flags & DBG(DPBB)) {
+		sscreen->dpbb_allowed = true;
+	} else {
+		/* Only enable primitive binning on Raven by default. */
+		sscreen->dpbb_allowed = sscreen->b.family == CHIP_RAVEN &&
+					!(sscreen->b.debug_flags & DBG(NO_DPBB));
+	}
+
+	if (sscreen->b.debug_flags & DBG(DFSM)) {
+		sscreen->dfsm_allowed = sscreen->dpbb_allowed;
+	} else {
+		sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
+					!(sscreen->b.debug_flags & DBG(NO_DFSM));
+	}
 
 	/* While it would be nice not to have this flag, we are constrained
 	 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
 	 * on GFX9.
 	 */
 	sscreen->llvm_has_working_vgpr_indexing = sscreen->b.chip_class <= VI;
 
 	sscreen->b.has_cp_dma = true;
 	sscreen->b.has_streamout = true;
 
-- 
2.7.4