[Mesa-dev] [PATCH 7/7] amd: move r600d_common.h into r600g

Marek Olšák maraeo at gmail.com
Sat Oct 7 22:47:06 UTC 2017


From: Marek Olšák <marek.olsak at amd.com>

---
 src/amd/Makefile.sources                           |  1 -
 src/amd/vulkan/radv_cmd_buffer.c                   |  2 +-
 src/amd/vulkan/radv_cs.h                           | 14 +++++------
 src/amd/vulkan/radv_formats.c                      | 29 +++++++++++-----------
 src/amd/vulkan/radv_pipeline.c                     |  1 -
 src/amd/vulkan/radv_query.c                        |  2 +-
 src/amd/vulkan/radv_shader.c                       |  1 -
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.h      |  1 -
 src/gallium/drivers/r600/Makefile.sources          |  2 ++
 src/gallium/drivers/r600/r600_cs.h                 |  2 +-
 src/gallium/drivers/r600/r600_perfcounter.c        |  2 +-
 .../common => gallium/drivers/r600}/r600d_common.h |  0
 12 files changed, 27 insertions(+), 30 deletions(-)
 rename src/{amd/common => gallium/drivers/r600}/r600d_common.h (100%)

diff --git a/src/amd/Makefile.sources b/src/amd/Makefile.sources
index 4accab0..bacba23 100644
--- a/src/amd/Makefile.sources
+++ b/src/amd/Makefile.sources
@@ -1,14 +1,13 @@
 COMMON_HEADER_FILES = \
 	common/gfx9d.h \
 	common/sid.h \
-	common/r600d_common.h \
 	common/amd_family.h \
 	common/amd_kernel_code_t.h \
 	common/amdgpu_id.h
 
 ADDRLIB_FILES = \
 	addrlib/addrinterface.cpp \
 	addrlib/addrinterface.h \
 	addrlib/addrtypes.h \
 	addrlib/core/addrcommon.h \
 	addrlib/core/addrelemlib.cpp \
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 4820cfa..702036c 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3608,21 +3608,21 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,
 
 	MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
 
 	/* TODO: this is overkill. Probably should figure something out from
 	 * the stage mask. */
 
 	si_cs_emit_write_event_eop(cs,
 				   cmd_buffer->state.predicating,
 				   cmd_buffer->device->physical_device->rad_info.chip_class,
 				   false,
-				   EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
+				   V_028A90_BOTTOM_OF_PIPE_TS, 0,
 				   1, va, 2, value);
 
 	assert(cmd_buffer->cs->cdw <= cdw_max);
 }
 
 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
 		      VkEvent _event,
 		      VkPipelineStageFlags stageMask)
 {
 	RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h
index 0990270..8405976 100644
--- a/src/amd/vulkan/radv_cs.h
+++ b/src/amd/vulkan/radv_cs.h
@@ -21,70 +21,70 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  * IN THE SOFTWARE.
  */
 
 #ifndef RADV_CS_H
 #define RADV_CS_H
 
 #include <string.h>
 #include <stdint.h>
 #include <assert.h>
-#include "r600d_common.h"
+#include "sid.h"
 
 static inline unsigned radeon_check_space(struct radeon_winsys *ws,
                                       struct radeon_winsys_cs *cs,
                                       unsigned needed)
 {
         if (cs->max_dw - cs->cdw < needed)
                 ws->cs_grow(cs, needed);
         return cs->cdw + needed;
 }
 
 static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 {
-        assert(reg < R600_CONTEXT_REG_OFFSET);
+        assert(reg < SI_CONTEXT_REG_OFFSET);
         assert(cs->cdw + 2 + num <= cs->max_dw);
         assert(num);
         radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
-        radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2);
+        radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
 }
 
 static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 {
         radeon_set_config_reg_seq(cs, reg, 1);
         radeon_emit(cs, value);
 }
 
 static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 {
-        assert(reg >= R600_CONTEXT_REG_OFFSET);
+        assert(reg >= SI_CONTEXT_REG_OFFSET);
         assert(cs->cdw + 2 + num <= cs->max_dw);
         assert(num);
         radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
-        radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2);
+        radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
 }
 
 static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 {
         radeon_set_context_reg_seq(cs, reg, 1);
         radeon_emit(cs, value);
 }
 
 
 static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs,
 					      unsigned reg, unsigned idx,
 					      unsigned value)
 {
-	assert(reg >= R600_CONTEXT_REG_OFFSET);
+	assert(reg >= SI_CONTEXT_REG_OFFSET);
 	assert(cs->cdw + 3 <= cs->max_dw);
 	radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
-	radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
+	radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
 	radeon_emit(cs, value);
 }
 
 static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 {
 	assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
 	assert(cs->cdw + 2 + num <= cs->max_dw);
 	assert(num);
 	radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
 	radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index 2444541..88305ab 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -19,21 +19,20 @@
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  * IN THE SOFTWARE.
  */
 
 #include "radv_private.h"
 
 #include "vk_format.h"
 #include "sid.h"
-#include "r600d_common.h"
 
 #include "vk_util.h"
 
 #include "util/u_half.h"
 #include "util/format_srgb.h"
 #include "util/format_r11g11b10f.h"
 
 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
 					  int first_non_void)
 {
@@ -760,67 +759,67 @@ uint32_t radv_translate_dbformat(VkFormat format)
 	}
 }
 
 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap)
 {
 	const struct vk_format_description *desc = vk_format_description(format);
 
 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == VK_SWIZZLE_##swz)
 
 	if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32)
-		return V_0280A0_SWAP_STD;
+		return V_028C70_SWAP_STD;
 
 	if (desc->layout != VK_FORMAT_LAYOUT_PLAIN)
 		return ~0U;
 
 	switch (desc->nr_channels) {
 	case 1:
 		if (HAS_SWIZZLE(0,X))
-			return V_0280A0_SWAP_STD; /* X___ */
+			return V_028C70_SWAP_STD; /* X___ */
 		else if (HAS_SWIZZLE(3,X))
-			return V_0280A0_SWAP_ALT_REV; /* ___X */
+			return V_028C70_SWAP_ALT_REV; /* ___X */
 		break;
 	case 2:
 		if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
 		    (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
 		    (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
-			return V_0280A0_SWAP_STD; /* XY__ */
+			return V_028C70_SWAP_STD; /* XY__ */
 		else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
 			 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
 		         (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
 			/* YX__ */
-			return (do_endian_swap ? V_0280A0_SWAP_STD : V_0280A0_SWAP_STD_REV);
+			return (do_endian_swap ? V_028C70_SWAP_STD : V_028C70_SWAP_STD_REV);
 		else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
-			return V_0280A0_SWAP_ALT; /* X__Y */
+			return V_028C70_SWAP_ALT; /* X__Y */
 		else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
-			return V_0280A0_SWAP_ALT_REV; /* Y__X */
+			return V_028C70_SWAP_ALT_REV; /* Y__X */
 		break;
 	case 3:
 		if (HAS_SWIZZLE(0,X))
-			return (do_endian_swap ? V_0280A0_SWAP_STD_REV : V_0280A0_SWAP_STD);
+			return (do_endian_swap ? V_028C70_SWAP_STD_REV : V_028C70_SWAP_STD);
 		else if (HAS_SWIZZLE(0,Z))
-			return V_0280A0_SWAP_STD_REV; /* ZYX */
+			return V_028C70_SWAP_STD_REV; /* ZYX */
 		break;
 	case 4:
 		/* check the middle channels, the 1st and 4th channel can be NONE */
 		if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z)) {
-			return V_0280A0_SWAP_STD; /* XYZW */
+			return V_028C70_SWAP_STD; /* XYZW */
 		} else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y)) {
-			return V_0280A0_SWAP_STD_REV; /* WZYX */
+			return V_028C70_SWAP_STD_REV; /* WZYX */
 		} else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X)) {
-			return V_0280A0_SWAP_ALT; /* ZYXW */
+			return V_028C70_SWAP_ALT; /* ZYXW */
 		} else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W)) {
 			/* YZWX */
 			if (desc->is_array)
-				return V_0280A0_SWAP_ALT_REV;
+				return V_028C70_SWAP_ALT_REV;
 			else
-				return (do_endian_swap ? V_0280A0_SWAP_ALT : V_0280A0_SWAP_ALT_REV);
+				return (do_endian_swap ? V_028C70_SWAP_ALT : V_028C70_SWAP_ALT_REV);
 		}
 		break;
 	}
 	return ~0U;
 }
 
 bool radv_format_pack_clear_color(VkFormat format,
 				  uint32_t clear_vals[2],
 				  VkClearColorValue *value)
 {
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 60b1d3e..f174c40 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -33,21 +33,20 @@
 #include "nir/nir.h"
 #include "nir/nir_builder.h"
 #include "spirv/nir_spirv.h"
 #include "vk_util.h"
 
 #include <llvm-c/Core.h>
 #include <llvm-c/TargetMachine.h>
 
 #include "sid.h"
 #include "gfx9d.h"
-#include "r600d_common.h"
 #include "ac_binary.h"
 #include "ac_llvm_util.h"
 #include "ac_nir_to_llvm.h"
 #include "vk_format.h"
 #include "util/debug.h"
 #include "ac_exp_param.h"
 
 static void
 radv_pipeline_destroy(struct radv_device *device,
                       struct radv_pipeline *pipeline,
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index b2ef805..06045d6 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -1146,21 +1146,21 @@ void radv_CmdEndQuery(
 
 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
 		radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
 		radeon_emit(cs, va);
 		radeon_emit(cs, va >> 32);
 
 		si_cs_emit_write_event_eop(cs,
 					   false,
 					   cmd_buffer->device->physical_device->rad_info.chip_class,
 					   false,
-					   EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
+					   V_028A90_BOTTOM_OF_PIPE_TS, 0,
 					   1, avail_va, 0, 1);
 		break;
 	default:
 		unreachable("ending unhandled query type");
 	}
 }
 
 void radv_CmdWriteTimestamp(
     VkCommandBuffer                             commandBuffer,
     VkPipelineStageFlagBits                     pipelineStage,
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 285f42e..e0944a4 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -32,21 +32,20 @@
 #include "radv_shader.h"
 #include "nir/nir.h"
 #include "nir/nir_builder.h"
 #include "spirv/nir_spirv.h"
 
 #include <llvm-c/Core.h>
 #include <llvm-c/TargetMachine.h>
 
 #include "sid.h"
 #include "gfx9d.h"
-#include "r600d_common.h"
 #include "ac_binary.h"
 #include "ac_llvm_util.h"
 #include "ac_nir_to_llvm.h"
 #include "vk_format.h"
 #include "util/debug.h"
 #include "ac_exp_param.h"
 
 static const struct nir_shader_compiler_options nir_options = {
 	.vertex_id_zero_based = true,
 	.lower_scmp = true,
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.h b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.h
index 42d89ee..135d4fa 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.h
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.h
@@ -25,21 +25,20 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  * IN THE SOFTWARE.
  */
 
 #ifndef RADV_AMDGPU_CS_H
 #define RADV_AMDGPU_CS_H
 
 #include <string.h>
 #include <stdint.h>
 #include <assert.h>
-#include "r600d_common.h"
 #include <amdgpu.h>
 
 #include "radv_radeon_winsys.h"
 #include "radv_amdgpu_winsys.h"
 
 enum {
 	MAX_RINGS_PER_TYPE = 8
 };
 
 
diff --git a/src/gallium/drivers/r600/Makefile.sources b/src/gallium/drivers/r600/Makefile.sources
index c232d6a..60fdc05 100644
--- a/src/gallium/drivers/r600/Makefile.sources
+++ b/src/gallium/drivers/r600/Makefile.sources
@@ -1,11 +1,13 @@
+
 C_SOURCES = \
+	r600d_common.h \
 	compute_memory_pool.c \
 	compute_memory_pool.h \
 	eg_asm.c \
 	eg_debug.c \
 	eg_sq.h \
 	evergreen_compute.c \
 	evergreen_compute.h \
 	evergreen_compute_internal.h \
 	evergreend.h \
 	evergreen_hw_context.c \
diff --git a/src/gallium/drivers/r600/r600_cs.h b/src/gallium/drivers/r600/r600_cs.h
index 28bdf15..0efae09 100644
--- a/src/gallium/drivers/r600/r600_cs.h
+++ b/src/gallium/drivers/r600/r600_cs.h
@@ -24,21 +24,21 @@
  */
 
 /**
  * This file contains helpers for writing commands to commands streams.
  */
 
 #ifndef R600_CS_H
 #define R600_CS_H
 
 #include "r600_pipe_common.h"
-#include "amd/common/r600d_common.h"
+#include "r600d_common.h"
 
 /**
  * Return true if there is enough memory in VRAM and GTT for the buffers
  * added so far.
  *
  * \param vram      VRAM memory size not added to the buffer list yet
  * \param gtt       GTT memory size not added to the buffer list yet
  */
 static inline bool
 radeon_cs_memory_below_limit(struct r600_common_screen *screen,
diff --git a/src/gallium/drivers/r600/r600_perfcounter.c b/src/gallium/drivers/r600/r600_perfcounter.c
index 48f609b..f186acb 100644
--- a/src/gallium/drivers/r600/r600_perfcounter.c
+++ b/src/gallium/drivers/r600/r600_perfcounter.c
@@ -21,21 +21,21 @@
  * SOFTWARE.
  *
  * Authors:
  *  Nicolai Hähnle <nicolai.haehnle at amd.com>
  *
  */
 
 #include "util/u_memory.h"
 #include "r600_query.h"
 #include "r600_pipe_common.h"
-#include "amd/common/r600d_common.h"
+#include "r600d_common.h"
 
 /* Max counters per HW block */
 #define R600_QUERY_MAX_COUNTERS 16
 
 static struct r600_perfcounter_block *
 lookup_counter(struct r600_perfcounters *pc, unsigned index,
 	       unsigned *base_gid, unsigned *sub_index)
 {
 	struct r600_perfcounter_block *block = pc->blocks;
 	unsigned bid;
diff --git a/src/amd/common/r600d_common.h b/src/gallium/drivers/r600/r600d_common.h
similarity index 100%
rename from src/amd/common/r600d_common.h
rename to src/gallium/drivers/r600/r600d_common.h
-- 
2.7.4



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