[Mesa-dev] [PATCH 5/7] radeonsi: import cayman_msaa.c from drivers/radeon
Nicolai Hähnle
nhaehnle at gmail.com
Mon Oct 9 13:26:44 UTC 2017
On 08.10.2017 00:47, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> ---
> src/gallium/drivers/radeon/Makefile.sources | 1 -
> src/gallium/drivers/radeon/cayman_msaa.c | 269 --------------------------
> src/gallium/drivers/radeon/r600_pipe_common.c | 1 -
> src/gallium/drivers/radeon/r600_pipe_common.h | 25 ---
> src/gallium/drivers/radeonsi/Makefile.sources | 1 +
> src/gallium/drivers/radeonsi/si_pipe.c | 1 +
> src/gallium/drivers/radeonsi/si_pipe.h | 9 +
> src/gallium/drivers/radeonsi/si_state.c | 79 ++++++--
> src/gallium/drivers/radeonsi/si_state.h | 4 +
> src/gallium/drivers/radeonsi/si_state_msaa.c | 209 ++++++++++++++++++++
> 10 files changed, 292 insertions(+), 307 deletions(-)
> delete mode 100644 src/gallium/drivers/radeon/cayman_msaa.c
> create mode 100644 src/gallium/drivers/radeonsi/si_state_msaa.c
>
[snip]
> diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
> index 82f3962..3c6b7ca 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
[snip]
> @@ -3296,24 +3296,82 @@ static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
> S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
> S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
> /* always 1: */
> S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
> S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
> S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
> S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
> S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
> S_028A4C_FORCE_EOV_REZ_ENABLE(1);
>
> - si_common_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
> - sctx->ps_iter_samples,
> - sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
> - sc_mode_cntl_1);
> + int setup_samples = sctx->framebuffer.nr_samples > 1 ? sctx->framebuffer.nr_samples :
> + sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0;
> +
> + /* Required by OpenGL line rasterization.
> + *
> + * TODO: We should also enable perpendicular endcaps for AA lines,
> + * but that requires implementing line stippling in the pixel
> + * shader. SC can only do line stippling with axis-aligned
> + * endcaps.
> + */
> + unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
> +
> + if (setup_samples > 1) {
> + /* distance from the pixel center, indexed by log2(nr_samples) */
> + static unsigned max_dist[] = {
> + 0, /* unused */
> + 4, /* 2x MSAA */
> + 6, /* 4x MSAA */
> + 7, /* 8x MSAA */
cayman_msaa.c had 8 here, is that change intentional?
Cheers,
Nicolai
> + 8, /* 16x MSAA */
> + };
> + unsigned log_samples = util_logbase2(setup_samples);
> + unsigned log_ps_iter_samples =
> + util_logbase2(util_next_power_of_two(sctx->ps_iter_samples));
> +
> + radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
> + radeon_emit(cs, sc_line_cntl |
> + S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
> + radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
> + S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
> + S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
> +
> + if (sctx->framebuffer.nr_samples > 1) {
> + radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
> + S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
> + S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
> + S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
> + S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
> + S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
> + S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
> + radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
> + EG_S_028A4C_PS_ITER_SAMPLE(sctx->ps_iter_samples > 1) |
> + sc_mode_cntl_1);
> + } else if (sctx->smoothing_enabled) {
> + radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
> + S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
> + S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
> + S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
> + radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
> + sc_mode_cntl_1);
> + }
> + } else {
> + radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
> + radeon_emit(cs, sc_line_cntl); /* CM_R_028BDC_PA_SC_LINE_CNTL */
> + radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
> +
> + radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
> + S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
> + S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
> + radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
> + sc_mode_cntl_1);
> + }
>
> /* GFX9: Flush DFSM when the AA mode changes. */
> if (sctx->screen->dfsm_allowed) {
> radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
> radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
> }
> }
>
> static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
> {
> @@ -4440,21 +4498,20 @@ void si_init_state_functions(struct si_context *sctx)
> sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
> sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
> sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
> sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
> sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
>
> sctx->b.b.set_clip_state = si_set_clip_state;
> sctx->b.b.set_stencil_ref = si_set_stencil_ref;
>
> sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
> - sctx->b.b.get_sample_position = si_get_sample_position;
>
> sctx->b.b.create_sampler_state = si_create_sampler_state;
> sctx->b.b.delete_sampler_state = si_delete_sampler_state;
>
> sctx->b.b.create_sampler_view = si_create_sampler_view;
> sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
>
> sctx->b.b.set_sample_mask = si_set_sample_mask;
>
> sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
> diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
> index a686d0d..8122ddb 100644
> --- a/src/gallium/drivers/radeonsi/si_state.h
> +++ b/src/gallium/drivers/radeonsi/si_state.h
> @@ -416,20 +416,24 @@ void si_emit_cache_flush(struct si_context *sctx);
> void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
> void si_draw_rectangle(struct blitter_context *blitter,
> void *vertex_elements_cso,
> blitter_get_vs_func get_vs,
> int x1, int y1, int x2, int y2,
> float depth, unsigned num_instances,
> enum blitter_attrib_type type,
> const union blitter_attrib *attrib);
> void si_trace_emit(struct si_context *sctx);
>
> +/* si_state_msaa.c */
> +void si_init_msaa_functions(struct si_context *sctx);
> +void si_emit_sample_locations(struct radeon_winsys_cs *cs, int nr_samples);
> +
> /* si_state_streamout.c */
> void si_streamout_buffers_dirty(struct si_context *sctx);
> void si_emit_streamout_end(struct si_context *sctx);
> void si_update_prims_generated_query_state(struct si_context *sctx,
> unsigned type, int diff);
> void si_init_streamout_functions(struct si_context *sctx);
>
>
> static inline unsigned
> si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
> diff --git a/src/gallium/drivers/radeonsi/si_state_msaa.c b/src/gallium/drivers/radeonsi/si_state_msaa.c
> new file mode 100644
> index 0000000..977f54b
> --- /dev/null
> +++ b/src/gallium/drivers/radeonsi/si_state_msaa.c
> @@ -0,0 +1,209 @@
> +/*
> + * Copyright 2014 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + *
> + * Authors: Marek Olšák <maraeo at gmail.com>
> + *
> + */
> +
> +#include "si_pipe.h"
> +#include "sid.h"
> +#include "radeon/r600_cs.h"
> +
> +/* For MSAA sample positions. */
> +#define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
> + (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
> + (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
> + (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
> + (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
> +
> +/* 2xMSAA
> + * There are two locations (4, 4), (-4, -4). */
> +static const uint32_t sample_locs_2x[4] = {
> + FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
> + FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
> + FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
> + FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
> +};
> +/* 4xMSAA
> + * There are 4 locations: (-2, -6), (6, -2), (-6, 2), (2, 6). */
> +static const uint32_t sample_locs_4x[4] = {
> + FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
> + FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
> + FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
> + FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
> +};
> +
> +/* Cayman 8xMSAA */
> +static const uint32_t sample_locs_8x[] = {
> + FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
> + FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
> + FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
> + FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
> + FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
> + FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
> + FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
> + FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
> +};
> +/* Cayman 16xMSAA */
> +static const uint32_t sample_locs_16x[] = {
> + FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
> + FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
> + FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
> + FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
> + FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
> + FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
> + FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
> + FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
> + FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
> + FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
> + FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
> + FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
> + FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
> + FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
> + FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
> + FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
> +};
> +
> +static void si_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
> + unsigned sample_index, float *out_value)
> +{
> + int offset, index;
> + struct {
> + int idx:4;
> + } val;
> +
> + switch (sample_count) {
> + case 1:
> + default:
> + out_value[0] = out_value[1] = 0.5;
> + break;
> + case 2:
> + offset = 4 * (sample_index * 2);
> + val.idx = (sample_locs_2x[0] >> offset) & 0xf;
> + out_value[0] = (float)(val.idx + 8) / 16.0f;
> + val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
> + out_value[1] = (float)(val.idx + 8) / 16.0f;
> + break;
> + case 4:
> + offset = 4 * (sample_index * 2);
> + val.idx = (sample_locs_4x[0] >> offset) & 0xf;
> + out_value[0] = (float)(val.idx + 8) / 16.0f;
> + val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
> + out_value[1] = (float)(val.idx + 8) / 16.0f;
> + break;
> + case 8:
> + offset = 4 * (sample_index % 4 * 2);
> + index = (sample_index / 4) * 4;
> + val.idx = (sample_locs_8x[index] >> offset) & 0xf;
> + out_value[0] = (float)(val.idx + 8) / 16.0f;
> + val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
> + out_value[1] = (float)(val.idx + 8) / 16.0f;
> + break;
> + case 16:
> + offset = 4 * (sample_index % 4 * 2);
> + index = (sample_index / 4) * 4;
> + val.idx = (sample_locs_16x[index] >> offset) & 0xf;
> + out_value[0] = (float)(val.idx + 8) / 16.0f;
> + val.idx = (sample_locs_16x[index] >> (offset + 4)) & 0xf;
> + out_value[1] = (float)(val.idx + 8) / 16.0f;
> + break;
> + }
> +}
> +
> +void si_emit_sample_locations(struct radeon_winsys_cs *cs, int nr_samples)
> +{
> + switch (nr_samples) {
> + default:
> + case 1:
> + radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
> + radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
> + radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
> + radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
> + break;
> + case 2:
> + radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
> + radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
> + radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
> + radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
> + break;
> + case 4:
> + radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
> + radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
> + radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
> + radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
> + break;
> + case 8:
> + radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
> + radeon_emit(cs, sample_locs_8x[0]);
> + radeon_emit(cs, sample_locs_8x[4]);
> + radeon_emit(cs, 0);
> + radeon_emit(cs, 0);
> + radeon_emit(cs, sample_locs_8x[1]);
> + radeon_emit(cs, sample_locs_8x[5]);
> + radeon_emit(cs, 0);
> + radeon_emit(cs, 0);
> + radeon_emit(cs, sample_locs_8x[2]);
> + radeon_emit(cs, sample_locs_8x[6]);
> + radeon_emit(cs, 0);
> + radeon_emit(cs, 0);
> + radeon_emit(cs, sample_locs_8x[3]);
> + radeon_emit(cs, sample_locs_8x[7]);
> + break;
> + case 16:
> + radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
> + radeon_emit(cs, sample_locs_16x[0]);
> + radeon_emit(cs, sample_locs_16x[4]);
> + radeon_emit(cs, sample_locs_16x[8]);
> + radeon_emit(cs, sample_locs_16x[12]);
> + radeon_emit(cs, sample_locs_16x[1]);
> + radeon_emit(cs, sample_locs_16x[5]);
> + radeon_emit(cs, sample_locs_16x[9]);
> + radeon_emit(cs, sample_locs_16x[13]);
> + radeon_emit(cs, sample_locs_16x[2]);
> + radeon_emit(cs, sample_locs_16x[6]);
> + radeon_emit(cs, sample_locs_16x[10]);
> + radeon_emit(cs, sample_locs_16x[14]);
> + radeon_emit(cs, sample_locs_16x[3]);
> + radeon_emit(cs, sample_locs_16x[7]);
> + radeon_emit(cs, sample_locs_16x[11]);
> + radeon_emit(cs, sample_locs_16x[15]);
> + break;
> + }
> +}
> +
> +void si_init_msaa_functions(struct si_context *sctx)
> +{
> + int i;
> +
> + sctx->b.b.get_sample_position = si_get_sample_position;
> +
> + si_get_sample_position(&sctx->b.b, 1, 0, sctx->sample_locations_1x[0]);
> +
> + for (i = 0; i < 2; i++)
> + si_get_sample_position(&sctx->b.b, 2, i, sctx->sample_locations_2x[i]);
> + for (i = 0; i < 4; i++)
> + si_get_sample_position(&sctx->b.b, 4, i, sctx->sample_locations_4x[i]);
> + for (i = 0; i < 8; i++)
> + si_get_sample_position(&sctx->b.b, 8, i, sctx->sample_locations_8x[i]);
> + for (i = 0; i < 16; i++)
> + si_get_sample_position(&sctx->b.b, 16, i, sctx->sample_locations_16x[i]);
> +}
>
--
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