[Mesa-dev] [PATCH] i965/tes: account for the fact that dvec3/4 inputs take two slots
kenneth at whitecape.org
Tue Oct 10 06:56:12 UTC 2017
On Monday, October 9, 2017 11:51:24 PM PDT Iago Toral Quiroga wrote:
> When computing the total size of the URB for tessellation evaluation
> inputs we were not accounting for this, and instead we were always
> assuming that each input would take a single vec4 slot, which could
> lead to computing a smaller read size than required. Specifically, this
> is a problem when the last input is a dvec3/4 such that its XY components
> are stored in the the second half of a payload register (which can happen
> if the offset for the input in the URB is not 64-bit aligned because
> there are 23-bit inputs mixed in) and the ZW components in the
> first half of the next, as in this case we would fail to account for the
> extra slot required for the ZW components.
> src/intel/compiler/brw_fs_nir.cpp | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
Oh, great find! Thanks Iago!
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
-------------- next part --------------
A non-text attachment was scrubbed...
Size: 833 bytes
Desc: This is a digitally signed message part.
More information about the mesa-dev