[Mesa-dev] [PATCH 2/4] radv: do not set registers for merged ES-GS on GFX9

[Samuel Pitoiset]

Based on RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
---
 src/amd/vulkan/si_cmd_buffer.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index f5dc26d392..626b68ad8e 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -343,8 +343,11 @@ si_emit_config(struct radv_physical_device *physical_device,
 	radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
 
 	/* FIXME calculate these values somehow ??? */
-	radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
-	radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
+	if (physical_device->rad_info.chip_class <= VI) {
+		radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
+		radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
+	}
+
 	radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
 
 	radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
-- 
2.14.2