[Mesa-dev] [PATCH v3 15/43] i965: Add support for control register

Jose Maria Casanova Crespo jmcasanova at igalia.com
Thu Oct 12 18:38:04 UTC 2017

Control register cr0 in i965 can be used to change the rounding modes
in 32-bit to 16-bit floating-point conversions.

>From intel Skylake PRM, vol 07, section "Register and Tegister Regions",
 subsection "Control Register" (page 754):

"Subregister cr0.0:ud contains normal operation control fields such as the
 floating-point mode ... "

Floating-point Rounding mode is changed at bits 5:4 of cr0.0:

"Rounding Mode. This field specifies the FPU rounding mode. It is
initialized by Thread Dispatch."
  00b = Round to Nearest or Even (RTNE)
  01b = Round Up, toward +inf (RU)
  10b = Round Down, toward -inf (RD)
  11b = Round Toward Zero (RTZ)"
 src/intel/compiler/brw_reg.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h
index 441dfb2447..d4ebb637e9 100644
--- a/src/intel/compiler/brw_reg.h
+++ b/src/intel/compiler/brw_reg.h
@@ -806,6 +806,12 @@ brw_notification_reg(void)
 static inline struct brw_reg
+brw_cr0_reg(unsigned subnr)
+static inline struct brw_reg
 brw_sr0_reg(unsigned subnr)
    return brw_ud1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_STATE, subnr);

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