[Mesa-dev] [PATCH v3 41/43] i965/fs: Predicate byte scattered writes if needed

[Jose Maria Casanova Crespo]

From: Alejandro Piñeiro <apinheiro at igalia.com>

While on Untyped Surface messages the bits of the execution mask are
ANDed with the corresponding bits of the Pixel/Sample Mask, that is
not the case for byte scattered writes. That is needed to avoid ssbo
stores writing on helper invocations. So when that can affect, we load
the sample mask, and predicate the send message.

Note: the need for this patch was tested with a custom test. Right now
the 16 bit storage CTS tests doesnt need this path in order to get a
full pass.
---
 src/intel/compiler/brw_fs_nir.cpp | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 332fc4bfb8..c04d2a4eb4 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -4315,11 +4315,23 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
              * to rely on byte scattered in order to write 16-bit elements.
              * The byte_scattered_write message needs that every written 16-bit
              * type to be aligned 32-bits (stride=2).
+             * Additionally, while on Untyped Surface messages the
+             * bits of the execution mask are ANDed with the corresponding
+             * bits of the Pixel/Sample Mask, that is not the case for byte
+             * scattered writes. That is needed to avoid ssbo stores writing
+             * on helper invocations. So when that can affect, we load the
+             * sample mask, and predicate the send message.
              */
+            brw_predicate pred = BRW_PREDICATE_NONE;
+
+            if (stage == MESA_SHADER_FRAGMENT) {
+               bld.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS);
+               pred = BRW_PREDICATE_NORMAL;
+            }
             emit_byte_scattered_write(bld, surf_index, offset_reg,
                                       current_val_reg,
                                       1 /* dims */, length * type_slots,
-                                      BRW_PREDICATE_NONE);
+                                      pred);
          } else {
             unsigned write_size = length * type_slots;
 
-- 
2.13.6