[Mesa-dev] [PATCH] radv: do not allocate CMASK for non-MSSA images with 128 bit formats

Bas Nieuwenhuizen bas at basnieuwenhuizen.nl
Thu Oct 12 22:44:45 UTC 2017


r-b

On Thu, Oct 12, 2017 at 4:55 PM, Samuel Pitoiset
<samuel.pitoiset at gmail.com> wrote:
> This saves some useless CMASK initializations/eliminations in
> the Vulkan SSAO demo.
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 2 +-
>  src/amd/vulkan/radv_image.c      | 8 ++++++++
>  src/amd/vulkan/radv_meta_clear.c | 5 -----
>  3 files changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
> index 99a48242c9..a7efcdc218 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -3537,7 +3537,7 @@ static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
>                                                    dst_queue_mask, range,
>                                                    pending_clears);
>
> -       if (image->cmask.size)
> +       if (image->cmask.size || image->fmask.size)
>                 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
>                                                    dst_layout, src_queue_mask,
>                                                    dst_queue_mask, range);
> diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
> index 7c3e55b1b8..0564454c77 100644
> --- a/src/amd/vulkan/radv_image.c
> +++ b/src/amd/vulkan/radv_image.c
> @@ -819,6 +819,14 @@ radv_image_can_enable_dcc(struct radv_image *image)
>  static inline bool
>  radv_image_can_enable_cmask(struct radv_image *image)
>  {
> +       if (image->surface.bpe > 8 && image->info.samples == 1) {
> +               /* Do not enable CMASK for non-MSAA images (fast color clear)
> +                * because 128 bit formats are not supported, but FMASK might
> +                * still be used.
> +                */
> +               return false;
> +       }
> +
>         return radv_image_can_enable_dcc_or_cmask(image) &&
>                image->info.levels == 1 &&
>                image->info.depth == 1 &&
> diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
> index d148a75c19..402271ae4f 100644
> --- a/src/amd/vulkan/radv_meta_clear.c
> +++ b/src/amd/vulkan/radv_meta_clear.c
> @@ -1029,11 +1029,6 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
>                 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
>                                                   !can_avoid_fast_clear_elim);
>         } else {
> -
> -               if (iview->image->surface.bpe > 8) {
> -                       /* 128 bit formats not supported */
> -                       return false;
> -               }
>                 radv_fill_buffer(cmd_buffer, iview->image->bo,
>                                  iview->image->offset + iview->image->cmask.offset,
>                                  iview->image->cmask.size, 0);
> --
> 2.14.2
>
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