[Mesa-dev] [PATCH v2 27/52] intel/cs: Re-run final NIR optimizations for each SIMD size

Jason Ekstrand jason at jlekstrand.net
Fri Oct 13 05:47:53 UTC 2017

With the advent of SPIR-V subgroup operations, compute shaders will have
to be slightly different depending on the SIMD size at which they
execute.  In order to allow us to do dispatch-width specific things in
NIR, we re-run the final NIR stages for each sIMD width.

As a side-effect of this change, we start using ralloc on fs_visitor so
we need to add DECLARE_RALLOC_OPERATORS to fs_visitor.
 src/intel/compiler/brw_fs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index d3ab385..9ff06b6 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -60,7 +60,7 @@ offset(const fs_reg &reg, const brw::fs_builder &bld, unsigned delta)
 class fs_visitor : public backend_shader
    fs_visitor(const struct brw_compiler *compiler, void *log_data,
               void *mem_ctx,

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