[Mesa-dev] [PATCH 8/9] radv: add radv_emit_shaders_prefetch()

[Bas Nieuwenhuizen]

On Tue, Oct 17, 2017 at 11:03 AM, Samuel Pitoiset
<samuel.pitoiset at gmail.com> wrote:
> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 38 ++++++++++++++++++++++++++------------
>  1 file changed, 26 insertions(+), 12 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
> index ec4e34966c..e72ef5ffb7 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -606,6 +606,30 @@ radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
>                 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
>  }
>
> +static void
> +radv_emit_shaders_prefetch(struct radv_cmd_buffer *cmd_buffer,
> +                          struct radv_pipeline *pipeline)
> +{
> +       radv_emit_shader_prefetch(cmd_buffer,
> +                                 pipeline->shaders[MESA_SHADER_VERTEX]);

Do this per stage instead of grouping, and also check the vertex
shader for NULL. Consequence of the merged shaders on vega.

> +
> +       if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
> +               radv_emit_shader_prefetch(cmd_buffer,
> +                                         pipeline->shaders[MESA_SHADER_TESS_CTRL]);
> +               radv_emit_shader_prefetch(cmd_buffer,
> +                                         pipeline->shaders[MESA_SHADER_TESS_EVAL]);
> +       }
> +
> +       if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
> +               radv_emit_shader_prefetch(cmd_buffer,
> +                                         pipeline->shaders[MESA_SHADER_GEOMETRY]);
> +               radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
> +       }
> +
> +       radv_emit_shader_prefetch(cmd_buffer,
> +                                 pipeline->shaders[MESA_SHADER_FRAGMENT]);
> +}
> +
>  static void
>  radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
>                 struct radv_pipeline *pipeline,
> @@ -615,8 +639,6 @@ radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
>         uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
>         unsigned export_count;
>
> -       radv_emit_shader_prefetch(cmd_buffer, shader);
> -
>         export_count = MAX2(1, outinfo->param_exports);
>         radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
>                                S_0286C4_VS_EXPORT_COUNT(export_count - 1));
> @@ -662,8 +684,6 @@ radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
>  {
>         uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
>
> -       radv_emit_shader_prefetch(cmd_buffer, shader);
> -
>         radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
>                                outinfo->esgs_itemsize / 4);
>         radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
> @@ -680,8 +700,6 @@ radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
>         uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
>         uint32_t rsrc2 = shader->rsrc2;
>
> -       radv_emit_shader_prefetch(cmd_buffer, shader);
> -
>         radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
>         radeon_emit(cmd_buffer->cs, va >> 8);
>         radeon_emit(cmd_buffer->cs, va >> 40);
> @@ -702,8 +720,6 @@ radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
>  {
>         uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
>
> -       radv_emit_shader_prefetch(cmd_buffer, shader);
> -
>         radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
>         radeon_emit(cmd_buffer->cs, va >> 8);
>         radeon_emit(cmd_buffer->cs, va >> 40);
> @@ -835,8 +851,6 @@ radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
>
>         va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
>
> -       radv_emit_shader_prefetch(cmd_buffer, gs);
> -
>         radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
>         radeon_emit(cmd_buffer->cs, va >> 8);
>         radeon_emit(cmd_buffer->cs, va >> 40);
> @@ -875,8 +889,6 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
>         ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
>         va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
>
> -       radv_emit_shader_prefetch(cmd_buffer, ps);
> -
>         radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
>         radeon_emit(cmd_buffer->cs, va >> 8);
>         radeon_emit(cmd_buffer->cs, va >> 40);
> @@ -953,6 +965,8 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
>         radv_emit_fragment_shader(cmd_buffer, pipeline);
>         radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
>
> +       radv_emit_shaders_prefetch(cmd_buffer, pipeline);
> +
>         cmd_buffer->scratch_size_needed =
>                                   MAX2(cmd_buffer->scratch_size_needed,
>                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
> --
> 2.14.2
>
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