[Mesa-dev] [PATCH v3 34/34] i965: Initialize disk shader cache if MESA_GLSL_CACHE_DISABLE is false

[Jordan Justen]

Double negative FTW!

For now, the shader cache is disabled by default on i965 to allow us
to verify its stability.

In other words, to enable the shader cache on i965, set
MESA_GLSL_CACHE_DISABLE to false or 0. If the variable is unset, then
the shader cache will be disabled.

We use the build-id of i965_dri.so for the timestamp, and the pci
device id for the device name.

v2:
 * Simplify code by forcing link to include build id sha. (Matt)

v3:
 * Don't use a for loop with snprintf for bin to hex. (Matt)
 * Assume fixed length render and timestamp string to further simplify
   code.

Cc: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_context.c    |  2 ++
 src/mesa/drivers/dri/i965/brw_disk_cache.c | 29 +++++++++++++++++++++++++++++
 src/mesa/drivers/dri/i965/brw_state.h      |  1 +
 3 files changed, 32 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 949ec4a2a3d..bb9474035c9 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1037,6 +1037,8 @@ brwCreateContext(gl_api api,
                          brw->dri_config_options_sha1);
    brw->ctx.Const.dri_config_options_sha1 = brw->dri_config_options_sha1;
 
+   brw_disk_cache_init(brw);
+
    return true;
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_disk_cache.c b/src/mesa/drivers/dri/i965/brw_disk_cache.c
index 9af893d40a7..22670e31667 100644
--- a/src/mesa/drivers/dri/i965/brw_disk_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_disk_cache.c
@@ -26,6 +26,8 @@
 #include "compiler/glsl/shader_cache.h"
 #include "compiler/nir/nir_serialize.h"
 #include "main/mtypes.h"
+#include "util/build_id.h"
+#include "util/debug.h"
 #include "util/disk_cache.h"
 #include "util/macros.h"
 #include "util/mesa-sha1.h"
@@ -460,3 +462,30 @@ brw_disk_cache_write_compute_program(struct brw_context *brw)
                          MESA_SHADER_COMPUTE);
    }
 }
+
+void
+brw_disk_cache_init(struct brw_context *brw)
+{
+#ifdef ENABLE_SHADER_CACHE
+   if (env_var_as_boolean("MESA_GLSL_CACHE_DISABLE", true))
+      return;
+
+   char renderer[10];
+   int len = snprintf(renderer, sizeof(renderer), "i965_%04x",
+                      brw->screen->deviceID);
+   assert(len == sizeof(renderer) - 1);
+
+   const struct build_id_note *note =
+      build_id_find_nhdr_for_addr(brw_disk_cache_init);
+   int id_size = build_id_length(note);
+   assert(note && id_size == 20 /* sha1 */);
+
+   const uint8_t *id_sha1 = build_id_data(note);
+   assert(id_sha1);
+
+   char timestamp[41];
+   _mesa_sha1_format(timestamp, id_sha1);
+
+   brw->ctx.Cache = disk_cache_create(renderer, timestamp, 0);
+#endif
+}
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index c98b7facd57..927e77920ef 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -132,6 +132,7 @@ void gen8_write_pma_stall_bits(struct brw_context *brw,
                                uint32_t pma_stall_bits);
 
 /* brw_disk_cache.c */
+void brw_disk_cache_init(struct brw_context *brw);
 bool brw_disk_cache_upload_program(struct brw_context *brw,
                                    gl_shader_stage stage);
 void brw_disk_cache_write_compute_program(struct brw_context *brw);
-- 
2.15.0.rc0