[Mesa-dev] [PATCH] radv: only emit dfsm packets if dfsm is allowed.

[Bas Nieuwenhuizen]

r-b

On Tue, Oct 24, 2017 at 5:04 AM, Dave Airlie <airlied at gmail.com> wrote:
> From: Dave Airlie <airlied at redhat.com>
>
> radeonsi only emits these when dfsm is enabled, so for now
> just hinge them on a flag we never set.
>
> Signed-off-by: Dave Airlie <airlied at redhat.com>
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 6 +++---
>  src/amd/vulkan/radv_private.h    | 1 +
>  2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
> index ba382c8691b..807283be1d8 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -551,7 +551,7 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
>         radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
>
>         /* GFX9: Flush DFSM when the AA mode changes. */
> -       if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
> +       if (cmd_buffer->device->dfsm_allowed) {
>                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
>                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
>         }
> @@ -956,7 +956,7 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
>         radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
>         radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
>
> -       if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
> +       if (cmd_buffer->device->dfsm_allowed) {
>                 /* optimise this? */
>                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
>                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
> @@ -1443,7 +1443,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
>                                S_028208_BR_X(framebuffer->width) |
>                                S_028208_BR_Y(framebuffer->height));
>
> -       if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
> +       if (cmd_buffer->device->dfsm_allowed) {
>                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
>                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
>         }
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index a4e52b25306..83529015c5d 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -531,6 +531,7 @@ struct radv_device {
>
>         bool llvm_supports_spill;
>         bool has_distributed_tess;
> +       bool dfsm_allowed;
>         uint32_t tess_offchip_block_dw_size;
>         uint32_t scratch_waves;
>
> --
> 2.14.2
>
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