[Mesa-dev] [PATCH 2/3] radeonsi: enable signed vertex buffer offsets
Marek Olšák
maraeo at gmail.com
Thu Oct 26 15:31:01 UTC 2017
From: Marek Olšák <marek.olsak at amd.com>
---
src/gallium/drivers/radeonsi/si_descriptors.c | 25 +++++++++++--------------
src/gallium/drivers/radeonsi/si_pipe.c | 2 +-
2 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index da6efa8..0502a42 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -991,21 +991,20 @@ static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
RADEON_PRIO_DESCRIPTORS);
}
bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
{
struct si_vertex_elements *velems = sctx->vertex_elements;
struct si_descriptors *desc = &sctx->vertex_buffers;
unsigned i, count;
unsigned desc_list_byte_size;
unsigned first_vb_use_mask;
- uint64_t va;
uint32_t *ptr;
if (!sctx->vertex_buffers_dirty || !velems)
return true;
count = velems->count;
if (!count)
return true;
@@ -1031,48 +1030,46 @@ bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
desc->list = ptr;
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
desc->buffer, RADEON_USAGE_READ,
RADEON_PRIO_DESCRIPTORS);
assert(count <= SI_MAX_ATTRIBS);
for (i = 0; i < count; i++) {
struct pipe_vertex_buffer *vb;
struct r600_resource *rbuffer;
- unsigned offset;
unsigned vbo_index = velems->vertex_buffer_index[i];
uint32_t *desc = &ptr[i*4];
vb = &sctx->vertex_buffer[vbo_index];
rbuffer = (struct r600_resource*)vb->buffer.resource;
if (!rbuffer) {
memset(desc, 0, 16);
continue;
}
- offset = vb->buffer_offset + velems->src_offset[i];
- va = rbuffer->gpu_address + offset;
-
- /* Fill in T# buffer resource description */
- desc[0] = va;
- desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
- S_008F04_STRIDE(vb->stride);
+ int offset = (int)vb->buffer_offset + (int)velems->src_offset[i];
+ int64_t va = (int64_t)rbuffer->gpu_address + offset;
+ assert(va > 0);
+ int64_t num_records = (int64_t)rbuffer->b.b.width0 - offset;
if (sctx->b.chip_class != VI && vb->stride) {
/* Round up by rounding down and adding 1 */
- desc[2] = (vb->buffer.resource->width0 - offset -
- velems->format_size[i]) /
- vb->stride + 1;
- } else {
- desc[2] = vb->buffer.resource->width0 - offset;
+ num_records = (num_records - velems->format_size[i]) /
+ vb->stride + 1;
}
+ assert(num_records >= 0 && num_records <= UINT_MAX);
+ desc[0] = va;
+ desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
+ S_008F04_STRIDE(vb->stride);
+ desc[2] = num_records;
desc[3] = velems->rsrc_word3[i];
if (first_vb_use_mask & (1 << i)) {
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
(struct r600_resource*)vb->buffer.resource,
RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
}
}
/* Don't flush the const cache. It would have a very negative effect
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 51f13a0..856eb93 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -500,20 +500,21 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
case PIPE_CAP_QUERY_SO_OVERFLOW:
case PIPE_CAP_MEMOBJ:
case PIPE_CAP_LOAD_CONSTBUF:
case PIPE_CAP_INT64:
case PIPE_CAP_INT64_DIVMOD:
case PIPE_CAP_TGSI_CLOCK:
case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
+ case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
return 1;
case PIPE_CAP_TGSI_VOTE:
return HAVE_LLVM >= 0x0400;
case PIPE_CAP_TGSI_BALLOT:
return HAVE_LLVM >= 0x0500;
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
@@ -582,21 +583,20 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
case PIPE_CAP_VERTEXID_NOBASE:
case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
case PIPE_CAP_MAX_WINDOW_RECTANGLES:
case PIPE_CAP_TGSI_FS_FBFETCH:
case PIPE_CAP_TGSI_MUL_ZERO_WINS:
case PIPE_CAP_UMA:
case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
case PIPE_CAP_POST_DEPTH_COVERAGE:
case PIPE_CAP_TILE_RASTER_ORDER:
- case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
return 0;
case PIPE_CAP_NATIVE_FENCE_FD:
return sscreen->b.info.has_sync_file;
case PIPE_CAP_QUERY_BUFFER_OBJECT:
return si_have_tgsi_compute(sscreen);
case PIPE_CAP_DRAW_PARAMETERS:
case PIPE_CAP_MULTI_DRAW_INDIRECT:
--
2.7.4
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