[Mesa-dev] [PATCH 1/2] radv: make radv_fill_buffer() return the needed flush bits
Bas Nieuwenhuizen
bas at basnieuwenhuizen.nl
Thu Oct 26 18:17:51 UTC 2017
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
for the series.
On Thu, Oct 26, 2017 at 6:03 PM, Samuel Pitoiset
<samuel.pitoiset at gmail.com> wrote:
> Only needed when the CS path is used.
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 46 +++++++++++++++++------------------
> src/amd/vulkan/radv_meta_buffer.c | 13 +++++++---
> src/amd/vulkan/radv_meta_clear.c | 50 +++++++++++++++++----------------------
> src/amd/vulkan/radv_private.h | 6 ++---
> 4 files changed, 57 insertions(+), 58 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
> index 08a05277fa..31f0ae227c 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -3640,16 +3640,15 @@ static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
> uint64_t size = image->surface.htile_slice_size * layer_count;
> uint64_t offset = image->offset + image->htile_offset +
> image->surface.htile_slice_size * range->baseArrayLayer;
> + struct radv_cmd_state *state = &cmd_buffer->state;
>
> - cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
> - RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
> + state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
> + RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
>
> - radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
> + state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
> + size, clear_word);
>
> - cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
> - RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
> - RADV_CMD_FLAG_INV_VMEM_L1 |
> - RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
> + state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
> }
>
> static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
> @@ -3695,16 +3694,16 @@ static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffe
> void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
> struct radv_image *image, uint32_t value)
> {
> - cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
> - RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
> + struct radv_cmd_state *state = &cmd_buffer->state;
>
> - radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
> - image->cmask.size, value);
> + state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
> + RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
>
> - cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
> - RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
> - RADV_CMD_FLAG_INV_VMEM_L1 |
> - RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
> + state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
> + image->offset + image->cmask.offset,
> + image->cmask.size, value);
> +
> + state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
> }
>
> static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
> @@ -3729,18 +3728,17 @@ static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffe
> void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
> struct radv_image *image, uint32_t value)
> {
> + struct radv_cmd_state *state = &cmd_buffer->state;
>
> - cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
> - RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
> + state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
> + RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
>
> - radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
> - image->surface.dcc_size, value);
> + state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
> + image->offset + image->dcc_offset,
> + image->surface.dcc_size, value);
>
> - cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
> - RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
> - RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
> - RADV_CMD_FLAG_INV_VMEM_L1 |
> - RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
> + state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
> + RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
> }
>
> static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
> diff --git a/src/amd/vulkan/radv_meta_buffer.c b/src/amd/vulkan/radv_meta_buffer.c
> index a737dbeec3..f7ffcbbc90 100644
> --- a/src/amd/vulkan/radv_meta_buffer.c
> +++ b/src/amd/vulkan/radv_meta_buffer.c
> @@ -404,21 +404,28 @@ static void copy_buffer_shader(struct radv_cmd_buffer *cmd_buffer,
> }
>
>
> -void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
> +uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
> struct radeon_winsys_bo *bo,
> uint64_t offset, uint64_t size, uint32_t value)
> {
> + uint32_t flush_bits = 0;
> +
> assert(!(offset & 3));
> assert(!(size & 3));
>
> - if (size >= RADV_BUFFER_OPS_CS_THRESHOLD)
> + if (size >= RADV_BUFFER_OPS_CS_THRESHOLD) {
> fill_buffer_shader(cmd_buffer, bo, offset, size, value);
> - else if (size) {
> + flush_bits = RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
> + RADV_CMD_FLAG_INV_VMEM_L1 |
> + RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
> + } else if (size) {
> uint64_t va = radv_buffer_get_va(bo);
> va += offset;
> cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
> si_cp_dma_clear_buffer(cmd_buffer, va, size, value);
> }
> +
> + return flush_bits;
> }
>
> static
> diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
> index dd0c1a01d3..7b6ab4a9b7 100644
> --- a/src/amd/vulkan/radv_meta_clear.c
> +++ b/src/amd/vulkan/radv_meta_clear.c
> @@ -678,7 +678,7 @@ emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
> const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
> VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
> VkImageAspectFlags aspects = clear_att->aspectMask;
> - uint32_t clear_word;
> + uint32_t clear_word, flush_bits;
>
> if (!iview->image->surface.htile_size)
> return false;
> @@ -730,20 +730,17 @@ emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
> cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
> RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
>
> - radv_fill_buffer(cmd_buffer, iview->image->bo,
> - iview->image->offset + iview->image->htile_offset,
> - iview->image->surface.htile_size, clear_word);
> -
> + flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
> + iview->image->offset + iview->image->htile_offset,
> + iview->image->surface.htile_size, clear_word);
>
> radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
> - if (post_flush)
> - *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
> - RADV_CMD_FLAG_INV_VMEM_L1 |
> - RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
> - else
> - cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
> - RADV_CMD_FLAG_INV_VMEM_L1 |
> - RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
> + if (post_flush) {
> + *post_flush |= flush_bits;
> + } else {
> + cmd_buffer->state.flush_bits |= flush_bits;
> + }
> +
> return true;
> fail:
> return false;
> @@ -952,7 +949,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
> const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
> const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
> VkClearColorValue clear_value = clear_att->clearValue.color;
> - uint32_t clear_color[2];
> + uint32_t clear_color[2], flush_bits;
> bool ret;
>
> if (!iview->image->cmask.size && !iview->image->surface.dcc_size)
> @@ -1021,25 +1018,22 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
> &clear_value, &reset_value,
> &can_avoid_fast_clear_elim);
>
> - radv_fill_buffer(cmd_buffer, iview->image->bo,
> - iview->image->offset + iview->image->dcc_offset,
> - iview->image->surface.dcc_size, reset_value);
> + flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
> + iview->image->offset + iview->image->dcc_offset,
> + iview->image->surface.dcc_size, reset_value);
> radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
> !can_avoid_fast_clear_elim);
> } else {
> - radv_fill_buffer(cmd_buffer, iview->image->bo,
> - iview->image->offset + iview->image->cmask.offset,
> - iview->image->cmask.size, 0);
> + flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
> + iview->image->offset + iview->image->cmask.offset,
> + iview->image->cmask.size, 0);
> }
>
> - if (post_flush)
> - *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
> - RADV_CMD_FLAG_INV_VMEM_L1 |
> - RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
> - else
> - cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
> - RADV_CMD_FLAG_INV_VMEM_L1 |
> - RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
> + if (post_flush) {
> + *post_flush |= flush_bits;
> + } else {
> + cmd_buffer->state.flush_bits |= flush_bits;
> + }
>
> radv_set_color_clear_regs(cmd_buffer, iview->image, subpass_att, clear_color);
>
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index 18e057dffb..c19aa070d3 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -961,9 +961,9 @@ void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
> void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
> struct radv_image *image,
> bool value);
> -void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
> - struct radeon_winsys_bo *bo,
> - uint64_t offset, uint64_t size, uint32_t value);
> +uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
> + struct radeon_winsys_bo *bo,
> + uint64_t offset, uint64_t size, uint32_t value);
> void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
> bool radv_get_memory_fd(struct radv_device *device,
> struct radv_device_memory *memory,
> --
> 2.14.3
>
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