[Mesa-dev] [PATCH 3/4] amd/common: pass chip_class to ac_dump_reg
Nicolai Hähnle
nhaehnle at gmail.com
Mon Sep 4 12:11:06 UTC 2017
From: Nicolai Hähnle <nicolai.haehnle at amd.com>
---
src/amd/common/ac_debug.c | 86 ++++++++++++++++-----------------
src/amd/common/ac_debug.h | 4 +-
src/gallium/drivers/radeonsi/si_debug.c | 45 +++++++++++------
3 files changed, 75 insertions(+), 60 deletions(-)
diff --git a/src/amd/common/ac_debug.c b/src/amd/common/ac_debug.c
index 0de00e27e75..570ba850851 100644
--- a/src/amd/common/ac_debug.c
+++ b/src/amd/common/ac_debug.c
@@ -94,22 +94,22 @@ static void print_value(FILE *file, uint32_t value, int bits)
}
static void print_named_value(FILE *file, const char *name, uint32_t value,
int bits)
{
print_spaces(file, INDENT_PKT);
fprintf(file, COLOR_YELLOW "%s" COLOR_RESET " <- ", name);
print_value(file, value, bits);
}
-void ac_dump_reg(FILE *file, unsigned offset, uint32_t value,
- uint32_t field_mask)
+void ac_dump_reg(FILE *file, enum chip_class chip_class, unsigned offset,
+ uint32_t value, uint32_t field_mask)
{
int r, f;
for (r = 0; r < ARRAY_SIZE(sid_reg_table); r++) {
const struct si_reg *reg = &sid_reg_table[r];
const char *reg_name = sid_strings + reg->name_offset;
if (reg->offset == offset) {
bool first_field = true;
@@ -189,21 +189,21 @@ static void ac_parse_set_reg_packet(FILE *f, unsigned count, unsigned reg_offset
unsigned reg = ((reg_dw & 0xFFFF) << 2) + reg_offset;
unsigned index = reg_dw >> 28;
int i;
if (index != 0) {
print_spaces(f, INDENT_PKT);
fprintf(f, "INDEX = %u\n", index);
}
for (i = 0; i < count; i++)
- ac_dump_reg(f, reg + i*4, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, reg + i*4, ac_ib_get(ib), ~0);
}
static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
int *current_trace_id)
{
unsigned first_dw = ib->cur_dw;
int count = PKT_COUNT_G(header);
unsigned op = PKT3_IT_OPCODE_G(header);
const char *predicate = PKT3_PREDICATE(header) ? "(predicate)" : "";
int i;
@@ -237,74 +237,74 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
case PKT3_SET_CONFIG_REG:
ac_parse_set_reg_packet(f, count, SI_CONFIG_REG_OFFSET, ib);
break;
case PKT3_SET_UCONFIG_REG:
ac_parse_set_reg_packet(f, count, CIK_UCONFIG_REG_OFFSET, ib);
break;
case PKT3_SET_SH_REG:
ac_parse_set_reg_packet(f, count, SI_SH_REG_OFFSET, ib);
break;
case PKT3_ACQUIRE_MEM:
- ac_dump_reg(f, R_0301F0_CP_COHER_CNTL, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_0301F4_CP_COHER_SIZE, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_030230_CP_COHER_SIZE_HI, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_0301F8_CP_COHER_BASE, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_0301E4_CP_COHER_BASE_HI, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_0301F0_CP_COHER_CNTL, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_0301F4_CP_COHER_SIZE, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_030230_CP_COHER_SIZE_HI, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_0301F8_CP_COHER_BASE, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_0301E4_CP_COHER_BASE_HI, ac_ib_get(ib), ~0);
print_named_value(f, "POLL_INTERVAL", ac_ib_get(ib), 16);
break;
case PKT3_SURFACE_SYNC:
if (ib->chip_class >= CIK) {
- ac_dump_reg(f, R_0301F0_CP_COHER_CNTL, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_0301F4_CP_COHER_SIZE, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_0301F8_CP_COHER_BASE, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_0301F0_CP_COHER_CNTL, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_0301F4_CP_COHER_SIZE, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_0301F8_CP_COHER_BASE, ac_ib_get(ib), ~0);
} else {
- ac_dump_reg(f, R_0085F0_CP_COHER_CNTL, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_0085F4_CP_COHER_SIZE, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_0085F8_CP_COHER_BASE, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_0085F0_CP_COHER_CNTL, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_0085F4_CP_COHER_SIZE, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_0085F8_CP_COHER_BASE, ac_ib_get(ib), ~0);
}
print_named_value(f, "POLL_INTERVAL", ac_ib_get(ib), 16);
break;
case PKT3_EVENT_WRITE: {
uint32_t event_dw = ac_ib_get(ib);
- ac_dump_reg(f, R_028A90_VGT_EVENT_INITIATOR, event_dw,
+ ac_dump_reg(f, ib->chip_class, R_028A90_VGT_EVENT_INITIATOR, event_dw,
S_028A90_EVENT_TYPE(~0));
print_named_value(f, "EVENT_INDEX", (event_dw >> 8) & 0xf, 4);
print_named_value(f, "INV_L2", (event_dw >> 20) & 0x1, 1);
if (count > 0) {
print_named_value(f, "ADDRESS_LO", ac_ib_get(ib), 32);
print_named_value(f, "ADDRESS_HI", ac_ib_get(ib), 16);
}
break;
}
case PKT3_EVENT_WRITE_EOP: {
uint32_t event_dw = ac_ib_get(ib);
- ac_dump_reg(f, R_028A90_VGT_EVENT_INITIATOR, event_dw,
+ ac_dump_reg(f, ib->chip_class, R_028A90_VGT_EVENT_INITIATOR, event_dw,
S_028A90_EVENT_TYPE(~0));
print_named_value(f, "EVENT_INDEX", (event_dw >> 8) & 0xf, 4);
print_named_value(f, "TCL1_VOL_ACTION_ENA", (event_dw >> 12) & 0x1, 1);
print_named_value(f, "TC_VOL_ACTION_ENA", (event_dw >> 13) & 0x1, 1);
print_named_value(f, "TC_WB_ACTION_ENA", (event_dw >> 15) & 0x1, 1);
print_named_value(f, "TCL1_ACTION_ENA", (event_dw >> 16) & 0x1, 1);
print_named_value(f, "TC_ACTION_ENA", (event_dw >> 17) & 0x1, 1);
print_named_value(f, "ADDRESS_LO", ac_ib_get(ib), 32);
uint32_t addr_hi_dw = ac_ib_get(ib);
print_named_value(f, "ADDRESS_HI", addr_hi_dw, 16);
print_named_value(f, "DST_SEL", (addr_hi_dw >> 16) & 0x3, 2);
print_named_value(f, "INT_SEL", (addr_hi_dw >> 24) & 0x7, 3);
print_named_value(f, "DATA_SEL", addr_hi_dw >> 29, 3);
print_named_value(f, "DATA_LO", ac_ib_get(ib), 32);
print_named_value(f, "DATA_HI", ac_ib_get(ib), 32);
break;
}
case PKT3_RELEASE_MEM: {
uint32_t event_dw = ac_ib_get(ib);
- ac_dump_reg(f, R_028A90_VGT_EVENT_INITIATOR, event_dw,
+ ac_dump_reg(f, ib->chip_class, R_028A90_VGT_EVENT_INITIATOR, event_dw,
S_028A90_EVENT_TYPE(~0));
print_named_value(f, "EVENT_INDEX", (event_dw >> 8) & 0xf, 4);
print_named_value(f, "TCL1_VOL_ACTION_ENA", (event_dw >> 12) & 0x1, 1);
print_named_value(f, "TC_VOL_ACTION_ENA", (event_dw >> 13) & 0x1, 1);
print_named_value(f, "TC_WB_ACTION_ENA", (event_dw >> 15) & 0x1, 1);
print_named_value(f, "TCL1_ACTION_ENA", (event_dw >> 16) & 0x1, 1);
print_named_value(f, "TC_ACTION_ENA", (event_dw >> 17) & 0x1, 1);
print_named_value(f, "TC_NC_ACTION_ENA", (event_dw >> 19) & 0x1, 1);
print_named_value(f, "TC_WC_ACTION_ENA", (event_dw >> 20) & 0x1, 1);
print_named_value(f, "TC_MD_ACTION_ENA", (event_dw >> 21) & 0x1, 1);
@@ -321,66 +321,66 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
}
case PKT3_WAIT_REG_MEM:
print_named_value(f, "OP", ac_ib_get(ib), 32);
print_named_value(f, "ADDRESS_LO", ac_ib_get(ib), 32);
print_named_value(f, "ADDRESS_HI", ac_ib_get(ib), 32);
print_named_value(f, "REF", ac_ib_get(ib), 32);
print_named_value(f, "MASK", ac_ib_get(ib), 32);
print_named_value(f, "POLL_INTERVAL", ac_ib_get(ib), 16);
break;
case PKT3_DRAW_INDEX_AUTO:
- ac_dump_reg(f, R_030930_VGT_NUM_INDICES, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_0287F0_VGT_DRAW_INITIATOR, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_030930_VGT_NUM_INDICES, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_0287F0_VGT_DRAW_INITIATOR, ac_ib_get(ib), ~0);
break;
case PKT3_DRAW_INDEX_2:
- ac_dump_reg(f, R_028A78_VGT_DMA_MAX_SIZE, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_0287E8_VGT_DMA_BASE, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_0287E4_VGT_DMA_BASE_HI, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_030930_VGT_NUM_INDICES, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_0287F0_VGT_DRAW_INITIATOR, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_028A78_VGT_DMA_MAX_SIZE, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_0287E8_VGT_DMA_BASE, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_0287E4_VGT_DMA_BASE_HI, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_030930_VGT_NUM_INDICES, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_0287F0_VGT_DRAW_INITIATOR, ac_ib_get(ib), ~0);
break;
case PKT3_INDEX_TYPE:
- ac_dump_reg(f, R_028A7C_VGT_DMA_INDEX_TYPE, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_028A7C_VGT_DMA_INDEX_TYPE, ac_ib_get(ib), ~0);
break;
case PKT3_NUM_INSTANCES:
- ac_dump_reg(f, R_030934_VGT_NUM_INSTANCES, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_030934_VGT_NUM_INSTANCES, ac_ib_get(ib), ~0);
break;
case PKT3_WRITE_DATA:
- ac_dump_reg(f, R_370_CONTROL, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_371_DST_ADDR_LO, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_372_DST_ADDR_HI, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_370_CONTROL, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_371_DST_ADDR_LO, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_372_DST_ADDR_HI, ac_ib_get(ib), ~0);
/* The payload is written automatically */
break;
case PKT3_CP_DMA:
- ac_dump_reg(f, R_410_CP_DMA_WORD0, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_411_CP_DMA_WORD1, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_412_CP_DMA_WORD2, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_413_CP_DMA_WORD3, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_414_COMMAND, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_410_CP_DMA_WORD0, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_411_CP_DMA_WORD1, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_412_CP_DMA_WORD2, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_413_CP_DMA_WORD3, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_414_COMMAND, ac_ib_get(ib), ~0);
break;
case PKT3_DMA_DATA:
- ac_dump_reg(f, R_500_DMA_DATA_WORD0, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_501_SRC_ADDR_LO, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_502_SRC_ADDR_HI, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_503_DST_ADDR_LO, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_504_DST_ADDR_HI, ac_ib_get(ib), ~0);
- ac_dump_reg(f, R_414_COMMAND, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_500_DMA_DATA_WORD0, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_501_SRC_ADDR_LO, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_502_SRC_ADDR_HI, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_503_DST_ADDR_LO, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_504_DST_ADDR_HI, ac_ib_get(ib), ~0);
+ ac_dump_reg(f, ib->chip_class, R_414_COMMAND, ac_ib_get(ib), ~0);
break;
case PKT3_INDIRECT_BUFFER_SI:
case PKT3_INDIRECT_BUFFER_CONST:
case PKT3_INDIRECT_BUFFER_CIK: {
uint32_t base_lo_dw = ac_ib_get(ib);
- ac_dump_reg(f, R_3F0_IB_BASE_LO, base_lo_dw, ~0);
+ ac_dump_reg(f, ib->chip_class, R_3F0_IB_BASE_LO, base_lo_dw, ~0);
uint32_t base_hi_dw = ac_ib_get(ib);
- ac_dump_reg(f, R_3F1_IB_BASE_HI, base_hi_dw, ~0);
+ ac_dump_reg(f, ib->chip_class, R_3F1_IB_BASE_HI, base_hi_dw, ~0);
uint32_t control_dw = ac_ib_get(ib);
- ac_dump_reg(f, R_3F2_CONTROL, control_dw, ~0);
+ ac_dump_reg(f, ib->chip_class, R_3F2_CONTROL, control_dw, ~0);
if (!ib->addr_callback)
break;
uint64_t addr = ((uint64_t)base_hi_dw << 32) | base_lo_dw;
void *data = ib->addr_callback(ib->addr_callback_data, addr);
if (!data)
break;
if (G_3F2_CHAIN(control_dw)) {
diff --git a/src/amd/common/ac_debug.h b/src/amd/common/ac_debug.h
index 277025d8b66..35e950014b0 100644
--- a/src/amd/common/ac_debug.h
+++ b/src/amd/common/ac_debug.h
@@ -31,22 +31,22 @@
#include <stdbool.h>
#include "amd_family.h"
#define AC_ENCODE_TRACE_POINT(id) (0xcafe0000 | ((id) & 0xffff))
#define AC_IS_TRACE_POINT(x) (((x) & 0xcafe0000) == 0xcafe0000)
#define AC_GET_TRACE_POINT_ID(x) ((x) & 0xffff)
typedef void *(*ac_debug_addr_callback)(void *data, uint64_t addr);
-void ac_dump_reg(FILE *file, unsigned offset, uint32_t value,
- uint32_t field_mask);
+void ac_dump_reg(FILE *file, enum chip_class chip_class, unsigned offset,
+ uint32_t value, uint32_t field_mask);
void ac_parse_ib_chunk(FILE *f, uint32_t *ib, int num_dw, const int *trace_ids,
unsigned trace_id_count, enum chip_class chip_class,
ac_debug_addr_callback addr_callback, void *addr_callback_data);
void ac_parse_ib(FILE *f, uint32_t *ib, int num_dw, const int *trace_ids,
unsigned trace_id_count, const char *name, enum chip_class chip_class,
ac_debug_addr_callback addr_callback, void *addr_callback_data);
bool ac_vm_fault_occured(enum chip_class chip_class,
uint64_t *old_dmesg_timestamp, uint64_t *out_addr);
diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c
index 28c777d105b..182574d653b 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -224,21 +224,21 @@ file_error:
#define COLOR_YELLOW "\033[1;33m"
#define COLOR_CYAN "\033[1;36m"
static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f,
unsigned offset)
{
struct radeon_winsys *ws = sctx->b.ws;
uint32_t value;
if (ws->read_registers(ws, offset, 1, &value))
- ac_dump_reg(f, offset, value, ~0);
+ ac_dump_reg(f, sctx->b.chip_class, offset, value, ~0);
}
static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
{
if (sctx->screen->b.info.drm_major == 2 &&
sctx->screen->b.info.drm_minor < 42)
return; /* no radeon support */
fprintf(f, "Memory-mapped registers:\n");
si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
@@ -557,20 +557,21 @@ typedef unsigned (*slot_remap_func)(unsigned);
struct si_log_chunk_desc_list {
/** Pointer to memory map of buffer where the list is uploader */
uint32_t *gpu_list;
/** Reference of buffer where the list is uploaded, so that gpu_list
* is kept live. */
struct r600_resource *buf;
const char *shader_name;
const char *elem_name;
slot_remap_func slot_remap;
+ enum chip_class chip_class;
unsigned element_dw_size;
unsigned num_elements;
uint32_t list[0];
};
static void
si_log_chunk_desc_list_destroy(void *data)
{
struct si_log_chunk_desc_list *chunk = data;
@@ -589,89 +590,98 @@ si_log_chunk_desc_list_print(void *data, FILE *f)
const char *list_note = chunk->gpu_list ? "GPU list" : "CPU list";
uint32_t *cpu_list = chunk->list + cpu_dw_offset;
uint32_t *gpu_list = chunk->gpu_list ? chunk->gpu_list + gpu_dw_offset : cpu_list;
fprintf(f, COLOR_GREEN "%s%s slot %u (%s):" COLOR_RESET "\n",
chunk->shader_name, chunk->elem_name, i, list_note);
switch (chunk->element_dw_size) {
case 4:
for (unsigned j = 0; j < 4; j++)
- ac_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
+ ac_dump_reg(f, chunk->chip_class,
+ R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
gpu_list[j], 0xffffffff);
break;
case 8:
for (unsigned j = 0; j < 8; j++)
- ac_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
+ ac_dump_reg(f, chunk->chip_class,
+ R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
gpu_list[j], 0xffffffff);
fprintf(f, COLOR_CYAN " Buffer:" COLOR_RESET "\n");
for (unsigned j = 0; j < 4; j++)
- ac_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
+ ac_dump_reg(f, chunk->chip_class,
+ R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
gpu_list[4+j], 0xffffffff);
break;
case 16:
for (unsigned j = 0; j < 8; j++)
- ac_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
+ ac_dump_reg(f, chunk->chip_class,
+ R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
gpu_list[j], 0xffffffff);
fprintf(f, COLOR_CYAN " Buffer:" COLOR_RESET "\n");
for (unsigned j = 0; j < 4; j++)
- ac_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
+ ac_dump_reg(f, chunk->chip_class,
+ R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
gpu_list[4+j], 0xffffffff);
fprintf(f, COLOR_CYAN " FMASK:" COLOR_RESET "\n");
for (unsigned j = 0; j < 8; j++)
- ac_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
+ ac_dump_reg(f, chunk->chip_class,
+ R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
gpu_list[8+j], 0xffffffff);
fprintf(f, COLOR_CYAN " Sampler state:" COLOR_RESET "\n");
for (unsigned j = 0; j < 4; j++)
- ac_dump_reg(f, R_008F30_SQ_IMG_SAMP_WORD0 + j*4,
+ ac_dump_reg(f, chunk->chip_class,
+ R_008F30_SQ_IMG_SAMP_WORD0 + j*4,
gpu_list[12+j], 0xffffffff);
break;
}
if (memcmp(gpu_list, cpu_list, chunk->element_dw_size * 4) != 0) {
fprintf(f, COLOR_RED "!!!!! This slot was corrupted in GPU memory !!!!!"
COLOR_RESET "\n");
}
fprintf(f, "\n");
}
}
static const struct u_log_chunk_type si_log_chunk_type_descriptor_list = {
.destroy = si_log_chunk_desc_list_destroy,
.print = si_log_chunk_desc_list_print,
};
-static void si_dump_descriptor_list(struct si_descriptors *desc,
+static void si_dump_descriptor_list(struct si_screen *screen,
+ struct si_descriptors *desc,
const char *shader_name,
const char *elem_name,
unsigned element_dw_size,
unsigned num_elements,
slot_remap_func slot_remap,
struct u_log_context *log)
{
if (!desc->list)
return;
struct si_log_chunk_desc_list *chunk =
CALLOC_VARIANT_LENGTH_STRUCT(si_log_chunk_desc_list,
4 * element_dw_size * num_elements);
chunk->shader_name = shader_name;
chunk->elem_name = elem_name;
chunk->element_dw_size = element_dw_size;
chunk->num_elements = num_elements;
chunk->slot_remap = slot_remap;
+ chunk->chip_class = screen->b.chip_class;
r600_resource_reference(&chunk->buf, desc->buffer);
chunk->gpu_list = desc->gpu_list;
for (unsigned i = 0; i < num_elements; ++i) {
memcpy(&chunk->list[i * element_dw_size],
&desc->list[slot_remap(i) * element_dw_size],
4 * element_dw_size);
}
@@ -708,38 +718,42 @@ static void si_dump_descriptors(struct si_context *sctx,
u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
enabled_shaderbuf = util_bitreverse(enabled_shaderbuf) >>
(32 - SI_NUM_SHADER_BUFFERS);
enabled_samplers = sctx->samplers[processor].views.enabled_mask;
enabled_images = sctx->images[processor].enabled_mask;
}
if (processor == PIPE_SHADER_VERTEX) {
assert(info); /* only CS may not have an info struct */
- si_dump_descriptor_list(&sctx->vertex_buffers, name,
+ si_dump_descriptor_list(sctx->screen, &sctx->vertex_buffers, name,
" - Vertex buffer", 4, info->num_inputs,
si_identity, log);
}
- si_dump_descriptor_list(&descs[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS],
+ si_dump_descriptor_list(sctx->screen,
+ &descs[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS],
name, " - Constant buffer", 4,
util_last_bit(enabled_constbuf),
si_get_constbuf_slot, log);
- si_dump_descriptor_list(&descs[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS],
+ si_dump_descriptor_list(sctx->screen,
+ &descs[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS],
name, " - Shader buffer", 4,
util_last_bit(enabled_shaderbuf),
si_get_shaderbuf_slot, log);
- si_dump_descriptor_list(&descs[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES],
+ si_dump_descriptor_list(sctx->screen,
+ &descs[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES],
name, " - Sampler", 16,
util_last_bit(enabled_samplers),
si_get_sampler_slot, log);
- si_dump_descriptor_list(&descs[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES],
+ si_dump_descriptor_list(sctx->screen,
+ &descs[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES],
name, " - Image", 8,
util_last_bit(enabled_images),
si_get_image_slot, log);
}
static void si_dump_gfx_descriptors(struct si_context *sctx,
const struct si_shader_ctx_state *state,
struct u_log_context *log)
{
if (!state->cso || !state->current)
@@ -1051,21 +1065,22 @@ void si_log_draw_state(struct si_context *sctx, struct u_log_context *log)
return;
si_dump_framebuffer(sctx, log);
si_dump_gfx_shader(sctx, &sctx->vs_shader, log);
si_dump_gfx_shader(sctx, &sctx->tcs_shader, log);
si_dump_gfx_shader(sctx, &sctx->tes_shader, log);
si_dump_gfx_shader(sctx, &sctx->gs_shader, log);
si_dump_gfx_shader(sctx, &sctx->ps_shader, log);
- si_dump_descriptor_list(&sctx->descriptors[SI_DESCS_RW_BUFFERS],
+ si_dump_descriptor_list(sctx->screen,
+ &sctx->descriptors[SI_DESCS_RW_BUFFERS],
"", "RW buffers", 4, SI_NUM_RW_BUFFERS,
si_identity, log);
si_dump_gfx_descriptors(sctx, &sctx->vs_shader, log);
si_dump_gfx_descriptors(sctx, &sctx->tcs_shader, log);
si_dump_gfx_descriptors(sctx, &sctx->tes_shader, log);
si_dump_gfx_descriptors(sctx, &sctx->gs_shader, log);
si_dump_gfx_descriptors(sctx, &sctx->ps_shader, log);
}
void si_log_compute_state(struct si_context *sctx, struct u_log_context *log)
--
2.11.0
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