[Mesa-dev] [PATCH 4/9] radeonsi: don't always apply the PrimID instancing bug workaround on SI

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

It looks like commit 391673af7ad1565a5f6ac8fc2f8c9fcdd1fe9908 that should
have fixed the perf regression didn't really change much if anything.
---
 src/gallium/drivers/radeonsi/si_state_draw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 051dfea..363a4ae 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -206,21 +206,21 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
 	/* The VGT HS block increments the patch ID unconditionally
 	 * within a single threadgroup. This results in incorrect
 	 * patch IDs when instanced draws are used.
 	 *
 	 * The intended solution is to restrict threadgroups to
 	 * a single instance by setting SWITCH_ON_EOI, which
 	 * should cause IA to split instances up. However, this
 	 * doesn't work correctly on SI when there is no other
 	 * SE to switch to.
 	 */
-	if (has_primid_instancing_bug)
+	if (has_primid_instancing_bug && tess_uses_primid)
 		*num_patches = 1;
 
 	sctx->last_num_patches = *num_patches;
 
 	output_patch0_offset = input_patch_size * *num_patches;
 	perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
 
 	/* Compute userdata SGPRs. */
 	assert(((input_vertex_size / 4) & ~0xff) == 0);
 	assert(((output_vertex_size / 4) & ~0xff) == 0);
-- 
2.7.4