[Mesa-dev] [PATCH] ac/surface: add radeon_surf::has_stencil for convenience
Nicolai Hähnle
nhaehnle at gmail.com
Thu Sep 7 15:23:33 UTC 2017
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
On 07.09.2017 16:42, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> ---
> src/amd/common/ac_surface.c | 2 ++
> src/amd/common/ac_surface.h | 1 +
> src/amd/vulkan/radv_device.c | 6 +++---
> src/gallium/drivers/r600/evergreen_state.c | 2 +-
> src/gallium/drivers/r600/r600_blit.c | 2 +-
> src/gallium/drivers/r600/r600_state_common.c | 2 +-
> src/gallium/drivers/radeon/r600_texture.c | 4 ++--
> src/gallium/drivers/radeonsi/si_blit.c | 2 +-
> src/gallium/drivers/radeonsi/si_state.c | 8 ++++----
> src/gallium/drivers/radeonsi/si_state_binning.c | 2 +-
> src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 1 +
> 11 files changed, 18 insertions(+), 14 deletions(-)
>
> diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
> index 4edefc7..c6ff573 100644
> --- a/src/amd/common/ac_surface.c
> +++ b/src/amd/common/ac_surface.c
> @@ -648,20 +648,21 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
> if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
> AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
> else
> AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
>
> /* Addrlib doesn't set this if tileIndex is forced like above. */
> AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
> }
> }
>
> + surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
> surf->num_dcc_levels = 0;
> surf->surf_size = 0;
> surf->dcc_size = 0;
> surf->dcc_alignment = 1;
> surf->htile_size = 0;
> surf->htile_slice_size = 0;
> surf->htile_alignment = 1;
>
> const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
> !(surf->flags & RADEON_SURF_ZBUFFER);
> @@ -1070,20 +1071,21 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
> &AddrSurfInfoIn.swizzleMode);
> if (r)
> return r;
> break;
>
> default:
> assert(0);
> }
>
> surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
> + surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
>
> surf->num_dcc_levels = 0;
> surf->surf_size = 0;
> surf->dcc_size = 0;
> surf->htile_size = 0;
> surf->htile_slice_size = 0;
> surf->u.gfx9.surf_offset = 0;
> surf->u.gfx9.stencil_offset = 0;
> surf->u.gfx9.fmask_size = 0;
> surf->u.gfx9.cmask_size = 0;
> diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
> index 3b99386..96138b9 100644
> --- a/src/amd/common/ac_surface.h
> +++ b/src/amd/common/ac_surface.h
> @@ -153,20 +153,21 @@ struct radeon_surf {
> /* Format properties. */
> unsigned blk_w:4;
> unsigned blk_h:4;
> unsigned bpe:5;
> /* Number of mipmap levels where DCC is enabled starting from level 0.
> * Non-zero levels may be disabled due to alignment constraints, but not
> * the first level.
> */
> unsigned num_dcc_levels:4;
> unsigned is_linear:1;
> + unsigned has_stencil:1;
> /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
> unsigned micro_tile_mode:3;
> uint32_t flags;
>
> /* These are return values. Some of them can be set by the caller, but
> * they will be treated as hints (e.g. bankw, bankh) and might be
> * changed by the calculator.
> */
>
> /* Tile swizzle can be OR'd with low bits of the BASE_256B address.
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index 7c218b1..b64a023 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -3134,21 +3134,21 @@ radv_initialise_ds_surface(struct radv_device *device,
> ds->offset_scale = 1.0f;
> break;
> case VK_FORMAT_S8_UINT:
> stencil_only = true;
> break;
> default:
> break;
> }
>
> format = radv_translate_dbformat(iview->image->vk_format);
> - stencil_format = iview->image->surface.flags & RADEON_SURF_SBUFFER ?
> + stencil_format = iview->image->surface.has_stencil ?
> V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
>
> uint32_t max_slice = radv_surface_layer_count(iview);
> ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
> S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
>
> ds->db_htile_data_base = 0;
> ds->db_htile_surface = 0;
>
> va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
> @@ -3169,21 +3169,21 @@ radv_initialise_ds_surface(struct radv_device *device,
> ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
> ds->db_depth_view |= S_028008_MIPID(level);
>
> ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
> S_02801C_Y_MAX(iview->image->info.height - 1);
>
> /* Only use HTILE for the first level. */
> if (iview->image->surface.htile_size && !level) {
> ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
>
> - if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
> + if (!iview->image->surface.has_stencil)
> /* Use all of the htile_buffer for depth if there's no stencil. */
> ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
> va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
> iview->image->htile_offset;
> ds->db_htile_data_base = va >> 8;
> ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
> S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
> S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
> }
> } else {
> @@ -3232,21 +3232,21 @@ radv_initialise_ds_surface(struct radv_device *device,
> ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
> }
>
> ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
> S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
> ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
>
> if (iview->image->surface.htile_size && !level) {
> ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
>
> - if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
> + if (!iview->image->surface.has_stencil)
> /* Use all of the htile_buffer for depth if there's no stencil. */
> ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
>
> va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
> iview->image->htile_offset;
> ds->db_htile_data_base = va >> 8;
> ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
> }
> }
>
> diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
> index a9b503f..5e9c77d 100644
> --- a/src/gallium/drivers/r600/evergreen_state.c
> +++ b/src/gallium/drivers/r600/evergreen_state.c
> @@ -1364,21 +1364,21 @@ static void evergreen_init_depth_surface(struct r600_context *rctx,
> assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
>
> surf->db_depth_base = offset;
> surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
> S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
> surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
> S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
> surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
> levelinfo->nblk_y / 64 - 1);
>
> - if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
> + if (rtex->surface.has_stencil) {
> uint64_t stencil_offset;
> unsigned stile_split = rtex->surface.u.legacy.stencil_tile_split;
>
> stile_split = eg_tile_split(stile_split);
>
> stencil_offset = rtex->surface.u.legacy.stencil_level[level].offset;
> stencil_offset += rtex->resource.gpu_address;
>
> surf->db_stencil_base = stencil_offset >> 8;
> surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
> diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
> index 783d8c8..64f06e8 100644
> --- a/src/gallium/drivers/r600/r600_blit.c
> +++ b/src/gallium/drivers/r600/r600_blit.c
> @@ -370,21 +370,21 @@ static bool r600_decompress_subresource(struct pipe_context *ctx,
> unsigned first_layer, unsigned last_layer)
> {
> struct r600_context *rctx = (struct r600_context *)ctx;
> struct r600_texture *rtex = (struct r600_texture*)tex;
>
> if (rtex->db_compatible) {
> if (r600_can_sample_zs(rtex, false)) {
> r600_blit_decompress_depth_in_place(rctx, rtex, false,
> level, level,
> first_layer, last_layer);
> - if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
> + if (rtex->surface.has_stencil) {
> r600_blit_decompress_depth_in_place(rctx, rtex, true,
> level, level,
> first_layer, last_layer);
> }
> } else {
> if (!r600_init_flushed_depth_texture(ctx, tex, NULL))
> return false; /* error */
>
> r600_blit_decompress_depth(ctx, rtex, NULL,
> level, level,
> diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
> index 4c97efa..c1bce83 100644
> --- a/src/gallium/drivers/r600/r600_state_common.c
> +++ b/src/gallium/drivers/r600/r600_state_common.c
> @@ -2023,21 +2023,21 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
> eg_trace_emit(rctx);
>
> if (rctx->framebuffer.do_update_surf_dirtiness) {
> /* Set the depth buffer as dirty. */
> if (rctx->framebuffer.state.zsbuf) {
> struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
> struct r600_texture *rtex = (struct r600_texture *)surf->texture;
>
> rtex->dirty_level_mask |= 1 << surf->u.tex.level;
>
> - if (rtex->surface.flags & RADEON_SURF_SBUFFER)
> + if (rtex->surface.has_stencil)
> rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
> }
> if (rctx->framebuffer.compressed_cb_mask) {
> struct pipe_surface *surf;
> struct r600_texture *rtex;
> unsigned mask = rctx->framebuffer.compressed_cb_mask;
>
> do {
> unsigned i = u_bit_scan(&mask);
> surf = rctx->framebuffer.state.cbufs[i];
> diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
> index 47fd56f..26afc98 100644
> --- a/src/gallium/drivers/radeon/r600_texture.c
> +++ b/src/gallium/drivers/radeon/r600_texture.c
> @@ -1161,21 +1161,21 @@ void r600_print_texture_info(struct r600_common_screen *rscreen,
> i, rtex->surface.u.legacy.level[i].offset,
> rtex->surface.u.legacy.level[i].slice_size,
> u_minify(rtex->resource.b.b.width0, i),
> u_minify(rtex->resource.b.b.height0, i),
> u_minify(rtex->resource.b.b.depth0, i),
> rtex->surface.u.legacy.level[i].nblk_x,
> rtex->surface.u.legacy.level[i].nblk_y,
> rtex->surface.u.legacy.level[i].mode,
> rtex->surface.u.legacy.tiling_index[i]);
>
> - if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
> + if (rtex->surface.has_stencil) {
> u_log_printf(log, " StencilLayout: tilesplit=%u\n",
> rtex->surface.u.legacy.stencil_tile_split);
> for (i = 0; i <= rtex->resource.b.b.last_level; i++) {
> u_log_printf(log, " StencilLevel[%i]: offset=%"PRIu64", "
> "slice_size=%"PRIu64", npix_x=%u, "
> "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
> "mode=%u, tiling_index = %u\n",
> i, rtex->surface.u.legacy.stencil_level[i].offset,
> rtex->surface.u.legacy.stencil_level[i].slice_size,
> u_minify(rtex->resource.b.b.width0, i),
> @@ -2113,21 +2113,21 @@ static void r600_clear_texture(struct pipe_context *pipe,
>
> if (rtex->is_depth) {
> unsigned clear;
> float depth;
> uint8_t stencil = 0;
>
> /* Depth is always present. */
> clear = PIPE_CLEAR_DEPTH;
> desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
>
> - if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
> + if (rtex->surface.has_stencil) {
> clear |= PIPE_CLEAR_STENCIL;
> desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
> }
>
> pipe->clear_depth_stencil(pipe, sf, clear, depth, stencil,
> box->x, box->y,
> box->width, box->height, false);
> } else {
> union pipe_color_union color;
>
> diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
> index 2f94f47..0ecfc83 100644
> --- a/src/gallium/drivers/radeonsi/si_blit.c
> +++ b/src/gallium/drivers/radeonsi/si_blit.c
> @@ -966,21 +966,21 @@ static void si_decompress_subresource(struct pipe_context *ctx,
> struct pipe_resource *tex,
> unsigned planes, unsigned level,
> unsigned first_layer, unsigned last_layer)
> {
> struct si_context *sctx = (struct si_context *)ctx;
> struct r600_texture *rtex = (struct r600_texture*)tex;
>
> if (rtex->db_compatible) {
> planes &= PIPE_MASK_Z | PIPE_MASK_S;
>
> - if (!(rtex->surface.flags & RADEON_SURF_SBUFFER))
> + if (!rtex->surface.has_stencil)
> planes &= ~PIPE_MASK_S;
>
> /* If we've rendered into the framebuffer and it's a blitting
> * source, make sure the decompression pass is invoked
> * by dirtying the framebuffer.
> */
> if (sctx->framebuffer.state.zsbuf &&
> sctx->framebuffer.state.zsbuf->u.tex.level == level &&
> sctx->framebuffer.state.zsbuf->texture == tex)
> si_update_fb_dirtiness_after_rendering(sctx);
> diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
> index 7e9140b..ee07010 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -2320,21 +2320,21 @@ static void si_initialize_color_surface(struct si_context *sctx,
>
> static void si_init_depth_surface(struct si_context *sctx,
> struct r600_surface *surf)
> {
> struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
> unsigned level = surf->base.u.tex.level;
> unsigned format, stencil_format;
> uint32_t z_info, s_info;
>
> format = si_translate_dbformat(rtex->db_render_format);
> - stencil_format = rtex->surface.flags & RADEON_SURF_SBUFFER ?
> + stencil_format = rtex->surface.has_stencil ?
> V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
>
> assert(format != V_028040_Z_INVALID);
> if (format == V_028040_Z_INVALID)
> R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
>
> surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
> S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
> surf->db_htile_data_base = 0;
> surf->db_htile_surface = 0;
> @@ -2365,21 +2365,21 @@ static void si_init_depth_surface(struct si_context *sctx,
>
> if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
> rtex->resource.b.b.nr_samples > 1)
> max_zplanes = 2;
>
> z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
> S_028038_ITERATE_FLUSH(1);
> s_info |= S_02803C_ITERATE_FLUSH(1);
> }
>
> - if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
> + if (rtex->surface.has_stencil) {
> /* Stencil buffer workaround ported from the SI-CI-VI code.
> * See that for explanation.
> */
> s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
> } else {
> /* Use all HTILE for depth if there's no stencil. */
> s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
> }
>
> surf->db_htile_data_base = (rtex->resource.gpu_address +
> @@ -2431,21 +2431,21 @@ static void si_init_depth_surface(struct si_context *sctx,
>
> surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
> S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
> surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
> levelinfo->nblk_y) / 64 - 1);
>
> if (r600_htile_enabled(rtex, level)) {
> z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
> S_028040_ALLOW_EXPCLEAR(1);
>
> - if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
> + if (rtex->surface.has_stencil) {
> /* Workaround: For a not yet understood reason, the
> * combination of MSAA, fast stencil clear and stencil
> * decompress messes with subsequent stencil buffer
> * uses. Problem was reproduced on Verde, Bonaire,
> * Tonga, and Carrizo.
> *
> * Disabling EXPCLEAR works around the problem.
> *
> * Check piglit's arb_texture_multisample-stencil-clear
> * test if you want to try changing this.
> @@ -2487,21 +2487,21 @@ void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
> {
> if (sctx->decompression_enabled)
> return;
>
> if (sctx->framebuffer.state.zsbuf) {
> struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
> struct r600_texture *rtex = (struct r600_texture *)surf->texture;
>
> rtex->dirty_level_mask |= 1 << surf->u.tex.level;
>
> - if (rtex->surface.flags & RADEON_SURF_SBUFFER)
> + if (rtex->surface.has_stencil)
> rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
> }
> if (sctx->framebuffer.compressed_cb_mask) {
> struct pipe_surface *surf;
> struct r600_texture *rtex;
> unsigned mask = sctx->framebuffer.compressed_cb_mask;
>
> do {
> unsigned i = u_bit_scan(&mask);
> surf = sctx->framebuffer.state.cbufs[i];
> diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c
> index d75e86e..8d98d6d 100644
> --- a/src/gallium/drivers/radeonsi/si_state_binning.c
> +++ b/src/gallium/drivers/radeonsi/si_state_binning.c
> @@ -196,21 +196,21 @@ static struct uvec2 si_get_depth_bin_size(struct si_context *sctx)
> if (!sctx->framebuffer.state.zsbuf ||
> (!dsa->depth_enabled && !dsa->stencil_enabled)) {
> /* Return the max size. */
> struct uvec2 size = {512, 512};
> return size;
> }
>
> struct r600_texture *rtex =
> (struct r600_texture*)sctx->framebuffer.state.zsbuf->texture;
> unsigned depth_coeff = dsa->depth_enabled ? 5 : 0;
> - unsigned stencil_coeff = rtex->surface.flags & RADEON_SURF_SBUFFER &&
> + unsigned stencil_coeff = rtex->surface.has_stencil &&
> dsa->stencil_enabled ? 1 : 0;
> unsigned sum = 4 * (depth_coeff + stencil_coeff) *
> sctx->framebuffer.nr_samples;
>
> static const si_bin_size_subtable table[] = {
> {
> // One RB / SE
> {
> // One shader engine
> { 0, 128, 256 },
> diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
> index 39d648f..6cda59e 100644
> --- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
> +++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
> @@ -180,20 +180,21 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
> const struct radeon_surface *surf_drm)
> {
> int i;
>
> memset(surf_ws, 0, sizeof(*surf_ws));
>
> surf_ws->blk_w = surf_drm->blk_w;
> surf_ws->blk_h = surf_drm->blk_h;
> surf_ws->bpe = surf_drm->bpe;
> surf_ws->is_linear = surf_drm->level[0].mode <= RADEON_SURF_MODE_LINEAR_ALIGNED;
> + surf_ws->has_stencil = !!(surf_drm->flags & RADEON_SURF_SBUFFER);
> surf_ws->flags = surf_drm->flags;
>
> surf_ws->surf_size = surf_drm->bo_size;
> surf_ws->surf_alignment = surf_drm->bo_alignment;
>
> surf_ws->u.legacy.bankw = surf_drm->bankw;
> surf_ws->u.legacy.bankh = surf_drm->bankh;
> surf_ws->u.legacy.mtilea = surf_drm->mtilea;
> surf_ws->u.legacy.tile_split = surf_drm->tile_split;
>
>
--
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.
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