[Mesa-dev] [PATCH] i965: do not fallback to linear tiling for depth/stencil surfaces

[Iago Toral Quiroga]

It is not supported by the hardware and the driver assumes
W-tiling for stencil and Y-tiling for depth everywhere anyway.

This fixes a regression in a CTS test introduced with commit
4ea63fab77f0 that started applying re-tiling for these surfaces
in certain scenarios.

Fixes:
KHR-GL45.direct_state_access.renderbuffers_storage
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 79afdc5342..cfc1212353 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -572,9 +572,13 @@ make_surface(struct brw_context *brw, GLenum target, mesa_format format,
 
    /* In case caller doesn't specifically request Y-tiling (needed
     * unconditionally for depth), check for corner cases needing special
-    * treatment.
+    * treatment. Stencil and depth surfaces are always W  and Y tiled
+    * respectively, so we should not attempt to retile them to different
+    * layouts.
     */
-   if (tiling_flags & ~ISL_TILING_Y0_BIT) {
+   bool is_depth_stencil = mt->surf.usage &
+      (ISL_SURF_USAGE_STENCIL_BIT | ISL_SURF_USAGE_DEPTH_BIT);
+   if (!is_depth_stencil && (tiling_flags & ~ISL_TILING_Y0_BIT)) {
       if (need_to_retile_as_linear(brw, mt->surf.row_pitch,
                                    mt->surf.tiling, mt->surf.samples)) {
          init_info.tiling_flags = 1u << ISL_TILING_LINEAR;
-- 
2.11.0