[Mesa-dev] [PATCH] radeonsi/uvd: fix interlaced video buffer height alignment

[Leo Liu]

In code:
	template.height = align(tmpl->height / array_size, VL_MACROBLOCK_HEIGHT);
	...
	template.height *= array_size;

It turns out the height will be aligned with 2*VL_MACROBLOCK_HEIGHT.
The problematic case for example is when VA-API postproc scaling with
blit between interlaced buffers, if the size is 720 in height, it will
be actually scaled to 736 in height, so the scaled video will crop out
the extra 16 lines of height.

Another example is when deint with 720p video from interlaced buffer
to progressive buffer. This problem happened on OMX, and got workaround
with patch:

(0c374a777 st/omx/dec: set dst rect to match src size

When creating interlaced video buffer, hegith set to "template.height =
align(tmpl->height/ array_size, VL_MACROBLOCK_HEIGHT);", and we use
"template.height *= array_size;" for the buffer height, so it actually
aligned with 32. With progressive video buffer it still aligned with 16,
thus causing different height between interlaced buffer and progressive
buffer for 4K (height=2160), and 720p (height=720).

When transcode the video, this will cause the 16 lines corruption
at the bottom of the encode video.)

Signed-off-by: Leo Liu <leo.liu at amd.com>
---
 src/gallium/drivers/radeonsi/si_uvd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_uvd.c b/src/gallium/drivers/radeonsi/si_uvd.c
index 2441ad248c..e4c55c20e1 100644
--- a/src/gallium/drivers/radeonsi/si_uvd.c
+++ b/src/gallium/drivers/radeonsi/si_uvd.c
@@ -62,7 +62,7 @@ struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 	array_size = tmpl->interlaced ? 2 : 1;
 	template = *tmpl;
 	template.width = align(tmpl->width, VL_MACROBLOCK_WIDTH);
-	template.height = align(tmpl->height / array_size, VL_MACROBLOCK_HEIGHT);
+	template.height = align(tmpl->height, VL_MACROBLOCK_HEIGHT) / array_size;
 
 	vl_video_buffer_template(&templ, &template, resource_formats[0], 1, array_size, PIPE_USAGE_DEFAULT, 0);
 	/* TODO: get tiling working */
-- 
2.11.0