[Mesa-dev] [PATCH 02/15] radv: save the bound pipeline pointers into the trace BO

[Bas Nieuwenhuizen]

On Tue, Sep 12, 2017 at 12:35 PM, Samuel Pitoiset
<samuel.pitoiset at gmail.com> wrote:
> When a GPU hang is detected in radv_gpu_hang_occured() we know
> which command buffer is faulty but the bound pipelines might
> have been updated during the execution.
>
> The pointers to the radv_pipeline objects are emitted just
> after the second trace ID, that way it would be easy to dump
> the active shaders at the moment of the hang.
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 59 +++++++++++++++++++++++++++++++++++-----
>  src/amd/vulkan/radv_debug.c      |  2 ++
>  2 files changed, 54 insertions(+), 7 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
> index 4e133d1f25..9b6c8c6106 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -329,6 +329,19 @@ radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
>         return true;
>  }
>
> +static void
> +radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
> +                           unsigned count, uint32_t *data)

const uint32_t *data

> +{
> +       radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
> +       radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
> +                   S_370_WR_CONFIRM(1) |
> +                   S_370_ENGINE_SEL(V_370_ME));
> +       radeon_emit(cs, va);
> +       radeon_emit(cs, va >> 32);
> +       radeon_emit_array(cs, data, count);
> +}
> +
>  void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
>  {
>         struct radv_device *device = cmd_buffer->device;
> @@ -346,17 +359,46 @@ void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
>
>         ++cmd_buffer->state.trace_id;
>         device->ws->cs_add_buffer(cs, device->trace_bo, 8);
> -       radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
> -       radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
> -                   S_370_WR_CONFIRM(1) |
> -                   S_370_ENGINE_SEL(V_370_ME));
> -       radeon_emit(cs, va);
> -       radeon_emit(cs, va >> 32);
> -       radeon_emit(cs, cmd_buffer->state.trace_id);
> +       radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
>         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
>         radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
>  }
>
> +static void
> +radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
> +                  struct radv_pipeline *pipeline, enum ring_type ring)
> +{
> +       struct radv_device *device = cmd_buffer->device;
> +       struct radeon_winsys_cs *cs = cmd_buffer->cs;
> +       uint32_t data[2];
> +       uint64_t va;
> +
> +       if (!device->trace_bo)
> +               return;
> +
> +       va = device->ws->buffer_get_va(device->trace_bo);
> +
> +       switch (ring) {
> +       case RING_GFX:
> +               va += 8;
> +               break;
> +       case RING_COMPUTE:
> +               va += 16;
> +               break;
> +       default:
> +               assert(!"invalid ring type");
> +       }
> +
> +       MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
> +                                                          cmd_buffer->cs, 6);
> +
> +       data[0] = (uintptr_t)pipeline;
> +       data[1] = (uintptr_t)pipeline >> 32;
> +
> +       device->ws->cs_add_buffer(cs, device->trace_bo, 8);
> +       radv_emit_write_data_packet(cs, va, 2, data);
> +}
> +
>  static void
>  radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
>                                struct radv_pipeline *pipeline)
> @@ -897,6 +939,8 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
>         }
>         radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
>
> +       radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
> +
>         cmd_buffer->state.emitted_pipeline = pipeline;
>  }
>
> @@ -2292,6 +2336,7 @@ radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
>                     S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
>
>         assert(cmd_buffer->cs->cdw <= cdw_max);
> +       radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
>  }
>
>  static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
> diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
> index 052daaef2f..0dc2d3a22b 100644
> --- a/src/amd/vulkan/radv_debug.c
> +++ b/src/amd/vulkan/radv_debug.c
> @@ -36,6 +36,8 @@
>   *
>   * [0]: primary trace ID
>   * [1]: secondary trace ID
> + * [2-3]: 64-bit GFX pipeline pointer
> + * [4-5]: 64-bit COMPUTE pipeline pointer
>   */
>
>  bool
> --
> 2.14.1
>
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