[Mesa-dev] [PATCH] radeonsi/uvd: fix interlaced video buffer height alignment

[Leo Liu]

On 2017-09-12 02:39 PM, Christian König wrote:
>
>>
>>
>> The problem is:
>>
>> In si_uvd.c
>>
>> struct pipe_video_buffer *si_video_buffer_create(struct pipe_context 
>> *pipe,
>>                          const struct pipe_video_buffer *tmpl)
>> {
>> struct pipe_video_buffer template;
>>
>> template.height = align(tmpl->height / array_size, 
>> VL_MACROBLOCK_HEIGHT);
>>
>>
>> The original info with right height in the tmpl, and that's my first 
>> thought to deal with the issue.
>>
>> but when you keep looking to the code, the tmpl got wiped out, and 
>> leave a new template with 32 aligned height.
>>
>> The video buffer was created based on this new template.
>>
>>
>>> and there are the pipe_resource->width/height which are aligned so 
>>> that the hardware can deal with them.
>>
>> Video buffer and pipe buffer are same, they both got aligned.
>
> Ok, than that is most likely the root problem.

Then how about to add member of "video_width", and "video_height" to 
"struct pipe_video_buffer" ?


Regards,
Leo



> This shouldn't be the case IIRC.
>
> Anyway feel free to go ahead with your original patch, as you noted 
> better not touch that to intense or a lot of things might break.
>
> We should just test with some low res MPEG2 stream to see if the 
> standard PAL/NTSC formats still work.
>
> Regards,
> Christian.
>