[Mesa-dev] [PATCH 2/2] anv/gen9: expose VK_EXT_post_depth_coverage

[Ilia Mirkin]

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---

Note that the use of ICMS_INNER_CONSERVATIVE disagrees with the GL driver.
Perhaps it's more performant than ICMS_NORMAL and is otherwise permitted?
Not sure, so I left it as-is.

Also note that there are no tests for this, and I have not verified anything
besides the fact that the ext shows up on a gen9 device.

 src/intel/vulkan/anv_extensions.py |  2 ++
 src/intel/vulkan/anv_pipeline.c    |  1 +
 src/intel/vulkan/genX_pipeline.c   | 13 +++++++++++--
 3 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_extensions.py b/src/intel/vulkan/anv_extensions.py
index acec785959..5170d48aff 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -76,6 +76,8 @@ EXTENSIONS = [
     Extension('VK_KHR_xlib_surface',                      6, 'VK_USE_PLATFORM_XLIB_KHR'),
     Extension('VK_KHX_multiview',                         1, True),
     Extension('VK_EXT_debug_report',                      8, True),
+    Extension('VK_EXT_post_depth_coverage',               1,
+              'device->instance->physicalDevice.info.gen >= 9'),
 ]
 
 class VkVersion:
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 94e99d8437..30d9d3df90 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -130,6 +130,7 @@ anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
       .image_write_without_format = true,
       .multiview = true,
       .variable_pointers = true,
+      .post_depth_coverage = device->instance->physicalDevice.info.gen >= 9,
    };
 
    nir_function *entry_point =
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 6dfa49b873..84140cd523 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1532,6 +1532,16 @@ emit_3dstate_ps_extra(struct anv_pipeline *pipeline,
       return;
    }
 
+#if GEN_GEN >= 9
+   uint32_t coverage = ICMS_NONE;
+   if (wm_prog_data->uses_sample_mask) {
+      if (wm_prog_data->post_depth_coverage)
+         coverage = ICMS_DEPTH_COVERAGE;
+      else
+         coverage = ICMS_INNER_CONSERVATIVE;
+   }
+#endif
+
    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA), ps) {
       ps.PixelShaderValid              = true;
       ps.AttributeEnable               = wm_prog_data->num_varying_inputs > 0;
@@ -1583,8 +1593,7 @@ emit_3dstate_ps_extra(struct anv_pipeline *pipeline,
 
 #if GEN_GEN >= 9
       ps.PixelShaderPullsBary    = wm_prog_data->pulls_bary;
-      ps.InputCoverageMaskState  = wm_prog_data->uses_sample_mask ?
-                                   ICMS_INNER_CONSERVATIVE : ICMS_NONE;
+      ps.InputCoverageMaskState  = coverage;
 #else
       ps.PixelShaderUsesInputCoverageMask = wm_prog_data->uses_sample_mask;
 #endif
-- 
2.13.5