[Mesa-dev] [PATCH 09/11] st/glsl_to_tgsi: use LDEXP when available
Nicolai Hähnle
nhaehnle at gmail.com
Sat Sep 16 11:23:51 UTC 2017
From: Nicolai Hähnle <nicolai.haehnle at amd.com>
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index cf6e8f8fde1..196b547d3d9 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -576,24 +576,24 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op,
dinst->src[j].index++;
}
if (swz & 1)
dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_W, SWIZZLE_Z, SWIZZLE_W);
else
dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
} else {
/* some opcodes are special case in what they use as sources
- - [FUI]2D/[UI]2I64 is a float/[u]int src0, DLDEXP is integer src1 */
+ - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is integer src1 */
if (op == TGSI_OPCODE_F2D || op == TGSI_OPCODE_U2D || op == TGSI_OPCODE_I2D ||
op == TGSI_OPCODE_I2I64 || op == TGSI_OPCODE_U2I64 ||
- op == TGSI_OPCODE_DLDEXP ||
+ op == TGSI_OPCODE_DLDEXP || op == TGSI_OPCODE_LDEXP ||
(op == TGSI_OPCODE_UCMP && dst_is_64bit[0])) {
dinst->src[j].swizzle = MAKE_SWIZZLE4(swz, swz, swz, swz);
}
}
}
}
inst = dinst;
} else {
this->instructions.push_tail(inst);
}
@@ -2025,20 +2025,22 @@ glsl_to_tgsi_visitor::visit_expression(ir_expression* ir, st_src_reg *op)
case ir_unop_unpack_sampler_2x32:
case ir_unop_pack_sampler_2x32:
case ir_unop_unpack_image_2x32:
case ir_unop_pack_image_2x32:
emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
break;
case ir_binop_ldexp:
if (ir->operands[0]->type->is_double()) {
emit_asm(ir, TGSI_OPCODE_DLDEXP, result_dst, op[0], op[1]);
+ } else if (ir->operands[0]->type->is_float()) {
+ emit_asm(ir, TGSI_OPCODE_LDEXP, result_dst, op[0], op[1]);
} else {
assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
}
break;
case ir_unop_pack_half_2x16:
emit_asm(ir, TGSI_OPCODE_PK2H, result_dst, op[0]);
break;
case ir_unop_unpack_half_2x16:
emit_asm(ir, TGSI_OPCODE_UP2H, result_dst, op[0]);
@@ -6704,20 +6706,22 @@ st_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
struct gl_linked_shader *shader = prog->_LinkedShaders[i];
exec_list *ir = shader->ir;
gl_shader_stage stage = shader->Stage;
const struct gl_shader_compiler_options *options =
&ctx->Const.ShaderCompilerOptions[stage];
enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(stage);
bool have_dround = pscreen->get_shader_param(pscreen, ptarget,
PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED);
bool have_dfrexp = pscreen->get_shader_param(pscreen, ptarget,
PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED);
+ bool have_ldexp = pscreen->get_shader_param(pscreen, ptarget,
+ PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED);
unsigned if_threshold = pscreen->get_shader_param(pscreen, ptarget,
PIPE_SHADER_CAP_LOWER_IF_THRESHOLD);
/* If there are forms of indirect addressing that the driver
* cannot handle, perform the lowering pass.
*/
if (options->EmitNoIndirectInput || options->EmitNoIndirectOutput ||
options->EmitNoIndirectTemp || options->EmitNoIndirectUniform) {
lower_variable_index_to_cond_assign(stage, ir,
options->EmitNoIndirectInput,
@@ -6754,21 +6758,21 @@ st_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
do_mat_op_to_vec(ir);
if (stage == MESA_SHADER_FRAGMENT)
lower_blend_equation_advanced(shader);
lower_instructions(ir,
MOD_TO_FLOOR |
FDIV_TO_MUL_RCP |
EXP_TO_EXP2 |
LOG_TO_LOG2 |
- LDEXP_TO_ARITH |
+ (have_ldexp ? 0 : LDEXP_TO_ARITH) |
(have_dfrexp ? 0 : DFREXP_DLDEXP_TO_ARITH) |
CARRY_TO_ARITH |
BORROW_TO_ARITH |
(have_dround ? 0 : DOPS_TO_DFRAC) |
(options->EmitNoPow ? POW_TO_EXP2 : 0) |
(!ctx->Const.NativeIntegers ? INT_DIV_TO_MUL_RCP : 0) |
(options->EmitNoSat ? SAT_TO_CLAMP : 0) |
(ctx->Const.ForceGLSLAbsSqrt ? SQRT_TO_ABS_SQRT : 0) |
/* Assume that if ARB_gpu_shader5 is not supported
* then all of the extended integer functions need
--
2.11.0
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