[Mesa-dev] [Mesa-stable] [PATCH 2/2] radeonsi: set MIP_POINT_PRECLAMP to 0

[Marek Olšák]

I commented on patch 1. Other than that, the series is:

Reviewed-by: Marek Olšák <marek.olsak at amd.com>

Marek

On Mon, Sep 18, 2017 at 4:57 PM, Nicolai Hähnle <nhaehnle at gmail.com> wrote:
> From: Nicolai Hähnle <nicolai.haehnle at amd.com>
>
> This fixes a bug with nearest ("point") mip selection when the fractional
> part of max_lod is in (0.5,1). In this case, the spec mandates that
> we still select the mip level ceil(max_lod) in the clamping case. However,
> MIP_POINT_PRECLAMP will clamp before the mip selection, which is wrong.
>
> Supposedly this setting was originally copied from the closed Vulkan
> driver, but as far as I can tell, closed Vulkan was actually changed back
> recently :)
>
> Fixes dEQP-GLES3.functional.texture.mipmap.2d.max_lod.{nearest,linear}_nearest
>
> Fixes: f7420ef5b464 ("radeonsi: enable some sampler fields to match the closed driver")
> ---
>  src/gallium/drivers/radeonsi/si_state.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
> index 96f9e444977..3135566cd63 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -3984,21 +3984,21 @@ static void *si_create_sampler_state(struct pipe_context *ctx,
>                           S_008F30_ANISO_BIAS(max_aniso_ratio) |
>                           S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
>                           S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
>         rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
>                           S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
>                           S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
>         rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
>                           S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
>                           S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
>                           S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
> -                         S_008F38_MIP_POINT_PRECLAMP(1) |
> +                         S_008F38_MIP_POINT_PRECLAMP(0) |
>                           S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
>                           S_008F38_FILTER_PREC_FIX(1) |
>                           S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
>         rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
>                          S_008F3C_BORDER_COLOR_TYPE(border_color_type);
>         return rstate;
>  }
>
>  static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
>  {
> --
> 2.11.0
>
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