[Mesa-dev] [PATCH 07/11] radeonsi: move and rename scissor and viewport state and functions
Nicolai Hähnle
nhaehnle at gmail.com
Fri Sep 29 11:01:34 UTC 2017
From: Nicolai Hähnle <nicolai.haehnle at amd.com>
---
src/gallium/drivers/radeon/r600_pipe_common.c | 1 -
src/gallium/drivers/radeon/r600_pipe_common.h | 35 ----
src/gallium/drivers/radeonsi/si_blit.c | 4 +-
src/gallium/drivers/radeonsi/si_hw_context.c | 10 +-
src/gallium/drivers/radeonsi/si_pipe.c | 3 +-
src/gallium/drivers/radeonsi/si_pipe.h | 37 ++++
src/gallium/drivers/radeonsi/si_state.c | 6 +-
src/gallium/drivers/radeonsi/si_state_draw.c | 6 +-
src/gallium/drivers/radeonsi/si_state_shaders.c | 6 +-
src/gallium/drivers/radeonsi/si_viewport.c | 245 ++++++++++++------------
10 files changed, 178 insertions(+), 175 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index 1c6c183b8fc..1aceb5b7559 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -727,21 +727,20 @@ bool si_common_context_init(struct r600_common_context *rctx,
if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
rctx->b.get_device_reset_status = r600_get_reset_status;
rctx->gpu_reset_counter =
rctx->ws->query_value(rctx->ws,
RADEON_GPU_RESET_COUNTER);
}
rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
si_init_context_texture_functions(rctx);
- si_init_viewport_functions(rctx);
si_streamout_init(rctx);
si_init_query_functions(rctx);
si_init_msaa(&rctx->b);
if (rctx->chip_class == CIK ||
rctx->chip_class == VI ||
rctx->chip_class == GFX9) {
rctx->eop_bug_scratch = (struct r600_resource*)
pipe_buffer_create(&rscreen->b, 0, PIPE_USAGE_DEFAULT,
16 * rscreen->info.num_render_backends);
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index 4508a768768..1558943bfec 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -113,21 +113,20 @@ struct u_log_context;
#define DBG_NO_OUT_OF_ORDER (1ull << 48)
#define DBG_UNSAFE_MATH (1ull << 49)
#define DBG_NO_DCC_FB (1ull << 50)
#define DBG_TEST_VMFAULT_CP (1ull << 51)
#define DBG_TEST_VMFAULT_SDMA (1ull << 52)
#define DBG_TEST_VMFAULT_SHADER (1ull << 53)
#define DBG_NO_DPBB (1ull << 54)
#define DBG_NO_DFSM (1ull << 55)
#define R600_MAP_BUFFER_ALIGNMENT 64
-#define R600_MAX_VIEWPORTS 16
#define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
enum r600_coherency {
R600_COHERENCY_NONE, /* no cache flushes needed */
R600_COHERENCY_SHADER,
R600_COHERENCY_CB_META,
};
#ifdef PIPE_ARCH_BIG_ENDIAN
@@ -516,41 +515,20 @@ struct r600_streamout {
/* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
unsigned hw_enabled_mask;
/* The state of VGT_STRMOUT_(CONFIG|EN). */
struct r600_atom enable_atom;
bool streamout_enabled;
bool prims_gen_query_enabled;
int num_prims_gen_queries;
};
-struct r600_signed_scissor {
- int minx;
- int miny;
- int maxx;
- int maxy;
-};
-
-struct r600_scissors {
- struct r600_atom atom;
- unsigned dirty_mask;
- struct pipe_scissor_state states[R600_MAX_VIEWPORTS];
-};
-
-struct r600_viewports {
- struct r600_atom atom;
- unsigned dirty_mask;
- unsigned depth_range_dirty_mask;
- struct pipe_viewport_state states[R600_MAX_VIEWPORTS];
- struct r600_signed_scissor as_scissor[R600_MAX_VIEWPORTS];
-};
-
struct r600_ring {
struct radeon_winsys_cs *cs;
void (*flush)(void *ctx, unsigned flags,
struct pipe_fence_handle **fence);
};
/* Saved CS data for debugging features. */
struct radeon_saved_cs {
uint32_t *ib;
unsigned num_dw;
@@ -583,26 +561,20 @@ struct r600_common_context {
struct u_suballocator *allocator_zeroed_memory;
struct slab_child_pool pool_transfers;
struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
/* Current unaccounted memory usage. */
uint64_t vram;
uint64_t gtt;
/* States. */
struct r600_streamout streamout;
- struct r600_scissors scissors;
- struct r600_viewports viewports;
- bool scissor_enabled;
- bool clip_halfz;
- bool vs_writes_viewport_index;
- bool vs_disables_clipping_viewport;
/* Additional context states. */
unsigned flags; /* flush flags */
enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
/* Queries. */
/* Maintain the list of active queries for pausing between IBs. */
int num_occlusion_queries;
int num_perfect_occlusion_queries;
struct list_head active_queries;
@@ -872,27 +844,20 @@ void vi_dcc_clear_level(struct r600_common_context *rctx,
void si_do_fast_color_clear(struct r600_common_context *rctx,
struct pipe_framebuffer_state *fb,
struct r600_atom *fb_state,
unsigned *buffers, ubyte *dirty_cbufs,
const union pipe_color_union *color);
bool si_texture_disable_dcc(struct r600_common_context *rctx,
struct r600_texture *rtex);
void si_init_screen_texture_functions(struct r600_common_screen *rscreen);
void si_init_context_texture_functions(struct r600_common_context *rctx);
-/* r600_viewport.c */
-void si_viewport_set_rast_deps(struct r600_common_context *rctx,
- bool scissor_enable, bool clip_halfz);
-void si_update_vs_writes_viewport_index(struct r600_common_context *rctx,
- struct tgsi_shader_info *info);
-void si_init_viewport_functions(struct r600_common_context *rctx);
-
/* cayman_msaa.c */
void si_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
unsigned sample_index, float *out_value);
void si_init_msaa(struct pipe_context *ctx);
void si_common_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
void si_common_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
int ps_iter_samples, int overrast_samples,
unsigned sc_mode_cntl_1);
diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index f5ae072f4f8..b8ff67d5ab7 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -63,22 +63,22 @@ static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
(struct pipe_stream_output_target**)sctx->b.streamout.targets);
util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
if (op & SI_SAVE_FRAGMENT_STATE) {
util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
- util_blitter_save_viewport(sctx->blitter, &sctx->b.viewports.states[0]);
- util_blitter_save_scissor(sctx->blitter, &sctx->b.scissors.states[0]);
+ util_blitter_save_viewport(sctx->blitter, &sctx->viewports.states[0]);
+ util_blitter_save_scissor(sctx->blitter, &sctx->scissors.states[0]);
}
if (op & SI_SAVE_FRAMEBUFFER)
util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
if (op & SI_SAVE_TEXTURES) {
util_blitter_save_fragment_sampler_states(
sctx->blitter, 2,
(void**)sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c
index dafb3bfa5fe..ef03a6d2c68 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -241,25 +241,25 @@ void si_begin_new_cs(struct si_context *ctx)
si_mark_atom_dirty(ctx, &ctx->db_render_state);
if (ctx->b.chip_class >= GFX9)
si_mark_atom_dirty(ctx, &ctx->dpbb_state);
si_mark_atom_dirty(ctx, &ctx->stencil_ref.atom);
si_mark_atom_dirty(ctx, &ctx->spi_map);
si_mark_atom_dirty(ctx, &ctx->b.streamout.enable_atom);
si_mark_atom_dirty(ctx, &ctx->b.render_cond_atom);
si_all_descriptors_begin_new_cs(ctx);
si_all_resident_buffers_begin_new_cs(ctx);
- ctx->b.scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
- ctx->b.viewports.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
- ctx->b.viewports.depth_range_dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
- si_mark_atom_dirty(ctx, &ctx->b.scissors.atom);
- si_mark_atom_dirty(ctx, &ctx->b.viewports.atom);
+ ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
+ ctx->viewports.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
+ ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
+ si_mark_atom_dirty(ctx, &ctx->scissors.atom);
+ si_mark_atom_dirty(ctx, &ctx->viewports.atom);
si_mark_atom_dirty(ctx, &ctx->scratch_state);
if (ctx->scratch_buffer) {
r600_context_add_resource_size(&ctx->b.b,
&ctx->scratch_buffer->b.b);
}
si_postflush_resume_features(&ctx->b);
assert(!ctx->b.gfx.cs->prev_dw);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 954f9ff063f..33f5adbd3ad 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -223,20 +223,21 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
sctx->border_color_map =
ws->buffer_map(sctx->border_color_buffer->buf,
NULL, PIPE_TRANSFER_WRITE);
if (!sctx->border_color_map)
goto fail;
si_init_all_descriptors(sctx);
si_init_state_functions(sctx);
si_init_shader_functions(sctx);
+ si_init_viewport_functions(sctx);
si_init_ia_multi_vgt_param_table(sctx);
if (sctx->b.chip_class >= CIK)
cik_init_sdma_functions(sctx);
else
si_init_dma_functions(sctx);
if (sscreen->b.debug_flags & DBG_FORCE_DMA)
sctx->b.b.resource_copy_region = sctx->b.dma_copy;
@@ -613,21 +614,21 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
return 15; /* 16384 */
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
/* textures support 8192, but layered rendering supports 2048 */
return 12;
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
/* textures support 8192, but layered rendering supports 2048 */
return 2048;
/* Viewports and render targets. */
case PIPE_CAP_MAX_VIEWPORTS:
- return R600_MAX_VIEWPORTS;
+ return SI_MAX_VIEWPORTS;
case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
case PIPE_CAP_MAX_RENDER_TARGETS:
return 8;
case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
case PIPE_CAP_MIN_TEXEL_OFFSET:
return -32;
case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
case PIPE_CAP_MAX_TEXEL_OFFSET:
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 08d47ea414e..b3d5b186457 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -74,20 +74,21 @@
#define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
#define SI_PREFETCH_LS (1 << 1)
#define SI_PREFETCH_HS (1 << 2)
#define SI_PREFETCH_ES (1 << 3)
#define SI_PREFETCH_GS (1 << 4)
#define SI_PREFETCH_VS (1 << 5)
#define SI_PREFETCH_PS (1 << 6)
#define SI_MAX_BORDER_COLORS 4096
+#define SI_MAX_VIEWPORTS 16
#define SIX_BITS 0x3F
struct si_compute;
struct hash_table;
struct u_suballocator;
struct si_screen {
struct r600_common_screen b;
unsigned gs_table_depth;
unsigned tess_offchip_block_dw_size;
@@ -205,20 +206,41 @@ struct si_framebuffer {
ubyte compressed_cb_mask;
ubyte color_is_int8;
ubyte color_is_int10;
ubyte dirty_cbufs;
bool dirty_zsbuf;
bool any_dst_linear;
bool CB_has_shader_readable_metadata;
bool DB_has_shader_readable_metadata;
};
+struct si_signed_scissor {
+ int minx;
+ int miny;
+ int maxx;
+ int maxy;
+};
+
+struct si_scissors {
+ struct r600_atom atom;
+ unsigned dirty_mask;
+ struct pipe_scissor_state states[SI_MAX_VIEWPORTS];
+};
+
+struct si_viewports {
+ struct r600_atom atom;
+ unsigned dirty_mask;
+ unsigned depth_range_dirty_mask;
+ struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
+ struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
+};
+
struct si_clip_state {
struct r600_atom atom;
struct pipe_clip_state state;
bool any_nonzeros;
};
struct si_sample_locs {
struct r600_atom atom;
unsigned nr_samples;
};
@@ -319,20 +341,22 @@ struct si_context {
struct r600_atom msaa_config;
struct si_sample_mask sample_mask;
struct r600_atom cb_render_state;
unsigned last_cb_target_mask;
struct si_blend_color blend_color;
struct r600_atom clip_regs;
struct si_clip_state clip_state;
struct si_shader_data shader_pointers;
struct si_stencil_ref stencil_ref;
struct r600_atom spi_map;
+ struct si_scissors scissors;
+ struct si_viewports viewports;
/* Precomputed states. */
struct si_pm4_state *init_config;
struct si_pm4_state *init_config_gs_rings;
bool init_config_has_vgt_flush;
struct si_pm4_state *vgt_shader_config[4];
/* shaders */
struct si_shader_ctx_state ps_shader;
struct si_shader_ctx_state gs_shader;
@@ -430,20 +454,25 @@ struct si_context {
/* Debug state. */
bool is_debug;
struct si_saved_cs *current_saved_cs;
uint64_t dmesg_timestamp;
unsigned apitrace_call_number;
/* Other state */
bool need_check_render_feedback;
bool decompression_enabled;
+ bool scissor_enabled;
+ bool clip_halfz;
+ bool vs_writes_viewport_index;
+ bool vs_disables_clipping_viewport;
+
/* Precomputed IA_MULTI_VGT_PARAM */
union si_vgt_param_key ia_multi_vgt_param_key;
unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
/* Bindless descriptors. */
struct si_descriptors bindless_descriptors;
struct util_idalloc bindless_used_slots;
unsigned num_bindless_descriptors;
bool bindless_descriptors_dirty;
bool graphics_bindless_pointer_dirty;
@@ -529,20 +558,28 @@ void si_init_compute_functions(struct si_context *sctx);
/* si_perfcounters.c */
void si_init_perfcounters(struct si_screen *screen);
/* si_uvd.c */
struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
const struct pipe_video_codec *templ);
struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
const struct pipe_video_buffer *tmpl);
+/* si_viewport.c */
+void si_viewport_set_rast_deps(struct si_context *rctx,
+ bool scissor_enable, bool clip_halfz);
+void si_update_vs_writes_viewport_index(struct si_context *ctx,
+ struct tgsi_shader_info *info);
+void si_init_viewport_functions(struct si_context *ctx);
+
+
/*
* common helpers
*/
static inline void
si_invalidate_draw_sh_constants(struct si_context *sctx)
{
sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
}
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 3fbacec5668..2dbe7c6e274 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -996,21 +996,21 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state)
/* Update the small primitive filter workaround if necessary. */
if (sctx->screen->has_msaa_sample_loc_bug &&
sctx->framebuffer.nr_samples > 1)
si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
}
sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
- si_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
+ si_viewport_set_rast_deps(sctx, rs->scissor_enable, rs->clip_halfz);
si_pm4_bind_state(sctx, rasterizer, rs);
si_update_poly_offset_state(sctx);
if (!old_rs ||
old_rs->clip_plane_enable != rs->clip_plane_enable ||
old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
si_mark_atom_dirty(sctx, &sctx->clip_regs);
sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
@@ -4395,22 +4395,22 @@ static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
si_need_cs_space((struct si_context*)ctx);
}
static void si_init_config(struct si_context *sctx);
void si_init_state_functions(struct si_context *sctx)
{
si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
- si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
- si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
+ si_init_external_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors);
+ si_init_external_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports);
si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
si_init_atom(sctx, &sctx->dpbb_state, &sctx->atoms.s.dpbb_state, si_emit_dpbb_state);
si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 42807c03091..9a6c9c8f842 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1254,22 +1254,22 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
rast_prim = PIPE_PRIM_POINTS;
else
rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
} else
rast_prim = info->mode;
if (rast_prim != sctx->b.current_rast_prim) {
bool old_is_poly = sctx->b.current_rast_prim >= PIPE_PRIM_TRIANGLES;
bool new_is_poly = rast_prim >= PIPE_PRIM_TRIANGLES;
if (old_is_poly != new_is_poly) {
- sctx->b.scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
- si_set_atom_dirty(sctx, &sctx->b.scissors.atom, true);
+ sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
+ si_mark_atom_dirty(sctx, &sctx->scissors.atom);
}
sctx->b.current_rast_prim = rast_prim;
sctx->do_update_shaders = true;
}
if (sctx->tes_shader.cso &&
(sctx->b.family == CHIP_VEGA10 || sctx->b.family == CHIP_RAVEN)) {
/* Determine whether the LS VGPR fix should be applied.
*
@@ -1391,21 +1391,21 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
* need_cs_space flush before we add buffers to the buffer list.
*/
if (!si_upload_vertex_buffer_descriptors(sctx))
return;
/* GFX9 scissor bug workaround. This must be done before VPORT scissor
* registers are changed. There is also a more efficient but more
* involved alternative workaround.
*/
if (sctx->b.chip_class == GFX9 &&
- si_is_atom_dirty(sctx, &sctx->b.scissors.atom)) {
+ si_is_atom_dirty(sctx, &sctx->scissors.atom)) {
sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
si_emit_cache_flush(sctx);
}
/* Use optimal packet order based on whether we need to sync the pipeline. */
if (unlikely(sctx->b.flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
SI_CONTEXT_FLUSH_AND_INV_DB |
SI_CONTEXT_PS_PARTIAL_FLUSH |
SI_CONTEXT_CS_PARTIAL_FLUSH))) {
/* If we have to wait for idle, set all states first, so that all
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 1146e5e3949..42814d9fd58 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -2294,21 +2294,21 @@ static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
struct si_shader_selector *sel = state;
if (sctx->vs_shader.cso == sel)
return;
sctx->vs_shader.cso = sel;
sctx->vs_shader.current = sel ? sel->first_variant : NULL;
si_update_common_shader_state(sctx);
- si_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
+ si_update_vs_writes_viewport_index(sctx, si_get_vs_info(sctx));
si_set_active_descriptors_for_shader(sctx, sel);
si_update_streamout_state(sctx);
si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
si_get_vs(sctx)->cso, si_get_vs_state(sctx));
}
static void si_update_tess_uses_prim_id(struct si_context *sctx)
{
sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
(sctx->tes_shader.cso &&
@@ -2337,21 +2337,21 @@ static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
si_update_common_shader_state(sctx);
sctx->last_rast_prim = -1; /* reset this so that it gets updated */
if (enable_changed) {
si_shader_change_notify(sctx);
if (sctx->ia_multi_vgt_param_key.u.uses_tess)
si_update_tess_uses_prim_id(sctx);
}
- si_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
+ si_update_vs_writes_viewport_index(sctx, si_get_vs_info(sctx));
si_set_active_descriptors_for_shader(sctx, sel);
si_update_streamout_state(sctx);
si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
si_get_vs(sctx)->cso, si_get_vs_state(sctx));
}
static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
{
struct si_context *sctx = (struct si_context *)ctx;
struct si_shader_selector *sel = state;
@@ -2388,21 +2388,21 @@ static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
si_update_tess_uses_prim_id(sctx);
si_update_common_shader_state(sctx);
sctx->last_rast_prim = -1; /* reset this so that it gets updated */
if (enable_changed) {
si_shader_change_notify(sctx);
sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
}
- si_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
+ si_update_vs_writes_viewport_index(sctx, si_get_vs_info(sctx));
si_set_active_descriptors_for_shader(sctx, sel);
si_update_streamout_state(sctx);
si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
si_get_vs(sctx)->cso, si_get_vs_state(sctx));
}
static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
{
struct si_context *sctx = (struct si_context *)ctx;
struct si_shader_selector *old_sel = sctx->ps_shader.cso;
diff --git a/src/gallium/drivers/radeonsi/si_viewport.c b/src/gallium/drivers/radeonsi/si_viewport.c
index 54f31c4694d..fcc869f1622 100644
--- a/src/gallium/drivers/radeonsi/si_viewport.c
+++ b/src/gallium/drivers/radeonsi/si_viewport.c
@@ -14,50 +14,52 @@
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
+#include "si_pipe.h"
+#include "sid.h"
#include "radeon/r600_cs.h"
#include "util/u_viewport.h"
#include "tgsi/tgsi_scan.h"
-#define GET_MAX_SCISSOR(rctx) (rctx->chip_class >= EVERGREEN ? 16384 : 8192)
+#define GET_MAX_SCISSOR(rctx) (16384)
-static void r600_set_scissor_states(struct pipe_context *ctx,
- unsigned start_slot,
- unsigned num_scissors,
- const struct pipe_scissor_state *state)
+static void si_set_scissor_states(struct pipe_context *pctx,
+ unsigned start_slot,
+ unsigned num_scissors,
+ const struct pipe_scissor_state *state)
{
- struct r600_common_context *rctx = (struct r600_common_context *)ctx;
+ struct si_context *ctx = (struct si_context *)pctx;
int i;
for (i = 0; i < num_scissors; i++)
- rctx->scissors.states[start_slot + i] = state[i];
+ ctx->scissors.states[start_slot + i] = state[i];
- if (!rctx->scissor_enabled)
+ if (!ctx->scissor_enabled)
return;
- rctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
- rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
+ ctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
+ si_mark_atom_dirty(ctx, &ctx->scissors.atom);
}
/* Since the guard band disables clipping, we have to clip per-pixel
* using a scissor.
*/
-static void r600_get_scissor_from_viewport(struct r600_common_context *rctx,
- const struct pipe_viewport_state *vp,
- struct r600_signed_scissor *scissor)
+static void si_get_scissor_from_viewport(struct si_context *ctx,
+ const struct pipe_viewport_state *vp,
+ struct si_signed_scissor *scissor)
{
float tmp, minx, miny, maxx, maxy;
/* Convert (-1, -1) and (1, 1) from clip space into window space. */
minx = -vp->scale[0] + vp->translate[0];
miny = -vp->scale[1] + vp->translate[1];
maxx = vp->scale[0] + vp->translate[0];
maxy = vp->scale[1] + vp->translate[1];
/* r600_draw_rectangle sets this. Disable the scissor. */
@@ -79,80 +81,80 @@ static void r600_get_scissor_from_viewport(struct r600_common_context *rctx,
maxy = tmp;
}
/* Convert to integer and round up the max bounds. */
scissor->minx = minx;
scissor->miny = miny;
scissor->maxx = ceilf(maxx);
scissor->maxy = ceilf(maxy);
}
-static void r600_clamp_scissor(struct r600_common_context *rctx,
- struct pipe_scissor_state *out,
- struct r600_signed_scissor *scissor)
+static void si_clamp_scissor(struct si_context *ctx,
+ struct pipe_scissor_state *out,
+ struct si_signed_scissor *scissor)
{
unsigned max_scissor = GET_MAX_SCISSOR(rctx);
out->minx = CLAMP(scissor->minx, 0, max_scissor);
out->miny = CLAMP(scissor->miny, 0, max_scissor);
out->maxx = CLAMP(scissor->maxx, 0, max_scissor);
out->maxy = CLAMP(scissor->maxy, 0, max_scissor);
}
-static void r600_clip_scissor(struct pipe_scissor_state *out,
- struct pipe_scissor_state *clip)
+static void si_clip_scissor(struct pipe_scissor_state *out,
+ struct pipe_scissor_state *clip)
{
out->minx = MAX2(out->minx, clip->minx);
out->miny = MAX2(out->miny, clip->miny);
out->maxx = MIN2(out->maxx, clip->maxx);
out->maxy = MIN2(out->maxy, clip->maxy);
}
-static void r600_scissor_make_union(struct r600_signed_scissor *out,
- struct r600_signed_scissor *in)
+static void si_scissor_make_union(struct si_signed_scissor *out,
+ struct si_signed_scissor *in)
{
out->minx = MIN2(out->minx, in->minx);
out->miny = MIN2(out->miny, in->miny);
out->maxx = MAX2(out->maxx, in->maxx);
out->maxy = MAX2(out->maxy, in->maxy);
}
-static void r600_emit_one_scissor(struct r600_common_context *rctx,
- struct radeon_winsys_cs *cs,
- struct r600_signed_scissor *vp_scissor,
- struct pipe_scissor_state *scissor)
+static void si_emit_one_scissor(struct si_context *ctx,
+ struct radeon_winsys_cs *cs,
+ struct si_signed_scissor *vp_scissor,
+ struct pipe_scissor_state *scissor)
{
struct pipe_scissor_state final;
- if (rctx->vs_disables_clipping_viewport) {
+ if (ctx->vs_disables_clipping_viewport) {
final.minx = final.miny = 0;
final.maxx = final.maxy = GET_MAX_SCISSOR(rctx);
} else {
- r600_clamp_scissor(rctx, &final, vp_scissor);
+ si_clamp_scissor(ctx, &final, vp_scissor);
}
if (scissor)
- r600_clip_scissor(&final, scissor);
+ si_clip_scissor(&final, scissor);
radeon_emit(cs, S_028250_TL_X(final.minx) |
S_028250_TL_Y(final.miny) |
S_028250_WINDOW_OFFSET_DISABLE(1));
radeon_emit(cs, S_028254_BR_X(final.maxx) |
S_028254_BR_Y(final.maxy));
}
/* the range is [-MAX, MAX] */
-#define GET_MAX_VIEWPORT_RANGE(rctx) (rctx->chip_class >= EVERGREEN ? 32768 : 16384)
+#define GET_MAX_VIEWPORT_RANGE(rctx) (32768)
-static void r600_emit_guardband(struct r600_common_context *rctx,
- struct r600_signed_scissor *vp_as_scissor)
+static void si_emit_guardband(struct si_context *ctx,
+ struct si_signed_scissor *vp_as_scissor)
{
- struct radeon_winsys_cs *cs = rctx->gfx.cs;
+ struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
struct pipe_viewport_state vp;
float left, top, right, bottom, max_range, guardband_x, guardband_y;
float discard_x, discard_y;
/* Reconstruct the viewport transformation from the scissor. */
vp.translate[0] = (vp_as_scissor->minx + vp_as_scissor->maxx) / 2.0;
vp.translate[1] = (vp_as_scissor->miny + vp_as_scissor->maxy) / 2.0;
vp.scale[0] = vp_as_scissor->maxx - vp.translate[0];
vp.scale[1] = vp_as_scissor->maxy - vp.translate[1];
@@ -164,270 +166,269 @@ static void r600_emit_guardband(struct r600_common_context *rctx,
/* Find the biggest guard band that is inside the supported viewport
* range. The guard band is specified as a horizontal and vertical
* distance from (0,0) in clip space.
*
* This is done by applying the inverse viewport transformation
* on the viewport limits to get those limits in clip space.
*
* Use a limit one pixel smaller to allow for some precision error.
*/
- max_range = GET_MAX_VIEWPORT_RANGE(rctx) - 1;
+ max_range = GET_MAX_VIEWPORT_RANGE(ctx) - 1;
left = (-max_range - vp.translate[0]) / vp.scale[0];
right = ( max_range - vp.translate[0]) / vp.scale[0];
top = (-max_range - vp.translate[1]) / vp.scale[1];
bottom = ( max_range - vp.translate[1]) / vp.scale[1];
assert(left <= -1 && top <= -1 && right >= 1 && bottom >= 1);
guardband_x = MIN2(-left, right);
guardband_y = MIN2(-top, bottom);
discard_x = 1.0;
discard_y = 1.0;
- if (rctx->current_rast_prim < PIPE_PRIM_TRIANGLES) {
+ if (ctx->b.current_rast_prim < PIPE_PRIM_TRIANGLES) {
/* When rendering wide points or lines, we need to be more
* conservative about when to discard them entirely. Since
* point size can be determined by the VS output, we basically
* disable discard completely completely here.
*
* TODO: This can hurt performance when rendering lines and
* points with fixed size, and could be improved.
*/
discard_x = guardband_x;
discard_y = guardband_y;
}
/* If any of the GB registers is updated, all of them must be updated. */
- if (rctx->chip_class >= CAYMAN)
- radeon_set_context_reg_seq(cs, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
- else
- radeon_set_context_reg_seq(cs, R600_R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
+ radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
radeon_emit(cs, fui(guardband_y)); /* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
radeon_emit(cs, fui(discard_y)); /* R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
radeon_emit(cs, fui(guardband_x)); /* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
radeon_emit(cs, fui(discard_x)); /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
}
-static void r600_emit_scissors(struct r600_common_context *rctx, struct r600_atom *atom)
+static void si_emit_scissors(struct r600_common_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->gfx.cs;
- struct pipe_scissor_state *states = rctx->scissors.states;
- unsigned mask = rctx->scissors.dirty_mask;
- bool scissor_enabled = rctx->scissor_enabled;
- struct r600_signed_scissor max_vp_scissor;
+ struct si_context *ctx = (struct si_context *)rctx;
+ struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
+ struct pipe_scissor_state *states = ctx->scissors.states;
+ unsigned mask = ctx->scissors.dirty_mask;
+ bool scissor_enabled = ctx->scissor_enabled;
+ struct si_signed_scissor max_vp_scissor;
int i;
/* The simple case: Only 1 viewport is active. */
- if (!rctx->vs_writes_viewport_index) {
- struct r600_signed_scissor *vp = &rctx->viewports.as_scissor[0];
+ if (!ctx->vs_writes_viewport_index) {
+ struct si_signed_scissor *vp = &ctx->viewports.as_scissor[0];
if (!(mask & 1))
return;
radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
- r600_emit_one_scissor(rctx, cs, vp, scissor_enabled ? &states[0] : NULL);
- r600_emit_guardband(rctx, vp);
- rctx->scissors.dirty_mask &= ~1; /* clear one bit */
+ si_emit_one_scissor(ctx, cs, vp, scissor_enabled ? &states[0] : NULL);
+ si_emit_guardband(ctx, vp);
+ ctx->scissors.dirty_mask &= ~1; /* clear one bit */
return;
}
/* Shaders can draw to any viewport. Make a union of all viewports. */
- max_vp_scissor = rctx->viewports.as_scissor[0];
- for (i = 1; i < R600_MAX_VIEWPORTS; i++)
- r600_scissor_make_union(&max_vp_scissor,
- &rctx->viewports.as_scissor[i]);
+ max_vp_scissor = ctx->viewports.as_scissor[0];
+ for (i = 1; i < SI_MAX_VIEWPORTS; i++)
+ si_scissor_make_union(&max_vp_scissor,
+ &ctx->viewports.as_scissor[i]);
while (mask) {
int start, count, i;
u_bit_scan_consecutive_range(&mask, &start, &count);
radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
start * 4 * 2, count * 2);
for (i = start; i < start+count; i++) {
- r600_emit_one_scissor(rctx, cs, &rctx->viewports.as_scissor[i],
- scissor_enabled ? &states[i] : NULL);
+ si_emit_one_scissor(ctx, cs, &ctx->viewports.as_scissor[i],
+ scissor_enabled ? &states[i] : NULL);
}
}
- r600_emit_guardband(rctx, &max_vp_scissor);
- rctx->scissors.dirty_mask = 0;
+ si_emit_guardband(ctx, &max_vp_scissor);
+ ctx->scissors.dirty_mask = 0;
}
-static void r600_set_viewport_states(struct pipe_context *ctx,
- unsigned start_slot,
- unsigned num_viewports,
- const struct pipe_viewport_state *state)
+static void si_set_viewport_states(struct pipe_context *pctx,
+ unsigned start_slot,
+ unsigned num_viewports,
+ const struct pipe_viewport_state *state)
{
- struct r600_common_context *rctx = (struct r600_common_context *)ctx;
+ struct si_context *ctx = (struct si_context *)pctx;
unsigned mask;
int i;
for (i = 0; i < num_viewports; i++) {
unsigned index = start_slot + i;
- rctx->viewports.states[index] = state[i];
- r600_get_scissor_from_viewport(rctx, &state[i],
- &rctx->viewports.as_scissor[index]);
+ ctx->viewports.states[index] = state[i];
+ si_get_scissor_from_viewport(ctx, &state[i],
+ &ctx->viewports.as_scissor[index]);
}
mask = ((1 << num_viewports) - 1) << start_slot;
- rctx->viewports.dirty_mask |= mask;
- rctx->viewports.depth_range_dirty_mask |= mask;
- rctx->scissors.dirty_mask |= mask;
- rctx->set_atom_dirty(rctx, &rctx->viewports.atom, true);
- rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
+ ctx->viewports.dirty_mask |= mask;
+ ctx->viewports.depth_range_dirty_mask |= mask;
+ ctx->scissors.dirty_mask |= mask;
+ si_mark_atom_dirty(ctx, &ctx->viewports.atom);
+ si_mark_atom_dirty(ctx, &ctx->scissors.atom);
}
-static void r600_emit_one_viewport(struct r600_common_context *rctx,
- struct pipe_viewport_state *state)
+static void si_emit_one_viewport(struct si_context *ctx,
+ struct pipe_viewport_state *state)
{
- struct radeon_winsys_cs *cs = rctx->gfx.cs;
+ struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
radeon_emit(cs, fui(state->scale[0]));
radeon_emit(cs, fui(state->translate[0]));
radeon_emit(cs, fui(state->scale[1]));
radeon_emit(cs, fui(state->translate[1]));
radeon_emit(cs, fui(state->scale[2]));
radeon_emit(cs, fui(state->translate[2]));
}
-static void r600_emit_viewports(struct r600_common_context *rctx)
+static void si_emit_viewports(struct si_context *ctx)
{
- struct radeon_winsys_cs *cs = rctx->gfx.cs;
- struct pipe_viewport_state *states = rctx->viewports.states;
- unsigned mask = rctx->viewports.dirty_mask;
+ struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
+ struct pipe_viewport_state *states = ctx->viewports.states;
+ unsigned mask = ctx->viewports.dirty_mask;
/* The simple case: Only 1 viewport is active. */
- if (!rctx->vs_writes_viewport_index) {
+ if (!ctx->vs_writes_viewport_index) {
if (!(mask & 1))
return;
radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
- r600_emit_one_viewport(rctx, &states[0]);
- rctx->viewports.dirty_mask &= ~1; /* clear one bit */
+ si_emit_one_viewport(ctx, &states[0]);
+ ctx->viewports.dirty_mask &= ~1; /* clear one bit */
return;
}
while (mask) {
int start, count, i;
u_bit_scan_consecutive_range(&mask, &start, &count);
radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
start * 4 * 6, count * 6);
for (i = start; i < start+count; i++)
- r600_emit_one_viewport(rctx, &states[i]);
+ si_emit_one_viewport(ctx, &states[i]);
}
- rctx->viewports.dirty_mask = 0;
+ ctx->viewports.dirty_mask = 0;
}
-static void r600_emit_depth_ranges(struct r600_common_context *rctx)
+static void si_emit_depth_ranges(struct si_context *ctx)
{
- struct radeon_winsys_cs *cs = rctx->gfx.cs;
- struct pipe_viewport_state *states = rctx->viewports.states;
- unsigned mask = rctx->viewports.depth_range_dirty_mask;
+ struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
+ struct pipe_viewport_state *states = ctx->viewports.states;
+ unsigned mask = ctx->viewports.depth_range_dirty_mask;
float zmin, zmax;
/* The simple case: Only 1 viewport is active. */
- if (!rctx->vs_writes_viewport_index) {
+ if (!ctx->vs_writes_viewport_index) {
if (!(mask & 1))
return;
- util_viewport_zmin_zmax(&states[0], rctx->clip_halfz, &zmin, &zmax);
+ util_viewport_zmin_zmax(&states[0], ctx->clip_halfz, &zmin, &zmax);
radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
radeon_emit(cs, fui(zmin));
radeon_emit(cs, fui(zmax));
- rctx->viewports.depth_range_dirty_mask &= ~1; /* clear one bit */
+ ctx->viewports.depth_range_dirty_mask &= ~1; /* clear one bit */
return;
}
while (mask) {
int start, count, i;
u_bit_scan_consecutive_range(&mask, &start, &count);
radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
start * 4 * 2, count * 2);
for (i = start; i < start+count; i++) {
- util_viewport_zmin_zmax(&states[i], rctx->clip_halfz, &zmin, &zmax);
+ util_viewport_zmin_zmax(&states[i], ctx->clip_halfz, &zmin, &zmax);
radeon_emit(cs, fui(zmin));
radeon_emit(cs, fui(zmax));
}
}
- rctx->viewports.depth_range_dirty_mask = 0;
+ ctx->viewports.depth_range_dirty_mask = 0;
}
-static void r600_emit_viewport_states(struct r600_common_context *rctx,
- struct r600_atom *atom)
+static void si_emit_viewport_states(struct r600_common_context *rctx,
+ struct r600_atom *atom)
{
- r600_emit_viewports(rctx);
- r600_emit_depth_ranges(rctx);
+ struct si_context *ctx = (struct si_context *)rctx;
+ si_emit_viewports(ctx);
+ si_emit_depth_ranges(ctx);
}
/* Set viewport dependencies on pipe_rasterizer_state. */
-void si_viewport_set_rast_deps(struct r600_common_context *rctx,
+void si_viewport_set_rast_deps(struct si_context *ctx,
bool scissor_enable, bool clip_halfz)
{
- if (rctx->scissor_enabled != scissor_enable) {
- rctx->scissor_enabled = scissor_enable;
- rctx->scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
- rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
+ if (ctx->scissor_enabled != scissor_enable) {
+ ctx->scissor_enabled = scissor_enable;
+ ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
+ si_mark_atom_dirty(ctx, &ctx->scissors.atom);
}
- if (rctx->clip_halfz != clip_halfz) {
- rctx->clip_halfz = clip_halfz;
- rctx->viewports.depth_range_dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
- rctx->set_atom_dirty(rctx, &rctx->viewports.atom, true);
+ if (ctx->clip_halfz != clip_halfz) {
+ ctx->clip_halfz = clip_halfz;
+ ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
+ si_mark_atom_dirty(ctx, &ctx->viewports.atom);
}
}
/**
* Normally, we only emit 1 viewport and 1 scissor if no shader is using
* the VIEWPORT_INDEX output, and emitting the other viewports and scissors
* is delayed. When a shader with VIEWPORT_INDEX appears, this should be
* called to emit the rest.
*/
-void si_update_vs_writes_viewport_index(struct r600_common_context *rctx,
+void si_update_vs_writes_viewport_index(struct si_context *ctx,
struct tgsi_shader_info *info)
{
bool vs_window_space;
if (!info)
return;
/* When the VS disables clipping and viewport transformation. */
vs_window_space =
info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
- if (rctx->vs_disables_clipping_viewport != vs_window_space) {
- rctx->vs_disables_clipping_viewport = vs_window_space;
- rctx->scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
- rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
+ if (ctx->vs_disables_clipping_viewport != vs_window_space) {
+ ctx->vs_disables_clipping_viewport = vs_window_space;
+ ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
+ si_mark_atom_dirty(ctx, &ctx->scissors.atom);
}
/* Viewport index handling. */
- rctx->vs_writes_viewport_index = info->writes_viewport_index;
- if (!rctx->vs_writes_viewport_index)
+ ctx->vs_writes_viewport_index = info->writes_viewport_index;
+ if (!ctx->vs_writes_viewport_index)
return;
- if (rctx->scissors.dirty_mask)
- rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
+ if (ctx->scissors.dirty_mask)
+ si_mark_atom_dirty(ctx, &ctx->scissors.atom);
- if (rctx->viewports.dirty_mask ||
- rctx->viewports.depth_range_dirty_mask)
- rctx->set_atom_dirty(rctx, &rctx->viewports.atom, true);
+ if (ctx->viewports.dirty_mask ||
+ ctx->viewports.depth_range_dirty_mask)
+ si_mark_atom_dirty(ctx, &ctx->viewports.atom);
}
-void si_init_viewport_functions(struct r600_common_context *rctx)
+void si_init_viewport_functions(struct si_context *ctx)
{
- rctx->scissors.atom.emit = r600_emit_scissors;
- rctx->viewports.atom.emit = r600_emit_viewport_states;
+ ctx->scissors.atom.emit = si_emit_scissors;
+ ctx->viewports.atom.emit = si_emit_viewport_states;
- rctx->scissors.atom.num_dw = (2 + 16 * 2) + 6;
- rctx->viewports.atom.num_dw = 2 + 16 * 6;
+ ctx->scissors.atom.num_dw = (2 + 16 * 2) + 6;
+ ctx->viewports.atom.num_dw = 2 + 16 * 6;
- rctx->b.set_scissor_states = r600_set_scissor_states;
- rctx->b.set_viewport_states = r600_set_viewport_states;
+ ctx->b.b.set_scissor_states = si_set_scissor_states;
+ ctx->b.b.set_viewport_states = si_set_viewport_states;
}
--
2.11.0
More information about the mesa-dev
mailing list