[Mesa-dev] [PATCH 13/13] i965/fs: Don't apply POW/FDIV workaround on Gen10+

[Scott D Phillips]

Matt Turner <mattst88 at gmail.com> writes:

> The documentation says it applies only to Gens 8 and 9.

Patch 10 & 13:
Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

> ---
>  src/intel/compiler/brw_fs_generator.cpp | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
> index 03ee26ccd4..07fd6307f0 100644
> --- a/src/intel/compiler/brw_fs_generator.cpp
> +++ b/src/intel/compiler/brw_fs_generator.cpp
> @@ -1639,6 +1639,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
>         * and empirically this affects CHV as well.
>         */
>        if (devinfo->gen >= 8 &&
> +          devinfo->gen <= 9 &&
>            p->nr_insn > 1 &&
>            brw_inst_opcode(devinfo, brw_last_inst) == BRW_OPCODE_MATH &&
>            brw_inst_math_function(devinfo, brw_last_inst) == BRW_MATH_FUNCTION_POW &&
> -- 
> 2.13.5
>
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