[Mesa-dev] [PATCH 03/17] ac/surface: only set the display flag for 4-channel images

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/amd/common/ac_surface.c                    | 3 ++-
 src/amd/common/ac_surface.h                    | 1 +
 src/amd/vulkan/radv_image.c                    | 1 +
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 1 +
 4 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 2b20a553d51..770e522acbb 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -414,21 +414,22 @@ static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
 	assert(index < 16);
 	return index;
 }
 
 static bool get_display_flag(const struct ac_surf_config *config,
 			     const struct radeon_surf *surf)
 {
 	return surf->flags & RADEON_SURF_SCANOUT &&
 	       !(surf->flags & RADEON_SURF_FMASK) &&
 	       config->info.samples <= 1 &&
-	       surf->bpe >= 4 && surf->bpe <= 8;
+	       surf->bpe >= 4 && surf->bpe <= 8 &&
+	       config->info.num_channels == 4;
 }
 
 /**
  * This must be called after the first level is computed.
  *
  * Copy surface-global settings like pipe/bank config from level 0 surface
  * computation, and compute tile swizzle.
  */
 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
 				 const struct radeon_info *info,
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 71f320af8ee..37df859e6de 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -212,20 +212,21 @@ struct radeon_surf {
         struct gfx9_surf_layout gfx9;
     } u;
 };
 
 struct ac_surf_info {
 	uint32_t width;
 	uint32_t height;
 	uint32_t depth;
 	uint8_t samples;
 	uint8_t levels;
+	uint8_t num_channels; /* heuristic for displayability */
 	uint16_t array_size;
 	uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */
 	uint32_t *fmask_surf_index; /* GFX9+ */
 };
 
 struct ac_surf_config {
 	struct ac_surf_info info;
 	unsigned is_3d : 1;
 	unsigned is_cube : 1;
 };
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index dd3189c67d0..ef6f1072abd 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -919,20 +919,21 @@ radv_image_create(VkDevice _device,
 	if (!image)
 		return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 
 	image->type = pCreateInfo->imageType;
 	image->info.width = pCreateInfo->extent.width;
 	image->info.height = pCreateInfo->extent.height;
 	image->info.depth = pCreateInfo->extent.depth;
 	image->info.samples = pCreateInfo->samples;
 	image->info.array_size = pCreateInfo->arrayLayers;
 	image->info.levels = pCreateInfo->mipLevels;
+	image->info.num_channels = 4; /* TODO: set this correctly */
 
 	image->vk_format = pCreateInfo->format;
 	image->tiling = pCreateInfo->tiling;
 	image->usage = pCreateInfo->usage;
 	image->flags = pCreateInfo->flags;
 
 	image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
 	if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
 		for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
 			if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHR)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index fc5c9d5a127..b5a1ebb1628 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -79,20 +79,21 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
    surf->flags = flags;
 
    struct ac_surf_config config;
 
    config.info.width = tex->width0;
    config.info.height = tex->height0;
    config.info.depth = tex->depth0;
    config.info.array_size = tex->array_size;
    config.info.samples = tex->nr_samples;
    config.info.levels = tex->last_level + 1;
+   config.info.num_channels = util_format_get_nr_components(tex->format);
    config.is_3d = !!(tex->target == PIPE_TEXTURE_3D);
    config.is_cube = !!(tex->target == PIPE_TEXTURE_CUBE);
 
    /* Use different surface counters for color and FMASK, so that MSAA MRTs
     * always use consecutive surface indices when FMASK is allocated between
     * them.
     */
    if (flags & RADEON_SURF_FMASK)
       config.info.surf_index = &ws->surf_index_fmask;
    else if (!(flags & RADEON_SURF_Z_OR_SBUFFER))
-- 
2.15.1