[Mesa-dev] [PATCH 13/17] radeonsi: clear up controlling the DCC MSAA level of support

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeon/r600_texture.c | 4 ++--
 src/gallium/drivers/radeonsi/si_pipe.c    | 2 ++
 src/gallium/drivers/radeonsi/si_pipe.h    | 1 +
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 8d4d771155a..a94203e26b4 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -260,23 +260,23 @@ static int r600_init_surface(struct si_screen *sscreen,
 			flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
 		}
 
 		if (is_stencil)
 			flags |= RADEON_SURF_SBUFFER;
 	}
 
 	if (sscreen->info.chip_class >= VI &&
 	    (ptex->flags & R600_RESOURCE_FLAG_DISABLE_DCC ||
 	     ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT ||
-	     /* DCC MSAA array textures are disallowed due to incomplete clear impl. */
 	     (ptex->nr_samples >= 2 &&
-	      (!sscreen->dcc_msaa_allowed || ptex->array_size > 1))))
+	      (!sscreen->dcc_msaa_allowed ||
+	       (!sscreen->dcc_msaa_array_allowed && ptex->array_size > 1)))))
 		flags |= RADEON_SURF_DISABLE_DCC;
 
 	if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
 		/* This should catch bugs in gallium users setting incorrect flags. */
 		assert(ptex->nr_samples <= 1 &&
 		       ptex->array_size == 1 &&
 		       ptex->depth0 == 1 &&
 		       ptex->last_level == 0 &&
 		       !(flags & RADEON_SURF_Z_OR_SBUFFER));
 
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index cbc8689044b..363979dc98c 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -865,20 +865,22 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
 			!(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
 			(sscreen->info.family == CHIP_STONEY ||
 			 sscreen->info.family == CHIP_VEGA12 ||
 			 sscreen->info.family == CHIP_RAVEN);
 	}
 
 	sscreen->dcc_msaa_allowed =
 		!(sscreen->debug_flags & DBG(NO_DCC_MSAA)) &&
 		(sscreen->debug_flags & DBG(DCC_MSAA) ||
 		 sscreen->info.chip_class == VI);
+	/* DCC MSAA array textures are disallowed due to incomplete clear impl. */
+	sscreen->dcc_msaa_array_allowed = false;
 
 	sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= VI;
 
 	(void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
 	sscreen->use_monolithic_shaders =
 		(sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
 
 	sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
 					    SI_CONTEXT_INV_VMEM_L1;
 	if (sscreen->info.chip_class <= VI) {
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index e65c946d186..bb1aebdda42 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -119,20 +119,21 @@ struct si_screen {
 	bool				dpbb_allowed;
 	bool				dfsm_allowed;
 	bool				llvm_has_working_vgpr_indexing;
 
 	/* Whether shaders are monolithic (1-part) or separate (3-part). */
 	bool				use_monolithic_shaders;
 	bool				record_llvm_ir;
 	bool				has_rbplus;     /* if RB+ registers exist */
 	bool				rbplus_allowed; /* if RB+ is allowed */
 	bool				dcc_msaa_allowed;
+	bool				dcc_msaa_array_allowed;
 	bool				cpdma_prefetch_writes_memory;
 
 	struct slab_parent_pool		pool_transfers;
 
 	/* Texture filter settings. */
 	int				force_aniso; /* -1 = disabled */
 
 	/* Auxiliary context. Mainly used to initialize resources.
 	 * It must be locked prior to using and flushed before unlocking. */
 	struct pipe_context		*aux_context;
-- 
2.15.1