[Mesa-dev] [PATCH 8/9] radeonsi: use r600_resource() typecast helper
Marek Olšák
maraeo at gmail.com
Tue Apr 17 00:42:10 UTC 2018
From: Marek Olšák <marek.olsak at amd.com>
---
src/gallium/drivers/radeon/radeon_vcn_dec.c | 4 ++--
src/gallium/drivers/radeon/radeon_video.c | 5 ++--
src/gallium/drivers/radeonsi/si_buffer.c | 20 ++++++++++------
src/gallium/drivers/radeonsi/si_clear.c | 2 +-
src/gallium/drivers/radeonsi/si_compute.c | 14 +++++------
src/gallium/drivers/radeonsi/si_cp_dma.c | 6 ++---
src/gallium/drivers/radeonsi/si_descriptors.c | 24 +++++++++----------
src/gallium/drivers/radeonsi/si_dma.c | 4 ++--
src/gallium/drivers/radeonsi/si_gfx_cs.c | 5 ++--
src/gallium/drivers/radeonsi/si_pipe.c | 18 +++++++-------
src/gallium/drivers/radeonsi/si_pipe.h | 19 +++++++--------
src/gallium/drivers/radeonsi/si_pm4.c | 2 +-
src/gallium/drivers/radeonsi/si_query.c | 6 ++---
src/gallium/drivers/radeonsi/si_shader.c | 3 +--
src/gallium/drivers/radeonsi/si_state.c | 2 +-
src/gallium/drivers/radeonsi/si_state_draw.c | 6 ++---
.../drivers/radeonsi/si_state_shaders.c | 8 +++----
.../drivers/radeonsi/si_state_streamout.c | 4 ++--
src/gallium/drivers/radeonsi/si_texture.c | 6 ++---
19 files changed, 80 insertions(+), 78 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 046b371384a..46ad2853f1c 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -846,22 +846,22 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
index->filled = 0;
decode->stream_type = dec->stream_type;
decode->decode_flags = 0x1;
decode->width_in_samples = dec->base.width;
decode->height_in_samples = dec->base.height;
decode->bsd_size = align(dec->bs_size, 128);
decode->dpb_size = dec->dpb.res->buf->size;
decode->dt_size =
- ((struct r600_resource *)((struct vl_video_buffer *)target)->resources[0])->buf->size +
- ((struct r600_resource *)((struct vl_video_buffer *)target)->resources[1])->buf->size;
+ r600_resource(((struct vl_video_buffer *)target)->resources[0])->buf->size +
+ r600_resource(((struct vl_video_buffer *)target)->resources[1])->buf->size;
decode->sct_size = 0;
decode->sc_coeff_size = 0;
decode->sw_ctxt_size = RDECODE_SESSION_CONTEXT_SIZE;
decode->db_pitch = align(dec->base.width, 32);
decode->db_surf_tile_config = 0;
decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w;
decode->dt_uv_pitch = decode->dt_pitch / 2;
diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c
index a2947df9590..f59b44736aa 100644
--- a/src/gallium/drivers/radeon/radeon_video.c
+++ b/src/gallium/drivers/radeon/radeon_video.c
@@ -56,23 +56,22 @@ unsigned si_vid_alloc_stream_handle()
bool si_vid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer,
unsigned size, unsigned usage)
{
memset(buffer, 0, sizeof(*buffer));
buffer->usage = usage;
/* Hardware buffer placement restrictions require the kernel to be
* able to move buffers around individually, so request a
* non-sub-allocated buffer.
*/
- buffer->res = (struct r600_resource *)
- pipe_buffer_create(screen, PIPE_BIND_SHARED,
- usage, size);
+ buffer->res = r600_resource(pipe_buffer_create(screen, PIPE_BIND_SHARED,
+ usage, size));
return buffer->res != NULL;
}
/* destroy a buffer */
void si_vid_destroy_buffer(struct rvid_buffer *buffer)
{
r600_resource_reference(&buffer->res, NULL);
}
diff --git a/src/gallium/drivers/radeonsi/si_buffer.c b/src/gallium/drivers/radeonsi/si_buffer.c
index a0855db571f..504e0c723dc 100644
--- a/src/gallium/drivers/radeonsi/si_buffer.c
+++ b/src/gallium/drivers/radeonsi/si_buffer.c
@@ -471,23 +471,23 @@ static void *si_buffer_transfer_map(struct pipe_context *ctx,
}
/* Use a staging buffer in cached GTT for reads. */
else if (((usage & PIPE_TRANSFER_READ) &&
!(usage & PIPE_TRANSFER_PERSISTENT) &&
(rbuffer->domains & RADEON_DOMAIN_VRAM ||
rbuffer->flags & RADEON_FLAG_GTT_WC)) ||
(rbuffer->flags & RADEON_FLAG_SPARSE)) {
struct r600_resource *staging;
assert(!(usage & TC_TRANSFER_MAP_THREADED_UNSYNC));
- staging = (struct r600_resource*) pipe_buffer_create(
+ staging = r600_resource(pipe_buffer_create(
ctx->screen, 0, PIPE_USAGE_STAGING,
- box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT));
+ box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT)));
if (staging) {
/* Copy the VRAM buffer to the staging buffer. */
sctx->dma_copy(ctx, &staging->b.b, 0,
box->x % SI_MAP_BUFFER_ALIGNMENT,
0, 0, resource, 0, box);
data = si_buffer_map_sync_with_rings(sctx, staging,
usage & ~PIPE_TRANSFER_UNSYNCHRONIZED);
if (!data) {
r600_resource_reference(&staging, NULL);
@@ -641,41 +641,47 @@ static struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
rbuffer->flags |= RADEON_FLAG_SPARSE;
if (!si_alloc_resource(sscreen, rbuffer)) {
FREE(rbuffer);
return NULL;
}
return &rbuffer->b.b;
}
-struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
- unsigned flags,
- unsigned usage,
- unsigned size,
- unsigned alignment)
+struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
+ unsigned flags, unsigned usage,
+ unsigned size, unsigned alignment)
{
struct pipe_resource buffer;
memset(&buffer, 0, sizeof buffer);
buffer.target = PIPE_BUFFER;
buffer.format = PIPE_FORMAT_R8_UNORM;
buffer.bind = 0;
buffer.usage = usage;
buffer.flags = flags;
buffer.width0 = size;
buffer.height0 = 1;
buffer.depth0 = 1;
buffer.array_size = 1;
return si_buffer_create(screen, &buffer, alignment);
}
+struct r600_resource *si_aligned_buffer_create(struct pipe_screen *screen,
+ unsigned flags, unsigned usage,
+ unsigned size, unsigned alignment)
+{
+ return r600_resource(pipe_aligned_buffer_create(screen, flags, usage,
+ size, alignment));
+}
+
static struct pipe_resource *
si_buffer_from_user_memory(struct pipe_screen *screen,
const struct pipe_resource *templ,
void *user_memory)
{
struct si_screen *sscreen = (struct si_screen*)screen;
struct radeon_winsys *ws = sscreen->ws;
struct r600_resource *rbuffer = si_alloc_buffer_struct(screen, templ);
rbuffer->domains = RADEON_DOMAIN_GTT;
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index b8047c4d532..d25e2c713f6 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -39,21 +39,21 @@ static void si_alloc_separate_cmask(struct si_screen *sscreen,
{
if (rtex->cmask_buffer)
return;
assert(rtex->cmask.size == 0);
si_texture_get_cmask_info(sscreen, rtex, &rtex->cmask);
if (!rtex->cmask.size)
return;
- rtex->cmask_buffer = (struct r600_resource *)
+ rtex->cmask_buffer =
si_aligned_buffer_create(&sscreen->b,
SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
rtex->cmask.size,
rtex->cmask.alignment);
if (rtex->cmask_buffer == NULL) {
rtex->cmask.size = 0;
return;
}
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index f77367aef7f..69c3dce0124 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -349,25 +349,25 @@ static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
{
uint64_t scratch_bo_size, scratch_needed;
scratch_bo_size = 0;
scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
if (sctx->compute_scratch_buffer)
scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
if (scratch_bo_size < scratch_needed) {
r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
- sctx->compute_scratch_buffer = (struct r600_resource*)
+ sctx->compute_scratch_buffer =
si_aligned_buffer_create(&sctx->screen->b,
- SI_RESOURCE_FLAG_UNMAPPABLE,
- PIPE_USAGE_DEFAULT,
- scratch_needed, 256);
+ SI_RESOURCE_FLAG_UNMAPPABLE,
+ PIPE_USAGE_DEFAULT,
+ scratch_needed, 256);
if (!sctx->compute_scratch_buffer)
return false;
}
if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
si_shader_apply_scratch_relocs(shader, scratch_va);
@@ -696,21 +696,21 @@ static void si_setup_tgsi_grid(struct si_context *sctx,
/* 12 bytes = 3 dwords. */
12 * program->uses_grid_size;
if (info->indirect) {
if (program->uses_grid_size) {
uint64_t base_va = r600_resource(info->indirect)->gpu_address;
uint64_t va = base_va + info->indirect_offset;
int i;
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
- (struct r600_resource *)info->indirect,
+ r600_resource(info->indirect),
RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
for (i = 0; i < 3; ++i) {
radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
COPY_DATA_DST_SEL(COPY_DATA_REG));
radeon_emit(cs, (va + 4 * i));
radeon_emit(cs, (va + 4 * i) >> 32);
radeon_emit(cs, (grid_size_reg >> 2) + i);
radeon_emit(cs, 0);
@@ -767,21 +767,21 @@ static void si_emit_dispatch_packets(struct si_context *sctx,
S_00B800_COMPUTE_SHADER_EN(1) |
S_00B800_FORCE_START_AT_000(1) |
/* If the KMD allows it (there is a KMD hw register for it),
* allow launching waves out-of-order. (same as Vulkan) */
S_00B800_ORDER_MODE(sctx->chip_class >= CIK);
if (info->indirect) {
uint64_t base_va = r600_resource(info->indirect)->gpu_address;
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
- (struct r600_resource *)info->indirect,
+ r600_resource(info->indirect),
RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
PKT3_SHADER_TYPE_S(1));
radeon_emit(cs, 1);
radeon_emit(cs, base_va);
radeon_emit(cs, base_va >> 32);
radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
PKT3_SHADER_TYPE_S(1));
@@ -870,21 +870,21 @@ static void si_launch_grid(
if ((program->input_size ||
program->ir_type == PIPE_SHADER_IR_NATIVE) &&
unlikely(!si_upload_compute_input(sctx, code_object, info))) {
return;
}
/* Global buffers */
for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
struct r600_resource *buffer =
- (struct r600_resource*)program->global_buffers[i];
+ r600_resource(program->global_buffers[i]);
if (!buffer) {
continue;
}
radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer,
RADEON_USAGE_READWRITE,
RADEON_PRIO_COMPUTE_GLOBAL);
}
if (program->ir_type != PIPE_SHADER_IR_NATIVE)
si_setup_tgsi_grid(sctx, info);
diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index db9cb0b5346..b3621f794f5 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -179,25 +179,25 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst
if (src)
si_context_add_resource_size(sctx, src);
}
if (!(user_flags & SI_CPDMA_SKIP_CHECK_CS_SPACE))
si_need_gfx_cs_space(sctx);
/* This must be done after need_cs_space. */
if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
- (struct r600_resource*)dst,
+ r600_resource(dst),
RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
if (src)
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
- (struct r600_resource*)src,
+ r600_resource(src),
RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
}
/* Flush the caches for the first copy only.
* Also wait for the previous CP DMA operations.
*/
if (!(user_flags & SI_CPDMA_SKIP_GFX_SYNC) && sctx->flags)
si_emit_cache_flush(sctx);
if (!(user_flags & SI_CPDMA_SKIP_SYNC_BEFORE) && *is_first)
@@ -373,21 +373,21 @@ static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size,
unsigned scratch_size = SI_CPDMA_ALIGNMENT * 2;
assert(size < SI_CPDMA_ALIGNMENT);
/* Use the scratch buffer as the dummy buffer. The 3D engine should be
* idle at this point.
*/
if (!sctx->scratch_buffer ||
sctx->scratch_buffer->b.b.width0 < scratch_size) {
r600_resource_reference(&sctx->scratch_buffer, NULL);
- sctx->scratch_buffer = (struct r600_resource*)
+ sctx->scratch_buffer =
si_aligned_buffer_create(&sctx->screen->b,
SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
scratch_size, 256);
if (!sctx->scratch_buffer)
return;
si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
}
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index a030cbe8229..6771b62a9fb 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -255,21 +255,21 @@ static void si_sampler_view_add_buffer(struct si_context *sctx,
if (!resource)
return;
if (resource->target != PIPE_BUFFER) {
struct r600_texture *tex = (struct r600_texture*)resource;
if (tex->is_depth && !si_can_sample_zs(tex, is_stencil_sampler))
resource = &tex->flushed_depth_texture->resource.b.b;
}
- rres = (struct r600_resource*)resource;
+ rres = r600_resource(resource);
priority = si_get_sampler_view_priority(rres);
radeon_add_to_gfx_buffer_list_check_mem(sctx, rres, usage, priority,
check_mem);
if (resource->target == PIPE_BUFFER)
return;
/* Now add separate DCC or HTILE. */
rtex = (struct r600_texture*)resource;
@@ -666,38 +666,38 @@ si_disable_shader_image(struct si_context *ctx, unsigned shader, unsigned slot)
memcpy(descs->list + desc_slot*8, null_image_descriptor, 8*4);
images->enabled_mask &= ~(1u << slot);
ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
}
}
static void
si_mark_image_range_valid(const struct pipe_image_view *view)
{
- struct r600_resource *res = (struct r600_resource *)view->resource;
+ struct r600_resource *res = r600_resource(view->resource);
assert(res && res->b.b.target == PIPE_BUFFER);
util_range_add(&res->valid_buffer_range,
view->u.buf.offset,
view->u.buf.offset + view->u.buf.size);
}
static void si_set_shader_image_desc(struct si_context *ctx,
const struct pipe_image_view *view,
bool skip_decompress,
uint32_t *desc, uint32_t *fmask_desc)
{
struct si_screen *screen = ctx->screen;
struct r600_resource *res;
- res = (struct r600_resource *)view->resource;
+ res = r600_resource(view->resource);
if (res->b.b.target == PIPE_BUFFER) {
if (view->access & PIPE_IMAGE_ACCESS_WRITE)
si_mark_image_range_valid(view);
si_make_buffer_descriptor(screen, res,
view->format,
view->u.buf.offset,
view->u.buf.size, desc);
si_set_buf_desc_address(res, view->u.buf.offset, desc + 4);
@@ -779,21 +779,21 @@ static void si_set_shader_image(struct si_context *ctx,
struct si_descriptors *descs = si_sampler_and_image_descriptors(ctx, shader);
struct r600_resource *res;
unsigned desc_slot = si_get_image_slot(slot);
uint32_t *desc = descs->list + desc_slot * 8;
if (!view || !view->resource) {
si_disable_shader_image(ctx, shader, slot);
return;
}
- res = (struct r600_resource *)view->resource;
+ res = r600_resource(view->resource);
if (&images->views[slot] != view)
util_copy_image_view(&images->views[slot], view);
si_set_shader_image_desc(ctx, view, skip_decompress, desc, NULL);
if (res->b.b.target == PIPE_BUFFER) {
images->needs_color_decompress_mask &= ~(1 << slot);
res->bind_history |= PIPE_BIND_SHADER_IMAGE;
} else {
@@ -1070,21 +1070,21 @@ static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
for (i = 0; i < count; i++) {
int vb = sctx->vertex_elements->vertex_buffer_index[i];
if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
continue;
if (!sctx->vertex_buffer[vb].buffer.resource)
continue;
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
- (struct r600_resource*)sctx->vertex_buffer[vb].buffer.resource,
+ r600_resource(sctx->vertex_buffer[vb].buffer.resource),
RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
}
if (!sctx->vb_descriptors_buffer)
return;
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
sctx->vb_descriptors_buffer, RADEON_USAGE_READ,
RADEON_PRIO_DESCRIPTORS);
}
@@ -1130,21 +1130,21 @@ bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
assert(count <= SI_MAX_ATTRIBS);
for (i = 0; i < count; i++) {
struct pipe_vertex_buffer *vb;
struct r600_resource *rbuffer;
unsigned vbo_index = velems->vertex_buffer_index[i];
uint32_t *desc = &ptr[i*4];
vb = &sctx->vertex_buffer[vbo_index];
- rbuffer = (struct r600_resource*)vb->buffer.resource;
+ rbuffer = r600_resource(vb->buffer.resource);
if (!rbuffer) {
memset(desc, 0, 16);
continue;
}
int64_t offset = (int64_t)((int)vb->buffer_offset) +
velems->src_offset[i];
uint64_t va = rbuffer->gpu_address + offset;
int64_t num_records = (int64_t)rbuffer->b.b.width0 - offset;
@@ -1156,21 +1156,21 @@ bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
assert(num_records >= 0 && num_records <= UINT_MAX);
desc[0] = va;
desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
S_008F04_STRIDE(vb->stride);
desc[2] = num_records;
desc[3] = velems->rsrc_word3[i];
if (first_vb_use_mask & (1 << i)) {
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
- (struct r600_resource*)vb->buffer.resource,
+ r600_resource(vb->buffer.resource),
RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
}
}
/* Don't flush the const cache. It would have a very negative effect
* on performance (confirmed by testing). New descriptors are always
* uploaded to a fresh new buffer, so I don't think flushing the const
* cache is needed. */
si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
sctx->vertex_buffers_dirty = false;
@@ -1255,21 +1255,21 @@ static void si_set_constant_buffer(struct si_context *sctx,
desc[2] = input->buffer_size;
desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
buffers->buffers[slot] = buffer;
radeon_add_to_gfx_buffer_list_check_mem(sctx,
- (struct r600_resource*)buffer,
+ r600_resource(buffer),
buffers->shader_usage_constbuf,
buffers->priority_constbuf, true);
buffers->enabled_mask |= 1u << slot;
} else {
/* Clear the descriptor. */
memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
buffers->enabled_mask &= ~(1u << slot);
}
sctx->descriptors_dirty |= 1u << descriptors_idx;
@@ -1337,21 +1337,21 @@ static void si_set_shader_buffers(struct pipe_context *ctx,
if (!sbuffer || !sbuffer->buffer) {
pipe_resource_reference(&buffers->buffers[slot], NULL);
memset(desc, 0, sizeof(uint32_t) * 4);
buffers->enabled_mask &= ~(1u << slot);
sctx->descriptors_dirty |=
1u << si_const_and_shader_buffer_descriptors_idx(shader);
continue;
}
- buf = (struct r600_resource *)sbuffer->buffer;
+ buf = r600_resource(sbuffer->buffer);
va = buf->gpu_address + sbuffer->buffer_offset;
desc[0] = va;
desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
S_008F04_STRIDE(0);
desc[2] = sbuffer->buffer_size;
desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
@@ -1467,21 +1467,21 @@ void si_set_ring_buffer(struct si_context *sctx, uint slot,
S_008F0C_INDEX_STRIDE(index_stride) |
S_008F0C_ADD_TID_ENABLE(add_tid);
if (sctx->chip_class >= GFX9)
assert(!swizzle || element_size == 1); /* always 4 bytes on GFX9 */
else
desc[3] |= S_008F0C_ELEMENT_SIZE(element_size);
pipe_resource_reference(&buffers->buffers[slot], buffer);
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
- (struct r600_resource*)buffer,
+ r600_resource(buffer),
buffers->shader_usage, buffers->priority);
buffers->enabled_mask |= 1u << slot;
} else {
/* Clear the descriptor. */
memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
buffers->enabled_mask &= ~(1u << slot);
}
sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
}
@@ -1592,21 +1592,21 @@ static void si_reset_buffer_resources(struct si_context *sctx,
unsigned mask = buffers->enabled_mask & slot_mask;
while (mask) {
unsigned i = u_bit_scan(&mask);
if (buffers->buffers[i] == buf) {
si_desc_reset_buffer_offset(descs->list + i*4,
old_va, buf);
sctx->descriptors_dirty |= 1u << descriptors_idx;
radeon_add_to_gfx_buffer_list_check_mem(sctx,
- (struct r600_resource *)buf,
+ r600_resource(buf),
usage, priority, true);
}
}
}
/* Update all resource bindings where the buffer is bound, including
* all resource descriptors. This is invalidate_buffer without
* the invalidation. */
void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf,
uint64_t old_va)
@@ -2562,21 +2562,21 @@ static void si_make_image_handle_resident(struct pipe_context *ctx,
struct r600_resource *res;
struct hash_entry *entry;
entry = _mesa_hash_table_search(sctx->img_handles,
(void *)(uintptr_t)handle);
if (!entry)
return;
img_handle = (struct si_image_handle *)entry->data;
view = &img_handle->view;
- res = (struct r600_resource *)view->resource;
+ res = r600_resource(view->resource);
if (resident) {
if (res->b.b.target != PIPE_BUFFER) {
struct r600_texture *rtex = (struct r600_texture *)res;
unsigned level = view->u.tex.level;
if (color_needs_decompression(rtex)) {
util_dynarray_append(
&sctx->resident_img_needs_color_decompress,
struct si_image_handle *,
diff --git a/src/gallium/drivers/radeonsi/si_dma.c b/src/gallium/drivers/radeonsi/si_dma.c
index e3b5bb46208..909c301d9f8 100644
--- a/src/gallium/drivers/radeonsi/si_dma.c
+++ b/src/gallium/drivers/radeonsi/si_dma.c
@@ -30,22 +30,22 @@
static void si_dma_copy_buffer(struct si_context *ctx,
struct pipe_resource *dst,
struct pipe_resource *src,
uint64_t dst_offset,
uint64_t src_offset,
uint64_t size)
{
struct radeon_winsys_cs *cs = ctx->dma_cs;
unsigned i, ncopy, count, max_size, sub_cmd, shift;
- struct r600_resource *rdst = (struct r600_resource*)dst;
- struct r600_resource *rsrc = (struct r600_resource*)src;
+ struct r600_resource *rdst = r600_resource(dst);
+ struct r600_resource *rsrc = r600_resource(src);
/* Mark the buffer range of destination as valid (initialized),
* so that transfer_map knows it should wait for the GPU when mapping
* that range. */
util_range_add(&rdst->valid_buffer_range, dst_offset,
dst_offset + size);
dst_offset += rdst->gpu_address;
src_offset += rsrc->gpu_address;
diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c
index 1358010c63c..0af16dd3474 100644
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -172,23 +172,22 @@ static void si_begin_gfx_cs_debug(struct si_context *ctx)
{
static const uint32_t zeros[1];
assert(!ctx->current_saved_cs);
ctx->current_saved_cs = calloc(1, sizeof(*ctx->current_saved_cs));
if (!ctx->current_saved_cs)
return;
pipe_reference_init(&ctx->current_saved_cs->reference, 1);
- ctx->current_saved_cs->trace_buf = (struct r600_resource*)
- pipe_buffer_create(ctx->b.screen, 0,
- PIPE_USAGE_STAGING, 8);
+ ctx->current_saved_cs->trace_buf = r600_resource(
+ pipe_buffer_create(ctx->b.screen, 0, PIPE_USAGE_STAGING, 8));
if (!ctx->current_saved_cs->trace_buf) {
free(ctx->current_saved_cs);
ctx->current_saved_cs = NULL;
return;
}
pipe_buffer_write_nooverlap(&ctx->b, &ctx->current_saved_cs->trace_buf->b.b,
0, sizeof(zeros), zeros);
ctx->current_saved_cs->trace_id = 0;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index abe7dd51eb4..3de843af11c 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -360,23 +360,23 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
}
sctx->b.set_device_reset_callback = si_set_device_reset_callback;
si_init_context_texture_functions(sctx);
si_init_query_functions(sctx);
if (sctx->chip_class == CIK ||
sctx->chip_class == VI ||
sctx->chip_class == GFX9) {
- sctx->eop_bug_scratch = (struct r600_resource*)
- pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
- 16 * sscreen->info.num_render_backends);
+ sctx->eop_bug_scratch = r600_resource(
+ pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
+ 16 * sscreen->info.num_render_backends));
if (!sctx->eop_bug_scratch)
goto fail;
}
sctx->allocator_zeroed_memory =
u_suballocator_create(&sctx->b, sscreen->info.gart_page_size,
0, PIPE_USAGE_DEFAULT, 0, true);
if (!sctx->allocator_zeroed_memory)
goto fail;
@@ -431,24 +431,24 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
sctx->gfx_cs = ws->cs_create(sctx->ctx, RING_GFX,
(void*)si_flush_gfx_cs, sctx);
/* Border colors. */
sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
sizeof(*sctx->border_color_table));
if (!sctx->border_color_table)
goto fail;
- sctx->border_color_buffer = (struct r600_resource*)
+ sctx->border_color_buffer = r600_resource(
pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
SI_MAX_BORDER_COLORS *
- sizeof(*sctx->border_color_table));
+ sizeof(*sctx->border_color_table)));
if (!sctx->border_color_buffer)
goto fail;
sctx->border_color_map =
ws->buffer_map(sctx->border_color_buffer->buf,
NULL, PIPE_TRANSFER_WRITE);
if (!sctx->border_color_map)
goto fail;
si_init_all_descriptors(sctx);
@@ -471,42 +471,42 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
goto fail;
sctx->blitter->draw_rectangle = si_draw_rectangle;
sctx->blitter->skip_viewport_restore = true;
sctx->sample_mask = 0xffff;
/* these must be last */
si_begin_new_gfx_cs(sctx);
if (sctx->chip_class >= GFX9) {
- sctx->wait_mem_scratch = (struct r600_resource*)
- pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4);
+ sctx->wait_mem_scratch = r600_resource(
+ pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4));
if (!sctx->wait_mem_scratch)
goto fail;
/* Initialize the memory. */
struct radeon_winsys_cs *cs = sctx->gfx_cs;
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
S_370_WR_CONFIRM(1) |
S_370_ENGINE_SEL(V_370_ME));
radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32);
radeon_emit(cs, sctx->wait_mem_number);
}
/* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
* if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
if (sctx->chip_class == CIK) {
sctx->null_const_buf.buffer =
- si_aligned_buffer_create(screen,
- SI_RESOURCE_FLAG_32BIT,
+ pipe_aligned_buffer_create(screen,
+ SI_RESOURCE_FLAG_32BIT,
PIPE_USAGE_DEFAULT, 16,
sctx->screen->info.tcc_cache_line_size);
if (!sctx->null_const_buf.buffer)
goto fail;
sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
sctx->b.set_constant_buffer(&sctx->b, shader, i,
&sctx->null_const_buf);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index eef8e602fad..6da1d73d26d 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -1077,25 +1077,26 @@ bool si_rings_is_buffer_referenced(struct si_context *sctx,
struct pb_buffer *buf,
enum radeon_bo_usage usage);
void *si_buffer_map_sync_with_rings(struct si_context *sctx,
struct r600_resource *resource,
unsigned usage);
void si_init_resource_fields(struct si_screen *sscreen,
struct r600_resource *res,
uint64_t size, unsigned alignment);
bool si_alloc_resource(struct si_screen *sscreen,
struct r600_resource *res);
-struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
- unsigned flags,
- unsigned usage,
- unsigned size,
- unsigned alignment);
+struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
+ unsigned flags, unsigned usage,
+ unsigned size, unsigned alignment);
+struct r600_resource *si_aligned_buffer_create(struct pipe_screen *screen,
+ unsigned flags, unsigned usage,
+ unsigned size, unsigned alignment);
void si_replace_buffer_storage(struct pipe_context *ctx,
struct pipe_resource *dst,
struct pipe_resource *src);
void si_init_screen_buffer_functions(struct si_screen *sscreen);
void si_init_buffer_functions(struct si_context *sctx);
/* si_clear.c */
enum pipe_format si_simplify_cb_format(enum pipe_format format);
bool vi_alpha_is_on_msb(enum pipe_format format);
void vi_dcc_clear_level(struct si_context *sctx,
@@ -1309,26 +1310,24 @@ si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
{
if (stencil)
return rtex->surface.u.legacy.stencil_tiling_index[level];
else
return rtex->surface.u.legacy.tiling_index[level];
}
static inline void
si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
{
- struct r600_resource *res = (struct r600_resource *)r;
-
- if (res) {
+ if (r) {
/* Add memory usage for need_gfx_cs_space */
- sctx->vram += res->vram_usage;
- sctx->gtt += res->gart_usage;
+ sctx->vram += r600_resource(r)->vram_usage;
+ sctx->gtt += r600_resource(r)->gart_usage;
}
}
static inline void
si_invalidate_draw_sh_constants(struct si_context *sctx)
{
sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
}
static inline unsigned
diff --git a/src/gallium/drivers/radeonsi/si_pm4.c b/src/gallium/drivers/radeonsi/si_pm4.c
index d68a38375f5..4869d19e4d3 100644
--- a/src/gallium/drivers/radeonsi/si_pm4.c
+++ b/src/gallium/drivers/radeonsi/si_pm4.c
@@ -160,21 +160,21 @@ void si_pm4_upload_indirect_buffer(struct si_context *sctx,
/* only supported on CIK and later */
if (sctx->chip_class < CIK)
return;
assert(state->ndw);
assert(aligned_ndw <= SI_PM4_MAX_DW);
r600_resource_reference(&state->indirect_buffer, NULL);
/* TODO: this hangs with 1024 or higher alignment on GFX9. */
- state->indirect_buffer = (struct r600_resource*)
+ state->indirect_buffer =
si_aligned_buffer_create(screen, 0,
PIPE_USAGE_DEFAULT, aligned_ndw * 4,
256);
if (!state->indirect_buffer)
return;
/* Pad the IB to 8 DWs to meet CP fetch alignment requirements. */
if (sctx->screen->info.gfx_ib_pad_with_type2) {
for (int i = state->ndw; i < aligned_ndw; i++)
state->pm4[i] = 0x80000000; /* type2 nop packet */
diff --git a/src/gallium/drivers/radeonsi/si_query.c b/src/gallium/drivers/radeonsi/si_query.c
index d621f22f46b..7f32be39a16 100644
--- a/src/gallium/drivers/radeonsi/si_query.c
+++ b/src/gallium/drivers/radeonsi/si_query.c
@@ -523,23 +523,23 @@ void si_query_hw_destroy(struct si_screen *sscreen,
static struct r600_resource *si_new_query_buffer(struct si_screen *sscreen,
struct si_query_hw *query)
{
unsigned buf_size = MAX2(query->result_size,
sscreen->info.min_alloc_size);
/* Queries are normally read by the CPU after
* being written by the gpu, hence staging is probably a good
* usage pattern.
*/
- struct r600_resource *buf = (struct r600_resource*)
+ struct r600_resource *buf = r600_resource(
pipe_buffer_create(&sscreen->b, 0,
- PIPE_USAGE_STAGING, buf_size);
+ PIPE_USAGE_STAGING, buf_size));
if (!buf)
return NULL;
if (!query->ops->prepare_buffer(sscreen, query, buf)) {
r600_resource_reference(&buf, NULL);
return NULL;
}
return buf;
}
@@ -1735,21 +1735,21 @@ static void si_query_hw_get_result_resource(struct si_context *sctx,
ssbo[0].buffer = &qbuf->buf->b.b;
ssbo[0].buffer_offset = params.start_offset;
ssbo[0].buffer_size = qbuf->results_end - params.start_offset;
if (!qbuf->previous) {
ssbo[2].buffer = resource;
ssbo[2].buffer_offset = offset;
ssbo[2].buffer_size = 8;
- ((struct r600_resource *)resource)->TC_L2_dirty = true;
+ r600_resource(resource)->TC_L2_dirty = true;
}
sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, ssbo);
if (wait && qbuf == &query->buffer) {
uint64_t va;
/* Wait for result availability. Wait only for readiness
* of the last entry, since the fence writes should be
* serialized in the CP.
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 8c62d53e2ad..765daa52bcb 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -5344,22 +5344,21 @@ int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
unsigned char *ptr;
assert(!prolog || !prolog->rodata_size);
assert(!previous_stage || !previous_stage->rodata_size);
assert(!prolog2 || !prolog2->rodata_size);
assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
!mainb->rodata_size);
assert(!epilog || !epilog->rodata_size);
r600_resource_reference(&shader->bo, NULL);
- shader->bo = (struct r600_resource*)
- si_aligned_buffer_create(&sscreen->b,
+ shader->bo = si_aligned_buffer_create(&sscreen->b,
sscreen->cpdma_prefetch_writes_memory ?
0 : SI_RESOURCE_FLAG_READ_ONLY,
PIPE_USAGE_IMMUTABLE,
align(bo_size, SI_CPDMA_ALIGNMENT),
256);
if (!shader->bo)
return -ENOMEM;
/* Upload. */
ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index da254f2ba73..0f3d945dff4 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3845,21 +3845,21 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
if (state->format == PIPE_FORMAT_X24S8_UINT ||
state->format == PIPE_FORMAT_S8X24_UINT ||
state->format == PIPE_FORMAT_X32_S8X24_UINT ||
state->format == PIPE_FORMAT_S8_UINT)
view->is_stencil_sampler = true;
/* Buffer resource. */
if (texture->target == PIPE_BUFFER) {
si_make_buffer_descriptor(sctx->screen,
- (struct r600_resource *)texture,
+ r600_resource(texture),
state->format,
state->u.buf.offset,
state->u.buf.size,
view->state);
return &view->base;
}
state_swizzle[0] = state->swizzle_r;
state_swizzle[1] = state->swizzle_g;
state_swizzle[2] = state->swizzle_b;
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 9b7a4869ba5..c6e720fd70e 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -712,21 +712,21 @@ static void si_emit_draw_packets(struct si_context *sctx,
}
sctx->last_index_size = index_size;
}
index_max_size = (indexbuf->width0 - index_offset) /
index_size;
index_va = r600_resource(indexbuf)->gpu_address + index_offset;
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
- (struct r600_resource *)indexbuf,
+ r600_resource(indexbuf),
RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
} else {
/* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
* so the state must be re-emitted before the next indexed draw.
*/
if (sctx->chip_class >= CIK)
sctx->last_index_size = -1;
}
if (indirect) {
@@ -735,21 +735,21 @@ static void si_emit_draw_packets(struct si_context *sctx,
assert(indirect_va % 8 == 0);
si_invalidate_draw_sh_constants(sctx);
radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
radeon_emit(cs, 1);
radeon_emit(cs, indirect_va);
radeon_emit(cs, indirect_va >> 32);
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
- (struct r600_resource *)indirect->buffer,
+ r600_resource(indirect->buffer),
RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
: V_0287F0_DI_SRC_SEL_AUTO_INDEX;
assert(indirect->offset % 4 == 0);
if (index_size) {
radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
radeon_emit(cs, index_va);
@@ -765,21 +765,21 @@ static void si_emit_draw_packets(struct si_context *sctx,
3, render_cond_bit));
radeon_emit(cs, indirect->offset);
radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
radeon_emit(cs, di_src_sel);
} else {
uint64_t count_va = 0;
if (indirect->indirect_draw_count) {
struct r600_resource *params_buf =
- (struct r600_resource *)indirect->indirect_draw_count;
+ r600_resource(indirect->indirect_draw_count);
radeon_add_to_buffer_list(
sctx, sctx->gfx_cs, params_buf,
RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
}
radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
PKT3_DRAW_INDIRECT_MULTI,
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 943c58cbf9f..f23ce098208 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -2713,32 +2713,32 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx)
bool update_gsvs = gsvs_ring_size &&
(!sctx->gsvs_ring ||
sctx->gsvs_ring->width0 < gsvs_ring_size);
if (!update_esgs && !update_gsvs)
return true;
if (update_esgs) {
pipe_resource_reference(&sctx->esgs_ring, NULL);
sctx->esgs_ring =
- si_aligned_buffer_create(sctx->b.screen,
+ pipe_aligned_buffer_create(sctx->b.screen,
SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
esgs_ring_size, alignment);
if (!sctx->esgs_ring)
return false;
}
if (update_gsvs) {
pipe_resource_reference(&sctx->gsvs_ring, NULL);
sctx->gsvs_ring =
- si_aligned_buffer_create(sctx->b.screen,
+ pipe_aligned_buffer_create(sctx->b.screen,
SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
gsvs_ring_size, alignment);
if (!sctx->gsvs_ring)
return false;
}
/* Create the "init_config_gs_rings" state. */
pm4 = CALLOC_STRUCT(si_pm4_state);
if (!pm4)
@@ -2965,21 +2965,21 @@ static bool si_update_spi_tmpring_size(struct si_context *sctx)
si_get_max_scratch_bytes_per_wave(sctx);
unsigned scratch_needed_size = scratch_bytes_per_wave *
sctx->scratch_waves;
unsigned spi_tmpring_size;
if (scratch_needed_size > 0) {
if (scratch_needed_size > current_scratch_buffer_size) {
/* Create a bigger scratch buffer */
r600_resource_reference(&sctx->scratch_buffer, NULL);
- sctx->scratch_buffer = (struct r600_resource*)
+ sctx->scratch_buffer =
si_aligned_buffer_create(&sctx->screen->b,
SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
scratch_needed_size, 256);
if (!sctx->scratch_buffer)
return false;
si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
si_context_add_resource_size(sctx,
&sctx->scratch_buffer->b.b);
@@ -3002,21 +3002,21 @@ static bool si_update_spi_tmpring_size(struct si_context *sctx)
return true;
}
static void si_init_tess_factor_ring(struct si_context *sctx)
{
assert(!sctx->tess_rings);
/* The address must be aligned to 2^19, because the shader only
* receives the high 13 bits.
*/
- sctx->tess_rings = si_aligned_buffer_create(sctx->b.screen,
+ sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
SI_RESOURCE_FLAG_32BIT,
PIPE_USAGE_DEFAULT,
sctx->screen->tess_offchip_ring_size +
sctx->screen->tess_factor_ring_size,
1 << 19);
if (!sctx->tess_rings)
return;
si_init_config_add_vgt_flush(sctx);
diff --git a/src/gallium/drivers/radeonsi/si_state_streamout.c b/src/gallium/drivers/radeonsi/si_state_streamout.c
index 3fd92889364..67fbb57a6cb 100644
--- a/src/gallium/drivers/radeonsi/si_state_streamout.c
+++ b/src/gallium/drivers/radeonsi/si_state_streamout.c
@@ -36,21 +36,21 @@ static inline void si_so_target_reference(struct si_streamout_target **dst,
}
static struct pipe_stream_output_target *
si_create_so_target(struct pipe_context *ctx,
struct pipe_resource *buffer,
unsigned buffer_offset,
unsigned buffer_size)
{
struct si_context *sctx = (struct si_context *)ctx;
struct si_streamout_target *t;
- struct r600_resource *rbuffer = (struct r600_resource*)buffer;
+ struct r600_resource *rbuffer = r600_resource(buffer);
t = CALLOC_STRUCT(si_streamout_target);
if (!t) {
return NULL;
}
u_suballocator_alloc(sctx->allocator_zeroed_memory, 4, 4,
&t->buf_filled_size_offset,
(struct pipe_resource**)&t->buf_filled_size);
if (!t->buf_filled_size) {
@@ -194,21 +194,21 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
/* Set the resource. */
pipe_resource_reference(&buffers->buffers[bufidx],
buffer);
radeon_add_to_gfx_buffer_list_check_mem(sctx,
- (struct r600_resource*)buffer,
+ r600_resource(buffer),
buffers->shader_usage,
RADEON_PRIO_SHADER_RW_BUFFER,
true);
r600_resource(buffer)->bind_history |= PIPE_BIND_STREAM_OUTPUT;
buffers->enabled_mask |= 1u << bufidx;
} else {
/* Clear the descriptor and unset the resource. */
memset(descs->list + bufidx*4, 0,
sizeof(uint32_t) * 4);
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index c39c594403e..7ab6699d96a 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -684,21 +684,21 @@ static void si_apply_opaque_metadata(struct si_screen *sscreen,
}
static boolean si_texture_get_handle(struct pipe_screen* screen,
struct pipe_context *ctx,
struct pipe_resource *resource,
struct winsys_handle *whandle,
unsigned usage)
{
struct si_screen *sscreen = (struct si_screen*)screen;
struct si_context *sctx;
- struct r600_resource *res = (struct r600_resource*)resource;
+ struct r600_resource *res = r600_resource(resource);
struct r600_texture *rtex = (struct r600_texture*)resource;
struct radeon_bo_metadata metadata;
bool update_metadata = false;
unsigned stride, offset, slice_size;
bool flush = false;
ctx = threaded_context_unwrap_sync(ctx);
sctx = (struct si_context*)(ctx ? ctx : sscreen->aux_context);
if (resource->target != PIPE_BUFFER) {
@@ -1785,21 +1785,21 @@ static void *si_texture_transfer_map(struct pipe_context *ctx,
level, level,
box->z, box->z + box->depth - 1,
0, 0);
offset = si_texture_get_offset(sctx->screen, staging_depth,
level, box,
&trans->b.b.stride,
&trans->b.b.layer_stride);
}
- trans->staging = (struct r600_resource*)staging_depth;
+ trans->staging = &staging_depth->resource;
buf = trans->staging;
} else if (use_staging_texture) {
struct pipe_resource resource;
struct r600_texture *staging;
si_init_temp_resource_from_box(&resource, texture, box, level,
SI_RESOURCE_FLAG_TRANSFER);
resource.usage = (usage & PIPE_TRANSFER_READ) ?
PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
@@ -2267,21 +2267,21 @@ void vi_separate_dcc_try_enable(struct si_context *sctx,
si_texture_discard_cmask(sctx->screen, tex);
/* Get a DCC buffer. */
if (tex->last_dcc_separate_buffer) {
assert(tex->dcc_gather_statistics);
assert(!tex->dcc_separate_buffer);
tex->dcc_separate_buffer = tex->last_dcc_separate_buffer;
tex->last_dcc_separate_buffer = NULL;
} else {
- tex->dcc_separate_buffer = (struct r600_resource*)
+ tex->dcc_separate_buffer =
si_aligned_buffer_create(sctx->b.screen,
SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
tex->surface.dcc_size,
tex->surface.dcc_alignment);
if (!tex->dcc_separate_buffer)
return;
}
/* dcc_offset is the absolute GPUVM address. */
--
2.17.0
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