[Mesa-dev] [PATCH 5/7] radeonsi: implement DCC fast clear swizzle constraints more accurately
Nicolai Hähnle
nhaehnle at gmail.com
Wed Apr 18 09:55:20 UTC 2018
On 17.04.2018 02:41, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> Reduce swizzle constraints to the ALPHA_IS_ON_MSB constraint and the clear
> value of 1.
>
> This significantly changes the DCC fast clear code, and fixes fast clear
> for RGB formats without alpha.
> ---
> src/gallium/drivers/radeonsi/si_clear.c | 94 ++++++++++++++++---------
> src/gallium/drivers/radeonsi/si_pipe.h | 2 +
> src/gallium/drivers/radeonsi/si_state.c | 4 +-
> 3 files changed, 65 insertions(+), 35 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
> index 7a8fdf59797..03cb08502ef 100644
> --- a/src/gallium/drivers/radeonsi/si_clear.c
> +++ b/src/gallium/drivers/radeonsi/si_clear.c
> @@ -86,69 +86,84 @@ static void si_set_clear_color(struct r600_texture *rtex,
> util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
> } else if (util_format_is_pure_sint(surface_format)) {
> util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
> } else {
> util_pack_color(color->f, surface_format, &uc);
> }
>
> memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
> }
>
> -static bool vi_get_fast_clear_parameters(enum pipe_format surface_format,
> +/** Linearize and convert luminace/intensity to red. */
> +enum pipe_format si_simplify_cb_format(enum pipe_format format)
> +{
> + format = util_format_linear(format);
> + format = util_format_luminance_to_red(format);
> + return util_format_intensity_to_red(format);
> +}
> +
> +bool vi_alpha_is_on_msb(enum pipe_format format)
> +{
> + format = si_simplify_cb_format(format);
> +
> + /* Formats with 3 channels can't have alpha. */
> + if (util_format_description(format)->nr_channels == 3)
> + return 1; /* same as xxxA; is any value OK here? */
Use true instead of 1 for the bool.
Apart from that,
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
> +
> + return si_translate_colorswap(format, false) <= 1;
> +}
> +
> +static bool vi_get_fast_clear_parameters(enum pipe_format base_format,
> + enum pipe_format surface_format,
> const union pipe_color_union *color,
> uint32_t* clear_value,
> bool *eliminate_needed)
> {
> /* If we want to clear without needing a fast clear eliminate step, we
> * can set color and alpha independently to 0 or 1 (or 0/max for integer
> * formats).
> */
> bool values[4] = {}; /* whether to clear to 0 or 1 */
> - int i;
> bool color_value = false; /* clear color to 0 or 1 */
> bool alpha_value = false; /* clear alpha to 0 or 1 */
> int alpha_channel; /* index of the alpha component */
> + bool has_color = false;
> + bool has_alpha = false;
>
> - /* Convert luminance to red. (the latter can't handle L8_SRGB,
> - * so convert to linear) */
> - surface_format = util_format_linear(surface_format);
> - surface_format = util_format_luminance_to_red(surface_format);
> -
> - const struct util_format_description *desc = util_format_description(surface_format);
> + const struct util_format_description *desc =
> + util_format_description(si_simplify_cb_format(surface_format));
>
> /* 128-bit fast clear with different R,G,B values is unsupported. */
> if (desc->block.bits == 128 &&
> (color->ui[0] != color->ui[1] ||
> color->ui[0] != color->ui[2]))
> return false;
>
> *eliminate_needed = true;
> *clear_value = 0x20202020U; /* use CB clear color registers */
>
> - if (surface_format == PIPE_FORMAT_R11G11B10_FLOAT ||
> - surface_format == PIPE_FORMAT_B5G6R5_UNORM ||
> - surface_format == PIPE_FORMAT_B5G6R5_SRGB ||
> - util_format_is_alpha(surface_format)) {
> - alpha_channel = -1;
> - } else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
> - if (si_translate_colorswap(surface_format, false) <= 1)
> - alpha_channel = desc->nr_channels - 1;
> - else
> - alpha_channel = 0;
> - } else
> + if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
> return true; /* need ELIMINATE_FAST_CLEAR */
>
> - for (i = 0; i < 4; ++i) {
> - int index = desc->swizzle[i] - PIPE_SWIZZLE_X;
> + bool base_alpha_is_on_msb = vi_alpha_is_on_msb(base_format);
> + bool surf_alpha_is_on_msb = vi_alpha_is_on_msb(surface_format);
> +
> + /* Formats with 3 channels can't have alpha. */
> + if (desc->nr_channels == 3)
> + alpha_channel = -1;
> + else if (surf_alpha_is_on_msb)
> + alpha_channel = desc->nr_channels - 1;
> + else
> + alpha_channel = 0;
>
> - if (desc->swizzle[i] < PIPE_SWIZZLE_X ||
> - desc->swizzle[i] > PIPE_SWIZZLE_W)
> + for (int i = 0; i < 4; ++i) {
> + if (desc->swizzle[i] >= PIPE_SWIZZLE_0)
> continue;
>
> if (desc->channel[i].pure_integer &&
> desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
> /* Use the maximum value for clamping the clear color. */
> int max = u_bit_consecutive(0, desc->channel[i].size - 1);
>
> values[i] = color->i[i] != 0;
> if (color->i[i] != 0 && MIN2(color->i[i], max) != max)
> return true; /* need ELIMINATE_FAST_CLEAR */
> @@ -159,32 +174,46 @@ static bool vi_get_fast_clear_parameters(enum pipe_format surface_format,
>
> values[i] = color->ui[i] != 0U;
> if (color->ui[i] != 0U && MIN2(color->ui[i], max) != max)
> return true; /* need ELIMINATE_FAST_CLEAR */
> } else {
> values[i] = color->f[i] != 0.0F;
> if (color->f[i] != 0.0F && color->f[i] != 1.0F)
> return true; /* need ELIMINATE_FAST_CLEAR */
> }
>
> - if (index == alpha_channel)
> + if (desc->swizzle[i] == alpha_channel) {
> alpha_value = values[i];
> - else
> + has_alpha = true;
> + } else {
> color_value = values[i];
> + has_color = true;
> + }
> }
>
> - for (int i = 0; i < 4; ++i)
> - if (values[i] != color_value &&
> - desc->swizzle[i] - PIPE_SWIZZLE_X != alpha_channel &&
> - desc->swizzle[i] >= PIPE_SWIZZLE_X &&
> - desc->swizzle[i] <= PIPE_SWIZZLE_W)
> - return true; /* need ELIMINATE_FAST_CLEAR */
> + /* If alpha isn't present, make it the same as color, and vice versa. */
> + if (!has_alpha)
> + alpha_value = color_value;
> + else if (!has_color)
> + color_value = alpha_value;
> +
> + if (color_value != alpha_value &&
> + base_alpha_is_on_msb != surf_alpha_is_on_msb)
> + return true; /* require ELIMINATE_FAST_CLEAR */
> +
> + /* Check if all color values are equal if they are present. */
> + for (int i = 0; i < 4; ++i) {
> + if (desc->swizzle[i] <= PIPE_SWIZZLE_W &&
> + desc->swizzle[i] != alpha_channel &&
> + values[i] != color_value)
> + return true; /* require ELIMINATE_FAST_CLEAR */
> + }
>
> /* This doesn't need ELIMINATE_FAST_CLEAR.
> * CB uses both the DCC clear codes and the CB clear color registers,
> * so they must match.
> */
> *eliminate_needed = false;
>
> if (color_value)
> *clear_value |= 0x80808080U;
> if (alpha_value)
> @@ -447,21 +476,22 @@ static void si_do_fast_color_clear(struct si_context *sctx,
> bool eliminate_needed;
>
> if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
> continue;
>
> /* This can only occur with MSAA. */
> if (sctx->chip_class == VI &&
> !tex->surface.u.legacy.level[level].dcc_fast_clear_size)
> continue;
>
> - if (!vi_get_fast_clear_parameters(fb->cbufs[i]->format,
> + if (!vi_get_fast_clear_parameters(tex->resource.b.b.format,
> + fb->cbufs[i]->format,
> color, &reset_value,
> &eliminate_needed))
> continue;
>
> if (eliminate_needed && too_small)
> continue;
>
> /* DCC fast clear with MSAA should clear CMASK to 0xC. */
> if (tex->resource.b.b.nr_samples >= 2 && tex->cmask.size) {
> /* TODO: This doesn't work with MSAA. */
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
> index f73e0d1aac3..24221d0a55a 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.h
> +++ b/src/gallium/drivers/radeonsi/si_pipe.h
> @@ -872,20 +872,22 @@ struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
> unsigned usage,
> unsigned size,
> unsigned alignment);
> void si_replace_buffer_storage(struct pipe_context *ctx,
> struct pipe_resource *dst,
> struct pipe_resource *src);
> void si_init_screen_buffer_functions(struct si_screen *sscreen);
> void si_init_buffer_functions(struct si_context *sctx);
>
> /* si_clear.c */
> +enum pipe_format si_simplify_cb_format(enum pipe_format format);
> +bool vi_alpha_is_on_msb(enum pipe_format format);
> void vi_dcc_clear_level(struct si_context *sctx,
> struct r600_texture *rtex,
> unsigned level, unsigned clear_value);
> void si_init_clear_functions(struct si_context *sctx);
>
> /* si_cp_dma.c */
> #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
> #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
> #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
> #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
> diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
> index 26f61afcab0..49110b292b9 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -3735,23 +3735,21 @@ si_make_texture_descriptor(struct si_screen *screen,
> state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
> util_logbase2(res->nr_samples) :
> tex->resource.b.b.last_level);
> } else {
> state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
> state[4] |= S_008F20_DEPTH(depth - 1);
> state[5] |= S_008F24_LAST_ARRAY(last_layer);
> }
>
> if (tex->dcc_offset) {
> - unsigned swap = si_translate_colorswap(pipe_format, false);
> -
> - state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
> + state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
> } else {
> /* The last dword is unused by hw. The shader uses it to clear
> * bits in the first dword of sampler state.
> */
> if (screen->info.chip_class <= CIK && res->nr_samples <= 1) {
> if (first_level == last_level)
> state[7] = C_008F30_MAX_ANISO_RATIO;
> else
> state[7] = 0xffffffff;
> }
>
--
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Aber vergiss niemals, wie sie sein sollte.
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