[Mesa-dev] [PATCH 1/7] ac/surface: handle DCC subresource fast clear restriction on VI

[Nicolai Hähnle]

On 18.04.2018 21:53, Marek Olšák wrote:
> On Wed, Apr 18, 2018 at 5:54 AM, Nicolai Hähnle <nhaehnle at gmail.com 
> <mailto:nhaehnle at gmail.com>> wrote:
> 
>     On 17.04.2018 02:41, Marek Olšák wrote:
> 
>         From: Marek Olšák <marek.olsak at amd.com <mailto:marek.olsak at amd.com>>
> 
>         ---
>            src/amd/common/ac_surface.c | 14 +++++++++++++-
>            1 file changed, 13 insertions(+), 1 deletion(-)
> 
>         diff --git a/src/amd/common/ac_surface.c
>         b/src/amd/common/ac_surface.c
>         index 7558dd91e34..c209b209da2 100644
>         --- a/src/amd/common/ac_surface.c
>         +++ b/src/amd/common/ac_surface.c
>         @@ -344,24 +344,36 @@ static int gfx6_compute_level(ADDR_HANDLE
>         addrlib,
>                          AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
>                          AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
>                          AddrDccIn->macroModeIndex =
>         AddrSurfInfoOut->macroModeIndex;
>                          ret = AddrComputeDccInfo(addrlib,
>                                                   AddrDccIn,
>                                                   AddrDccOut);
>                          if (ret == ADDR_OK) {
>                                  surf_level->dcc_offset = surf->dcc_size;
>         -                       surf_level->dcc_fast_clear_size =
>         AddrDccOut->dccFastClearSize;
>                                  surf->num_dcc_levels = level + 1;
>                                  surf->dcc_size = surf_level->dcc_offset
>         + AddrDccOut->dccRamSize;
>                                  surf->dcc_alignment =
>         MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
>         +
>         +                       /* If the DCC size of a subresource (1
>         mip level or 1 slice)
>         +                        * is not aligned, the DCC memory layout
>         is not contiguous for
>         +                        * that subresource, which means we
>         can't use fast clear.
>         +                        *
>         +                        * We only do fast clears for whole
>         mipmap levels. If we did
>         +                        * per-slice fast clears, the same
>         restriction would apply.
>         +                        * (i.e. only compute the slice size and
>         see if it's aligned)
>         +                        */
>         +                       if (level == config->info.levels - 1 ||
>         AddrDccOut->dccRamSizeAligned)
> 
> 
>     Are you sure that the last level is always okay? It seems possible
>     that the last and second-to-last level end up interleaved due to
>     swizzling.
> 
>     The catch is that you'd probably only ever notice this with a
>     truncated mip-tree.
> 
> 
> This condition was copied from amdvlk. I guess that if the 
> second-to-last level is unaligned, the last level would also be unaligned.

Agreed, but does that make it any better? If the last level is N, and 
both levels N and N-1 are unaligned, then this code will disable fast 
clear on level N-1 and enable it on level N. That seems wrong to me.


> We never use fast clear for non-zero level. For now, we only have to 
> make sure that level 0 is contiguous.

Okay, but that might change in the future.

Cheers,
Nicolai


> 
> Marek
> 


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