[Mesa-dev] [PATCH 2/2] spirv: convert the offset and count operands for bitfield ops to uint32
Samuel Iglesias Gonsálvez
siglesias at igalia.com
Thu Apr 26 09:24:46 UTC 2018
SPIR-V allows to define the shift operand for shift opcodes with
a bit-size different than 32 bits, but in NIR the opcodes have
that limitation. As agreed in the mailing list, this patch adds
a conversion to 32 bits to fix this.
For more info, see:
https://lists.freedesktop.org/archives/mesa-dev/2018-April/193026.html
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
---
src/compiler/spirv/vtn_alu.c | 48 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index 6f3b82cd5c3..a1654b20273 100644
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src/compiler/spirv/vtn_alu.c
@@ -640,6 +640,54 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
break;
}
+ case SpvOpBitFieldInsert: {
+ if (src[2]->bit_size != 32) {
+ /* Convert the Shift operand to 32 bits, which is the bitsize
+ * supported by the NIR instruction. See discussion here:
+ *
+ * https://lists.freedesktop.org/archives/mesa-dev/2018-April/193026.html
+ */
+ src[2] = nir_build_alu(&b->nb, nir_op_u2u32, src[2], NULL, NULL, NULL);
+ }
+ if (src[3]->bit_size != 32) {
+ /* Convert the Shift operand to 32 bits, which is the bitsize
+ * supported by the NIR instruction. See discussion here:
+ *
+ * https://lists.freedesktop.org/archives/mesa-dev/2018-April/193026.html
+ */
+ src[3] = nir_build_alu(&b->nb, nir_op_u2u32, src[3], NULL, NULL, NULL);
+ }
+ val->ssa->def = nir_build_alu(&b->nb, nir_op_bitfield_insert, src[0], src[1], src[2], src[3]);
+ break;
+ }
+
+ case SpvOpBitFieldSExtract:
+ case SpvOpBitFieldUExtract: {
+ bool swap;
+ unsigned src_bit_size = glsl_get_bit_size(vtn_src[0]->type);
+ unsigned dst_bit_size = glsl_get_bit_size(type);
+ nir_op op = vtn_nir_alu_op_for_spirv_opcode(b, opcode, &swap,
+ src_bit_size, dst_bit_size);
+ if (src[1]->bit_size != 32) {
+ /* Convert the Shift operand to 32 bits, which is the bitsize
+ * supported by the NIR instruction. See discussion here:
+ *
+ * https://lists.freedesktop.org/archives/mesa-dev/2018-April/193026.html
+ */
+ src[1] = nir_build_alu(&b->nb, nir_op_u2u32, src[1], NULL, NULL, NULL);
+ }
+ if (src[2]->bit_size != 32) {
+ /* Convert the Shift operand to 32 bits, which is the bitsize
+ * supported by the NIR instruction. See discussion here:
+ *
+ * https://lists.freedesktop.org/archives/mesa-dev/2018-April/193026.html
+ */
+ src[2] = nir_build_alu(&b->nb, nir_op_u2u32, src[2], NULL, NULL, NULL);
+ }
+ val->ssa->def = nir_build_alu(&b->nb, op, src[0], src[1], src[2], src[3]);
+ break;
+ }
+
case SpvOpShiftLeftLogical:
case SpvOpShiftRightArithmetic:
case SpvOpShiftRightLogical: {
--
2.14.1
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