[Mesa-dev] [PATCH 1/7] ac/surface: handle DCC subresource fast clear restriction on VI

[Nicolai Hähnle]

On 27.04.2018 19:23, Marek Olšák wrote:
> On Fri, Apr 27, 2018 at 4:14 AM, Nicolai Hähnle <nhaehnle at gmail.com 
> <mailto:nhaehnle at gmail.com>> wrote:
> 
>     Sorry, but I still don't understand the logic of this :/
> 
>     What we want to check for is that all the DCC bytes of a mip-level
>     are contiguous, right?
> 
>     Why does it matter for that whether a level is the last level?
> 
>     Here's the thought experiment that I can't make sense of: Let's say
>     that you have format, base level, and number of levels N so that the
>     last-level condition applies. That is, all levels up to and
>     including N-2 have dccRamAligned true. Level N-1 has dccRamAligned
>     false, but the patch as-is will still consider it fast-clearable.
> 
> 
> Yes, because the non-contiguous level N-1 DCC range (last level) doesn't 
> overlap with any existing level. It's interleaved with level N that 
> doesn't exist. So clearing the level N-1 DCC range that might overwrite 
> level N DCC range doesn't break anything and so the clear is allowed.
> 
> Is it clear now?

Yes. I was thinking that dccFastClearSize is the number of bytes 
belonging to the mip level that have to be cleared, but digging into 
AddrLib it is in fact a span like you describe (which potentially 
contains bytes that *don't* belong to the mip level). So the patch is 
okay as-is.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

> 
> Marek
> 


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