[Mesa-dev] [PATCH 1/4] nir: rename f2f16_undef to f2f16

[Karol Herbst]

we need rounding modes on other conversions involving floats and it is easier
to rename f2f16_undef than renaming all the other ones.

Signed-off-by: Karol Herbst <kherbst at redhat.com>
---
 src/compiler/nir/nir_opcodes.py   | 4 ++--
 src/compiler/nir/nir_opcodes_c.py | 8 ++++----
 src/intel/compiler/brw_fs_nir.cpp | 2 +-
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py
index 89a6c6becc2..7070f53adef 100644
--- a/src/compiler/nir/nir_opcodes.py
+++ b/src/compiler/nir/nir_opcodes.py
@@ -180,9 +180,9 @@ for src_t in [tint, tuint, tfloat]:
          bit_sizes = [8, 16, 32, 64]
       for bit_size in bit_sizes:
           if bit_size == 16 and dst_t == tfloat and src_t == tfloat:
-              rnd_modes = ['rtne', 'rtz', 'undef']
+              rnd_modes = ['_rtne', '_rtz', '']
               for rnd_mode in rnd_modes:
-                  unop_convert("{0}2{1}{2}_{3}".format(src_t[0], dst_t[0],
+                  unop_convert("{0}2{1}{2}{3}".format(src_t[0], dst_t[0],
                                                        bit_size, rnd_mode),
                                dst_t + str(bit_size), src_t, "src0")
           else:
diff --git a/src/compiler/nir/nir_opcodes_c.py b/src/compiler/nir/nir_opcodes_c.py
index 8afccca9504..3edf1d4c225 100644
--- a/src/compiler/nir/nir_opcodes_c.py
+++ b/src/compiler/nir/nir_opcodes_c.py
@@ -71,10 +71,10 @@ nir_type_conversion_op(nir_alu_type src, nir_alu_type dst, nir_rounding_mode rnd
                   case ${dst_bits}:
 %                    if src_t == 'float' and dst_t == 'float' and dst_bits == 16:
                      switch(rnd) {
-%                       for rnd_t in ['rtne', 'rtz', 'undef']:
-                        case nir_rounding_mode_${rnd_t}:
-                           return ${'nir_op_{0}2{1}{2}_{3}'.format(src_t[0], dst_t[0],
-                                                                   dst_bits, rnd_t)};
+%                       for rnd_t in [('rtne', '_rtne'), ('rtz', '_rtz'), ('undef', '')]:
+                        case nir_rounding_mode_${rnd_t[0]}:
+                           return ${'nir_op_{0}2{1}{2}{3}'.format(src_t[0], dst_t[0],
+                                                                   dst_bits, rnd_t[1])};
 %                       endfor
                         default:
                            unreachable("Invalid 16-bit nir rounding mode");
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 9698a0111ef..681f29ea761 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -753,7 +753,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
        * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
        */
 
-   case nir_op_f2f16_undef:
+   case nir_op_f2f16:
    case nir_op_i2i16:
    case nir_op_u2u16: {
       /* TODO: Fixing aligment rules for conversions from 32-bits to
-- 
2.14.3