[Mesa-dev] [PATCH] spirv: convert some operands for bitwise shift and bitwise ops to uint32
Samuel Iglesias Gonsálvez
siglesias at igalia.com
Mon Apr 30 10:12:21 UTC 2018
SPIR-V allows to define the shift, offset and count operands for
shift and bitfield opcodes with a bit-size different than 32 bits,
but in NIR the opcodes have that limitation. As agreed in the
mailing list, this patch adds a conversion to 32 bits to fix this.
For more info, see:
https://lists.freedesktop.org/archives/mesa-dev/2018-April/193026.html
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
---
src/compiler/spirv/vtn_alu.c | 47 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index 3134849ba90..36e5751bc05 100644
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src/compiler/spirv/vtn_alu.c
@@ -635,6 +635,53 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
break;
}
+ case SpvOpBitFieldInsert:
+ case SpvOpBitFieldSExtract:
+ case SpvOpBitFieldUExtract:
+ case SpvOpShiftLeftLogical:
+ case SpvOpShiftRightArithmetic:
+ case SpvOpShiftRightLogical: {
+ bool swap;
+ unsigned initial_source = 0;
+ unsigned src_bit_size = glsl_get_bit_size(vtn_src[0]->type);
+ unsigned dst_bit_size = glsl_get_bit_size(type);
+ nir_op op = vtn_nir_alu_op_for_spirv_opcode(b, opcode, &swap,
+ src_bit_size, dst_bit_size);
+
+ assert (op == nir_op_ushr || op == nir_op_ishr || op == nir_op_ishl ||
+ op == nir_op_bitfield_insert || op == nir_op_ubitfield_extract ||
+ op == nir_op_ibitfield_extract);
+
+ switch (op) {
+ case nir_op_ushr:
+ case nir_op_ishr:
+ case nir_op_ishl:
+ case nir_op_ubitfield_extract:
+ case nir_op_ibitfield_extract:
+ initial_source = 1;
+ break;
+ case nir_op_bitfield_insert:
+ initial_source = 2;
+ break;
+ default:
+ unreachable("Not supported opcode");
+ };
+ for (unsigned i = initial_source; i < nir_op_infos[op].num_inputs; i++) {
+ src_bit_size = nir_alu_type_get_type_size(nir_op_infos[op].input_types[i]);
+ assert(src_bit_size == 32);
+ if (src_bit_size && src_bit_size != src[i]->bit_size) {
+ /* Convert the Shift, Offset and Count operands to 32 bits, which is the bitsize
+ * supported by the NIR instructions. See discussion here:
+ *
+ * https://lists.freedesktop.org/archives/mesa-dev/2018-April/193026.html
+ */
+ src[i] = nir_u2u32(&b->nb, src[i]);
+ }
+ }
+ val->ssa->def = nir_build_alu(&b->nb, op, src[0], src[1], src[2], src[3]);
+ break;
+ }
+
default: {
bool swap;
unsigned src_bit_size = glsl_get_bit_size(vtn_src[0]->type);
--
2.14.1
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